Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Power saving features/services |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "AGESA.h" |
| 52 | #include "Ids.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "Gnb.h" |
| 55 | #include "GnbPcie.h" |
| 56 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 58 | #include "GnbRegistersON.h" |
| 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE |
| 61 | |
| 62 | /*---------------------------------------------------------------------------------------- |
| 63 | * D E F I N I T I O N S A N D M A C R O S |
| 64 | *---------------------------------------------------------------------------------------- |
| 65 | */ |
| 66 | |
| 67 | |
| 68 | /*---------------------------------------------------------------------------------------- |
| 69 | * T Y P E D E F S A N D S T R U C T U R E S |
| 70 | *---------------------------------------------------------------------------------------- |
| 71 | */ |
| 72 | |
| 73 | |
| 74 | /*---------------------------------------------------------------------------------------- |
| 75 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 76 | *---------------------------------------------------------------------------------------- |
| 77 | */ |
| 78 | |
| 79 | /*----------------------------------------------------------------------------------------*/ |
| 80 | /** |
| 81 | * Power down unused lanes and plls |
| 82 | * |
| 83 | * |
| 84 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 85 | * @param[in] Pcie Pointer to global PCIe configuration |
| 86 | */ |
| 87 | |
| 88 | VOID |
| 89 | PciePwrPowerDownUnusedLanes ( |
| 90 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 91 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 92 | ) |
| 93 | { |
| 94 | UINT32 UnusedLanes; |
| 95 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); |
| 96 | UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_ACTIVE, Wrapper, Pcie); |
| 97 | if (Wrapper->Features.PowerOffUnusedLanes != 0) { |
| 98 | PcieTopologyLaneControl ( |
| 99 | DisableLanes, |
| 100 | UnusedLanes, |
| 101 | Wrapper, |
| 102 | Pcie |
| 103 | ); |
| 104 | } |
| 105 | if (Wrapper->Features.PowerOffUnusedPlls != 0) { |
| 106 | PciePifPllPowerDown ( |
| 107 | UnusedLanes, |
| 108 | Wrapper, |
| 109 | Pcie |
| 110 | ); |
| 111 | } |
| 112 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); |
| 113 | } |
| 114 | |
| 115 | |
| 116 | /*----------------------------------------------------------------------------------------*/ |
| 117 | /** |
| 118 | * Lane bitmam to enable PLL power down in L1 |
| 119 | * |
| 120 | * |
| 121 | * @param[in] PllPowerUpLatency Pointer to wrapper config descriptor |
| 122 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 123 | * @param[in] Pcie Pointer to global PCIe configuration |
| 124 | * @retval Lane bitmap for which PLL can be powered down in L1 |
| 125 | */ |
| 126 | |
| 127 | UINT32 |
| 128 | PcieLanesToPowerDownPllInL1 ( |
| 129 | IN UINT8 PllPowerUpLatency, |
| 130 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 131 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 132 | ) |
| 133 | { |
| 134 | UINT8 LaneGroupExitLatency [4]; |
| 135 | UINT32 LaneBitmapForPllOffInL1; |
| 136 | PCIe_ENGINE_CONFIG *EngineList; |
| 137 | UINTN Index; |
| 138 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n"); |
| 139 | LaneBitmapForPllOffInL1 = 0; |
| 140 | if (Wrapper->Features.PllOffInL1 != 0) { |
| 141 | LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie)); |
| 142 | EngineList = PcieWrapperGetEngineList (Wrapper); |
| 143 | while (EngineList != NULL) { |
| 144 | PCIe_ASPM_LATENCY_INFO LinkLatencyInfo; |
| 145 | UINT32 ActiveLanesBitmap; |
| 146 | UINT32 HotplugLanesBitmap; |
| 147 | if (EngineList->EngineData.EngineType == PciePortEngine) { |
| 148 | LinkLatencyInfo.MaxL1ExitLatency = 0; |
| 149 | LinkLatencyInfo.MaxL0sExitLatency = 0; |
| 150 | ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_ACTIVE, 0, EngineList, Pcie); |
| 151 | HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_HOTPLUG, 0, EngineList, Pcie); |
| 152 | if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !EngineList->Type.Port.IsSB) { |
| 153 | PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie)); |
| 154 | } |
| 155 | if (HotplugLanesBitmap != 0 || EngineList->Type.Port.IsSB) { |
| 156 | LinkLatencyInfo.MaxL1ExitLatency = 0xff; |
| 157 | } |
| 158 | IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap); |
| 159 | for (Index = 0; Index < 4; Index++) { |
| 160 | if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { |
| 161 | if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { |
| 162 | IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); |
| 163 | LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; |
| 164 | } |
| 165 | } |
| 166 | } |
| 167 | } |
| 168 | EngineList = PcieLibGetNextDescriptor (EngineList); |
| 169 | } |
| 170 | LaneBitmapForPllOffInL1 = 0; |
| 171 | for (Index = 0; Index < 4; Index++) { |
| 172 | IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); |
| 173 | if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { |
| 174 | LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); |
| 175 | } |
| 176 | } |
| 177 | } |
| 178 | IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1); |
| 179 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n"); |
| 180 | return LaneBitmapForPllOffInL1; |
| 181 | } |
| 182 | |
| 183 | /*----------------------------------------------------------------------------------------*/ |
| 184 | /** |
| 185 | * Auto-Power Down electrical Idle detector |
| 186 | * |
| 187 | * |
| 188 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 189 | * @param[in] Pcie Pointer to global PCIe configuration |
| 190 | */ |
| 191 | |
| 192 | VOID |
| 193 | PciePwrAutoPowerDownElectricalIdleDetector ( |
| 194 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 195 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 196 | ) |
| 197 | { |
| 198 | UINT8 Pif; |
| 199 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n"); |
| 200 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 201 | PcieRegisterWriteField ( |
| 202 | Wrapper, |
| 203 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 204 | D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, |
| 205 | D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, |
| 206 | 0x0, |
| 207 | TRUE, |
| 208 | Pcie |
| 209 | ); |
| 210 | |
| 211 | PcieRegisterWriteField ( |
| 212 | Wrapper, |
| 213 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 214 | D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET, |
| 215 | D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH, |
| 216 | 0x2, |
| 217 | TRUE, |
| 218 | Pcie |
| 219 | ); |
| 220 | |
| 221 | PcieRegisterWriteField ( |
| 222 | Wrapper, |
| 223 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 224 | D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, |
| 225 | D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, |
| 226 | 0x1, |
| 227 | TRUE, |
| 228 | Pcie |
| 229 | ); |
| 230 | } |
| 231 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n"); |
| 232 | } |
| 233 | |
| 234 | /*----------------------------------------------------------------------------------------*/ |
| 235 | /** |
| 236 | * Clock gating |
| 237 | * |
| 238 | * |
| 239 | * |
| 240 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 241 | * @param[in] Pcie Pointer to global PCIe configuration |
| 242 | */ |
| 243 | |
| 244 | VOID |
| 245 | PciePwrClockGating ( |
| 246 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 247 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 248 | ) |
| 249 | { |
| 250 | D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; |
| 251 | D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; |
| 252 | D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; |
| 253 | D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; |
| 254 | UINT8 CoreId; |
| 255 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n"); |
| 256 | D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( |
| 257 | Wrapper, |
| 258 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), |
| 259 | Pcie |
| 260 | ); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 261 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 262 | D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( |
| 263 | Wrapper, |
| 264 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), |
| 265 | Pcie |
| 266 | ); |
| 267 | |
| 268 | D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( |
| 269 | Wrapper, |
| 270 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), |
| 271 | Pcie |
| 272 | ); |
| 273 | |
| 274 | if (Wrapper->Features.ClkGating == 0x1) { |
| 275 | D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; |
| 276 | D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; |
| 277 | |
| 278 | D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; |
| 279 | D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1; |
| 280 | |
| 281 | D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; |
| 282 | D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; |
| 283 | D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; |
| 284 | D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1; |
| 285 | D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; |
| 286 | D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f; |
| 287 | D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f; |
| 288 | D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f; |
| 289 | |
| 290 | D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7; |
| 291 | D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1; |
| 292 | D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1; |
| 293 | D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; |
| 294 | D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; |
| 295 | D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1; |
| 296 | } |
| 297 | if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { |
| 298 | D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; |
| 299 | } |
| 300 | PcieRegisterWrite ( |
| 301 | Wrapper, |
| 302 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), |
| 303 | D0F0xE4_WRAP_8014.Value, |
| 304 | TRUE, |
| 305 | Pcie |
| 306 | ); |
| 307 | PcieRegisterWrite ( |
| 308 | Wrapper, |
| 309 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), |
| 310 | D0F0xE4_WRAP_8012.Value, |
| 311 | TRUE, |
| 312 | Pcie |
| 313 | ); |
| 314 | PcieRegisterWrite ( |
| 315 | Wrapper, |
| 316 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), |
| 317 | D0F0xE4_WRAP_8011.Value, |
| 318 | TRUE, |
| 319 | Pcie |
| 320 | ); |
| 321 | for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { |
| 322 | PcieRegisterWriteField ( |
| 323 | Wrapper, |
| 324 | CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), |
| 325 | D0F0xE4_CORE_0011_DynClkLatency_OFFSET, |
| 326 | D0F0xE4_CORE_0011_DynClkLatency_WIDTH, |
| 327 | 0xf, |
| 328 | TRUE, |
| 329 | Pcie |
| 330 | ); |
| 331 | } |
| 332 | if (Wrapper->Features.LclkGating == 0x1) { |
| 333 | D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( |
| 334 | Wrapper, |
| 335 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), |
| 336 | Pcie |
| 337 | ); |
| 338 | D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; |
| 339 | D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; |
| 340 | PcieRegisterWrite ( |
| 341 | Wrapper, |
| 342 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), |
| 343 | D0F0xE4_WRAP_8016.Value, |
| 344 | TRUE, |
| 345 | Pcie |
| 346 | ); |
| 347 | } |
| 348 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n"); |
| 349 | } |
| 350 | |
| 351 | |