Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe port initialization service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "AGESA.h" |
| 52 | #include "Ids.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "Gnb.h" |
| 55 | #include "GnbPcie.h" |
| 56 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 58 | #include "GnbRegistersON.h" |
| 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | |
| 67 | /*---------------------------------------------------------------------------------------- |
| 68 | * T Y P E D E F S A N D S T R U C T U R E S |
| 69 | *---------------------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | /*----------------------------------------------------------------------------------------*/ |
| 79 | /** |
| 80 | * Set completion timeout |
| 81 | * |
| 82 | * |
| 83 | * |
| 84 | * @param[in] Engine Pointer to engine config descriptor |
| 85 | * @param[in] Pcie Pointer to global PCIe configuration |
| 86 | * |
| 87 | */ |
| 88 | |
| 89 | VOID |
| 90 | PcieCompletionTimeout ( |
| 91 | IN PCIe_ENGINE_CONFIG *Engine, |
| 92 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 93 | ) |
| 94 | { |
| 95 | GnbLibPciRMW ( |
| 96 | Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS, |
| 97 | AccessWidth32, |
| 98 | 0xffffffff, |
| 99 | 0x6 << DxF0x80_CplTimeoutValue_OFFSET, |
| 100 | GnbLibGetHeader (Pcie) |
| 101 | ); |
| 102 | if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { |
| 103 | PciePortRegisterWriteField ( |
| 104 | Engine, |
| 105 | DxF0xE4_x20_ADDRESS, |
| 106 | DxF0xE4_x20_TxFlushTlpDis_OFFSET, |
| 107 | DxF0xE4_x20_TxFlushTlpDis_WIDTH, |
| 108 | 0x0, |
| 109 | TRUE, |
| 110 | Pcie |
| 111 | ); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | /*----------------------------------------------------------------------------------------*/ |
| 116 | /** |
| 117 | * Init hotplug port |
| 118 | * |
| 119 | * |
| 120 | * |
| 121 | * @param[in] Engine Pointer to engine config descriptor |
| 122 | * @param[in] Pcie Pointer to global PCIe configuration |
| 123 | * |
| 124 | */ |
| 125 | |
| 126 | VOID |
| 127 | PcieLinkInitHotplug ( |
| 128 | IN PCIe_ENGINE_CONFIG *Engine, |
| 129 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 130 | ) |
| 131 | { |
| 132 | DxF0xE4_xB5_STRUCT DxF0xE4_xB5; |
| 133 | if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { |
| 134 | DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie); |
| 135 | DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3; |
| 136 | DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3; |
| 137 | DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; |
| 138 | PciePortRegisterWrite ( |
| 139 | Engine, |
| 140 | DxF0xE4_xB5_ADDRESS, |
| 141 | DxF0xE4_xB5.Value, |
| 142 | TRUE, |
| 143 | Pcie |
| 144 | ); |
| 145 | PcieRegisterWriteField ( |
| 146 | PcieEngineGetParentWrapper (Engine), |
Frank.Vibrans | 9c2fb60 | 2011-03-17 22:19:45 +0000 | [diff] [blame] | 147 | CORE_SPACE (Engine->Type.Port.CoreId, 0x10), |
| 148 | 1, |
| 149 | 3, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 150 | 0x5, |
| 151 | TRUE, |
| 152 | Pcie |
| 153 | ); |
| 154 | PcieRegisterWriteField ( |
| 155 | PcieEngineGetParentWrapper (Engine), |
| 156 | WRAP_SPACE (PcieEngineGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS), |
| 157 | D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET, |
| 158 | D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH, |
| 159 | 0x1, |
| 160 | TRUE, |
| 161 | Pcie |
| 162 | ); |
| 163 | } |
| 164 | if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { |
| 165 | GnbLibPciRMW ( |
| 166 | Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, |
| 167 | AccessS3SaveWidth32, |
| 168 | 0xffffffff, |
| 169 | 1 << DxF0x6C_HotplugCapable_OFFSET, |
| 170 | GnbLibGetHeader (Pcie) |
| 171 | ); |
| 172 | PciePortRegisterWriteField ( |
| 173 | Engine, |
| 174 | DxF0xE4_x20_ADDRESS, |
| 175 | DxF0xE4_x20_TxFlushTlpDis_OFFSET, |
| 176 | DxF0xE4_x20_TxFlushTlpDis_WIDTH, |
| 177 | 0x0, |
| 178 | TRUE, |
| 179 | Pcie |
| 180 | ); |
| 181 | PciePortRegisterWriteField ( |
| 182 | Engine, |
| 183 | DxF0xE4_x70_ADDRESS, |
| 184 | DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET, |
| 185 | DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH, |
| 186 | 0x1, |
| 187 | FALSE, |
| 188 | Pcie |
| 189 | ); |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | /*----------------------------------------------------------------------------------------*/ |
| 194 | /** |
| 195 | * Set misc slot capability |
| 196 | * |
| 197 | * |
| 198 | * |
| 199 | * @param[in] Engine Pointer to engine config descriptor |
| 200 | * @param[in] Pcie Pointer to global PCIe configuration |
| 201 | * |
| 202 | */ |
| 203 | |
| 204 | VOID |
| 205 | PcieLinkSetSlotCap ( |
| 206 | IN PCIe_ENGINE_CONFIG *Engine, |
| 207 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 208 | ) |
| 209 | { |
| 210 | GnbLibPciRMW ( |
| 211 | Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, |
| 212 | AccessWidth32, |
| 213 | 0xffffffff, |
| 214 | 1 << DxF0x58_SlotImplemented_OFFSET, |
| 215 | GnbLibGetHeader (Pcie) |
| 216 | ); |
| 217 | GnbLibPciRMW ( |
| 218 | Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, |
| 219 | AccessWidth32, |
| 220 | 0xffffffff, |
| 221 | 1 << DxF0x3C_IntPin_OFFSET, |
| 222 | GnbLibGetHeader (Pcie) |
| 223 | ); |
| 224 | } |
| 225 | |
| 226 | /*----------------------------------------------------------------------------------------*/ |
| 227 | /** |
| 228 | * Safe mode to force link advertize Gen1 only capability in TS |
| 229 | * |
| 230 | * |
| 231 | * |
| 232 | * @param[in] Engine Pointer to engine config descriptor |
| 233 | * @param[in] Pcie Pointer to global PCIe configuration |
| 234 | * |
| 235 | */ |
| 236 | |
| 237 | VOID |
| 238 | PcieLinkSafeMode ( |
| 239 | IN PCIe_ENGINE_CONFIG *Engine, |
| 240 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 241 | ) |
| 242 | { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 243 | PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); |
| 244 | PciePortRegisterRMW ( |
| 245 | Engine, |
| 246 | DxF0xE4_xA2_ADDRESS, |
| 247 | DxF0xE4_xA2_LcUpconfigureDis_MASK, |
| 248 | (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET), |
| 249 | FALSE, |
| 250 | Pcie |
| 251 | ); |
| 252 | } |
| 253 | |
| 254 | |
| 255 | /*----------------------------------------------------------------------------------------*/ |
| 256 | /** |
| 257 | * Set current link speed |
| 258 | * |
| 259 | * |
| 260 | * @param[in] Engine Pointer to engine configuration descriptor |
| 261 | * @param[in] Pcie Pointer to global PCIe configuration |
| 262 | * |
| 263 | */ |
| 264 | VOID |
| 265 | PcieSetLinkWidthCap ( |
| 266 | IN PCIe_ENGINE_CONFIG *Engine, |
| 267 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 268 | ) |
| 269 | { |
| 270 | PciePortRegisterRMW ( |
| 271 | Engine, |
| 272 | DxF0xE4_xA2_ADDRESS, |
| 273 | DxF0xE4_xA2_LcUpconfigureDis_MASK, |
| 274 | 0, |
| 275 | FALSE, |
| 276 | Pcie |
| 277 | ); |
| 278 | } |
| 279 | |
| 280 | /*----------------------------------------------------------------------------------------*/ |
| 281 | /** |
| 282 | * Set current link speed |
| 283 | * |
| 284 | * |
| 285 | * @param[in] LinkSpeedCapability Link Speed Capability |
| 286 | * @param[in] Engine Pointer to engine configuration descriptor |
| 287 | * @param[in] Pcie Pointer to global PCIe configuration |
| 288 | * |
| 289 | */ |
| 290 | VOID |
| 291 | PcieSetLinkSpeedCap ( |
| 292 | IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, |
| 293 | IN PCIe_ENGINE_CONFIG *Engine, |
| 294 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 295 | ) |
| 296 | { |
| 297 | DxF0xE4_xA4_STRUCT DxF0xE4_xA4; |
| 298 | DxF0xE4_xC0_STRUCT DxF0xE4_xC0; |
| 299 | DxF0x88_STRUCT DxF0x88; |
| 300 | GnbLibPciRead ( |
| 301 | Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| 302 | AccessWidth32, |
| 303 | &DxF0x88.Value, |
| 304 | GnbLibGetHeader (Pcie) |
| 305 | ); |
| 306 | DxF0xE4_xA4.Value = PciePortRegisterRead ( |
| 307 | Engine, |
| 308 | DxF0xE4_xA4_ADDRESS, |
| 309 | Pcie |
| 310 | ); |
| 311 | DxF0xE4_xC0.Value = PciePortRegisterRead ( |
| 312 | Engine, |
| 313 | DxF0xE4_xC0_ADDRESS, |
| 314 | Pcie |
| 315 | ); |
| 316 | |
| 317 | switch (LinkSpeedCapability) { |
| 318 | case PcieGen2: |
| 319 | DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1; |
| 320 | DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; |
| 321 | DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; |
| 322 | DxF0x88.Field.TargetLinkSpeed = 0x2; |
| 323 | DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; |
| 324 | break; |
| 325 | case PcieGen1: |
| 326 | DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0; |
| 327 | DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; |
| 328 | DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; |
| 329 | DxF0x88.Field.TargetLinkSpeed = 0x1; |
| 330 | DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; |
| 331 | PcieRegisterWriteField ( |
| 332 | PcieEngineGetParentWrapper (Engine), |
| 333 | WRAP_SPACE (PcieEngineGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), |
| 334 | D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, |
| 335 | D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, |
| 336 | 0, |
| 337 | FALSE, |
| 338 | Pcie |
| 339 | ); |
| 340 | break; |
| 341 | default: |
| 342 | ASSERT (FALSE); |
| 343 | break; |
| 344 | } |
| 345 | PciePortRegisterWrite ( |
| 346 | Engine, |
| 347 | DxF0xE4_xA4_ADDRESS, |
| 348 | DxF0xE4_xA4.Value, |
| 349 | FALSE, |
| 350 | Pcie |
| 351 | ); |
| 352 | PciePortRegisterWrite ( |
| 353 | Engine, |
| 354 | DxF0xE4_xC0_ADDRESS, |
| 355 | DxF0xE4_xC0.Value, |
| 356 | FALSE, |
| 357 | Pcie |
| 358 | ); |
| 359 | GnbLibPciWrite ( |
| 360 | Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| 361 | AccessWidth32, |
| 362 | &DxF0x88.Value, |
| 363 | GnbLibGetHeader (Pcie) |
| 364 | ); |
| 365 | } |
| 366 | |
| 367 | |
| 368 | /*----------------------------------------------------------------------------------------*/ |
| 369 | /** |
| 370 | * Force compliance |
| 371 | * |
| 372 | * |
| 373 | * |
| 374 | * @param[in] Engine Pointer to engine config descriptor |
| 375 | * @param[in] Pcie Pointer to global PCIe configuration |
| 376 | * |
| 377 | */ |
| 378 | |
| 379 | VOID |
| 380 | PcieForceCompliance ( |
| 381 | IN PCIe_ENGINE_CONFIG *Engine, |
| 382 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 383 | ) |
| 384 | { |
| 385 | if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { |
| 386 | GnbLibPciRMW ( |
| 387 | Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| 388 | AccessWidth32, |
| 389 | 0xffffffff, |
| 390 | 0x1 << DxF0x88_EnterCompliance_OFFSET, |
| 391 | GnbLibGetHeader (Pcie) |
| 392 | ); |
| 393 | } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { |
| 394 | PciePortRegisterWriteField ( |
| 395 | Engine, |
| 396 | DxF0xE4_xC0_ADDRESS, |
| 397 | DxF0xE4_xC0_StrapForceCompliance_OFFSET, |
| 398 | DxF0xE4_xC0_StrapForceCompliance_WIDTH, |
| 399 | 0x1, |
| 400 | FALSE, |
| 401 | Pcie |
| 402 | ); |
| 403 | } |
| 404 | } |
| 405 | |