Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Supporting services to access PCIe port indirect register |
| 6 | * space. |
| 7 | * |
| 8 | * |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: GNB |
| 13 | * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ |
| 14 | * |
| 15 | */ |
| 16 | /* |
| 17 | ***************************************************************************** |
| 18 | * |
| 19 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 20 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 21 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 22 | * Redistribution and use in source and binary forms, with or without |
| 23 | * modification, are permitted provided that the following conditions are met: |
| 24 | * * Redistributions of source code must retain the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer. |
| 26 | * * Redistributions in binary form must reproduce the above copyright |
| 27 | * notice, this list of conditions and the following disclaimer in the |
| 28 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 29 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 30 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 31 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 32 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 34 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 35 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 36 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 37 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 38 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 39 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 40 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 41 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 42 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 43 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 44 | * *************************************************************************** |
| 45 | * |
| 46 | */ |
| 47 | |
| 48 | /*---------------------------------------------------------------------------------------- |
| 49 | * M O D U L E S U S E D |
| 50 | *---------------------------------------------------------------------------------------- |
| 51 | */ |
| 52 | #include "AGESA.h" |
| 53 | #include "Ids.h" |
| 54 | #include "Gnb.h" |
| 55 | #include "GnbPcie.h" |
| 56 | #include "GnbPcieFamServices.h" |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 58 | #include "PciePortRegAcc.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | |
| 67 | /*---------------------------------------------------------------------------------------- |
| 68 | * T Y P E D E F S A N D S T R U C T U R E S |
| 69 | *---------------------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | |
| 79 | /*----------------------------------------------------------------------------------------*/ |
| 80 | /** |
| 81 | * Read PCIe port indirect register. |
| 82 | * |
| 83 | * Support for unify register access through index/data pair on PCIe port |
| 84 | * |
| 85 | * @param[in] Engine Pointer to Engine descriptor for this port |
| 86 | * @param[in] Address Register address |
| 87 | * @param[in] Pcie Pointer to internal configuration data area |
| 88 | * @retval Register Value |
| 89 | */ |
| 90 | |
| 91 | UINT32 |
| 92 | PciePortRegisterRead ( |
| 93 | IN PCIe_ENGINE_CONFIG *Engine, |
| 94 | IN UINT16 Address, |
| 95 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 96 | ) |
| 97 | { |
| 98 | UINT32 Value; |
| 99 | GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); |
| 100 | GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); |
| 101 | return Value; |
| 102 | } |
| 103 | |
| 104 | /*----------------------------------------------------------------------------------------*/ |
| 105 | /** |
| 106 | * Write PCIe Port Indirect register. |
| 107 | * |
| 108 | * Support for unify register access through index/data pair on GNB |
| 109 | * |
| 110 | * @param[in] Engine Pointer to Engine descriptor for this port |
| 111 | * @param[in] Address Register address |
| 112 | * @param[in] Value New register value |
| 113 | * @param[in] S3Save Save for S3 flag |
| 114 | * @param[in] Pcie Pointer to internal configuration data area |
| 115 | */ |
| 116 | VOID |
| 117 | PciePortRegisterWrite ( |
| 118 | IN PCIe_ENGINE_CONFIG *Engine, |
| 119 | IN UINT16 Address, |
| 120 | IN UINT32 Value, |
| 121 | IN BOOLEAN S3Save, |
| 122 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 123 | ) |
| 124 | { |
| 125 | ASSERT (S3Save == TRUE || S3Save == FALSE); |
| 126 | |
| 127 | IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, " *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n", |
| 128 | Engine->Type.Port.Address.Address.Bus, |
| 129 | Engine->Type.Port.Address.Address.Device, |
| 130 | Engine->Type.Port.Address.Address.Function, |
| 131 | Address, |
| 132 | Value |
| 133 | ); |
| 134 | GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); |
| 135 | GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); |
| 136 | } |
| 137 | |
| 138 | /*----------------------------------------------------------------------------------------*/ |
| 139 | /** |
| 140 | * Write PCIe Port Indirect register field. |
| 141 | * |
| 142 | * Support for unify register access through index/data pair on GNB |
| 143 | * |
| 144 | * @param[in] Engine Pointer to Engine descriptor for this port |
| 145 | * @param[in] Address Register address |
| 146 | * @param[in] FieldOffset Field offset |
| 147 | * @param[in] FieldWidth Field width |
| 148 | * @param[in] S3Save Save for S3 flag |
| 149 | * @param[in] Value New register value |
| 150 | * @param[in] Pcie Pointer to internal configuration data area |
| 151 | */ |
| 152 | |
| 153 | VOID |
| 154 | PciePortRegisterWriteField ( |
| 155 | IN PCIe_ENGINE_CONFIG *Engine, |
| 156 | IN UINT16 Address, |
| 157 | IN UINT8 FieldOffset, |
| 158 | IN UINT8 FieldWidth, |
| 159 | IN UINT32 Value, |
| 160 | IN BOOLEAN S3Save, |
| 161 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 162 | ) |
| 163 | { |
| 164 | UINT32 Data; |
| 165 | UINT32 Mask; |
| 166 | Data = PciePortRegisterRead (Engine, Address, Pcie); |
| 167 | Mask = (1 << FieldWidth) - 1; |
| 168 | Value &= Mask; |
| 169 | Data &= (~(Mask << FieldOffset)); |
| 170 | PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie); |
| 171 | } |
| 172 | |
| 173 | /*----------------------------------------------------------------------------------------*/ |
| 174 | /** |
| 175 | * Write PCIe Port Indirect register field. |
| 176 | * |
| 177 | * Support for unify register access through index/data pair on GNB |
| 178 | * |
| 179 | * @param[in] Engine Pointer to Engine descriptor for this port |
| 180 | * @param[in] Address Register address |
| 181 | * @param[in] FieldOffset Field offset |
| 182 | * @param[in] FieldWidth Field width |
| 183 | * @param[in] Pcie Pointer to internal configuration data area |
| 184 | * @retval Register Field Value. |
| 185 | */ |
| 186 | |
| 187 | UINT32 |
| 188 | PciePortRegisterReadField ( |
| 189 | IN PCIe_ENGINE_CONFIG *Engine, |
| 190 | IN UINT16 Address, |
| 191 | IN UINT8 FieldOffset, |
| 192 | IN UINT8 FieldWidth, |
| 193 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 194 | ) |
| 195 | { |
| 196 | UINT32 Value; |
| 197 | Value = PciePortRegisterRead (Engine, Address, Pcie); |
| 198 | Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1); |
| 199 | return Value; |
| 200 | } |
| 201 | |
| 202 | /*----------------------------------------------------------------------------------------*/ |
| 203 | /** |
| 204 | * Read/Modify/Write PCIe port register. |
| 205 | * |
| 206 | * Support for unify register access through index/data pair on GNB |
| 207 | * |
| 208 | * @param[in] Engine Pointer to Engine descriptor for this port |
| 209 | * @param[in] Address Register address |
| 210 | * @param[in] AndMask Value & (~AndMask) |
| 211 | * @param[in] OrMask Value | OrMask |
| 212 | * @param[in] S3Save Save register for S3 (True/False) |
| 213 | * @param[in] Pcie Pointer to global PCIe configuration |
| 214 | */ |
| 215 | |
| 216 | VOID |
| 217 | PciePortRegisterRMW ( |
| 218 | IN PCIe_ENGINE_CONFIG *Engine, |
| 219 | IN UINT16 Address, |
| 220 | IN UINT32 AndMask, |
| 221 | IN UINT32 OrMask, |
| 222 | IN BOOLEAN S3Save, |
| 223 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 224 | ) |
| 225 | { |
| 226 | UINT32 Value; |
| 227 | Value = PciePortRegisterRead (Engine, Address, Pcie); |
| 228 | Value = (Value & (~AndMask)) | OrMask; |
| 229 | PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie); |
| 230 | } |
| 231 | |