Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe PIF initialization routine |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | |
| 51 | #include "AGESA.h" |
| 52 | #include "Ids.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "Gnb.h" |
| 55 | #include "GnbPcie.h" |
| 56 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 58 | #include "GnbRegistersON.h" |
| 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | #define MAX_NUM_PHYs 2 |
| 67 | #define MAX_NUM_LANE_PER_PHY 8 |
| 68 | |
| 69 | /*---------------------------------------------------------------------------------------- |
| 70 | * T Y P E D E F S A N D S T R U C T U R E S |
| 71 | *---------------------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | |
| 75 | /*---------------------------------------------------------------------------------------- |
| 76 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 77 | *---------------------------------------------------------------------------------------- |
| 78 | */ |
| 79 | |
| 80 | |
| 81 | /*---------------------------------------------------------------------------------------- |
| 82 | * E X P O R T E D F U N C T I O N S |
| 83 | *---------------------------------------------------------------------------------------- |
| 84 | */ |
| 85 | |
| 86 | |
| 87 | /*----------------------------------------------------------------------------------------*/ |
| 88 | /** |
| 89 | * PHY lane ganging |
| 90 | * |
| 91 | * |
| 92 | * |
| 93 | * @param[out] Wrapper Pointer to internal configuration data area |
| 94 | * @param[in] Pcie Pointer to global PCIe configuration |
| 95 | */ |
| 96 | VOID |
| 97 | PciePhyApplyGanging ( |
| 98 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 99 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 100 | ) |
| 101 | { |
| 102 | PCIe_ENGINE_CONFIG *EngineList; |
| 103 | UINT8 GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; |
| 104 | UINT8 MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; |
| 105 | UINT16 LoPhylane; |
| 106 | UINT16 HiPhylane; |
| 107 | UINT8 Phy; |
| 108 | UINT16 Lane; |
| 109 | UINT16 PhyLinkWidth; |
| 110 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n"); |
| 111 | LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie)); |
| 112 | LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie)); |
| 113 | EngineList = PcieWrapperGetEngineList (Wrapper); |
| 114 | while (EngineList != NULL) { |
| 115 | if (PcieLibIsEngineAllocated (EngineList)) { |
| 116 | HiPhylane = PcieUtilGetHiPhyLane (EngineList) - Wrapper->StartPhyLane; |
| 117 | LoPhylane = PcieUtilGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; |
| 118 | PhyLinkWidth = HiPhylane - LoPhylane + 1; |
| 119 | |
| 120 | if (PhyLinkWidth >= 8) { |
| 121 | for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) { |
| 122 | ((UINT8 *) GangMatrix)[Lane] = 1; |
| 123 | } |
| 124 | } else { |
| 125 | if (PhyLinkWidth > 0 && PhyLinkWidth < 4) { |
| 126 | for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) { |
| 127 | ((UINT8 *) MasterMatrix)[Lane] = 1; |
| 128 | } |
| 129 | } |
| 130 | } |
| 131 | } |
| 132 | EngineList = PcieLibGetNextDescriptor (EngineList); |
| 133 | } |
| 134 | for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { |
| 135 | for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) { |
| 136 | D0F0xE4_PHY_6005_STRUCT D0F0xE4_PHY_6005; |
| 137 | D0F0xE4_PHY_6005.Value = PcieRegisterRead ( |
| 138 | Wrapper, |
| 139 | PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), |
| 140 | Pcie |
| 141 | ); |
| 142 | D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane]; |
| 143 | D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane]; |
| 144 | PcieRegisterWrite ( |
| 145 | Wrapper, |
| 146 | PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), |
| 147 | D0F0xE4_PHY_6005.Value, |
| 148 | FALSE, |
| 149 | Pcie |
| 150 | ); |
| 151 | } |
| 152 | } |
| 153 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n"); |
| 154 | } |
| 155 | |
| 156 | |
| 157 | /*----------------------------------------------------------------------------------------*/ |
| 158 | /** |
| 159 | * Point "virtual" PLL clock picker away from PCIe |
| 160 | * |
| 161 | * |
| 162 | * |
| 163 | * @param[in] Wrapper Pointer to internal configuration data area |
| 164 | * @param[in] Pcie Pointer to global PCIe configuration |
| 165 | */ |
| 166 | VOID |
| 167 | PciePhyAvertClockPickers ( |
| 168 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 169 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 170 | ) |
| 171 | { |
| 172 | UINT32 DdiLanes; |
| 173 | UINT8 Nibble; |
| 174 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n"); |
| 175 | DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ALLOCATED, 0, Wrapper, Pcie); |
| 176 | for (Nibble = 0; Nibble < 4; Nibble++) { |
| 177 | if (DdiLanes & (0xf << (Nibble * 4))) { |
| 178 | PcieRegisterRMW ( |
| 179 | Wrapper, |
| 180 | PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)), |
| 181 | D0F0xE4_PHY_0009_PCIePllSel_MASK, |
| 182 | 0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET, |
| 183 | FALSE, |
| 184 | Pcie |
| 185 | ); |
| 186 | PcieRegisterRMW ( |
| 187 | Wrapper, |
| 188 | PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)), |
| 189 | D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK, |
| 190 | (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET), |
| 191 | FALSE, |
| 192 | Pcie |
| 193 | ); |
| 194 | } |
| 195 | } |
| 196 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n"); |
| 197 | } |