| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Register definitions |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision:$ @e \$Date:$ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 20 | * |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 31 | * |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 42 | * |
| 43 | *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _GNBREGISTERSON_H_ |
| 48 | #define _GNBREGISTERSON_H_ |
| 49 | #define TYPE_D0F0 0x1 |
| 50 | #define TYPE_D0F0x64 0x2 |
| 51 | #define TYPE_D0F0x98 0x3 |
| 52 | #define TYPE_D0F0xE4 0x5 |
| 53 | #define TYPE_DxF0 0x6 |
| 54 | #define TYPE_DxF0xE4 0x7 |
| 55 | #define TYPE_D18F1 0xb |
| 56 | #define TYPE_D18F2 0xc |
| 57 | #define TYPE_D18F3 0xd |
| 58 | #define TYPE_MSR 0x10 |
| 59 | #define TYPE_D1F0 0x11 |
| 60 | #define TYPE_GMM 0x12 |
| 61 | #define D18F2x9C 0xe |
| 62 | #define GMM 0x11 |
| 63 | #ifndef WRAP_SPACE |
| 64 | #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) |
| 65 | #endif |
| 66 | #ifndef CORE_SPACE |
| 67 | #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) |
| 68 | #endif |
| 69 | #ifndef PHY_SPACE |
| 70 | #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) |
| 71 | #endif |
| 72 | #ifndef PIF_SPACE |
| 73 | #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) |
| 74 | #endif |
| 75 | // **** D0F0x00 Register Definition **** |
| 76 | // Address |
| 77 | #define D0F0x00_ADDRESS 0x0 |
| 78 | |
| 79 | // Type |
| 80 | #define D0F0x00_TYPE TYPE_D0F0 |
| 81 | // Field Data |
| 82 | #define D0F0x00_VendorID_OFFSET 0 |
| 83 | #define D0F0x00_VendorID_WIDTH 16 |
| 84 | #define D0F0x00_VendorID_MASK 0xffff |
| 85 | #define D0F0x00_DeviceID_OFFSET 16 |
| 86 | #define D0F0x00_DeviceID_WIDTH 16 |
| 87 | #define D0F0x00_DeviceID_MASK 0xffff0000 |
| 88 | |
| 89 | /// D0F0x00 |
| 90 | typedef union { |
| 91 | struct { ///< |
| 92 | UINT32 VendorID:16; ///< |
| 93 | UINT32 DeviceID:16; ///< |
| 94 | } Field; ///< |
| 95 | UINT32 Value; ///< |
| 96 | } D0F0x00_STRUCT; |
| 97 | |
| 98 | // **** D0F0x04 Register Definition **** |
| 99 | // Address |
| 100 | #define D0F0x04_ADDRESS 0x4 |
| 101 | |
| 102 | // Type |
| 103 | #define D0F0x04_TYPE TYPE_D0F0 |
| 104 | // Field Data |
| 105 | #define D0F0x04_IoAccessEn_OFFSET 0 |
| 106 | #define D0F0x04_IoAccessEn_WIDTH 1 |
| 107 | #define D0F0x04_IoAccessEn_MASK 0x1 |
| 108 | #define D0F0x04_MemAccessEn_OFFSET 1 |
| 109 | #define D0F0x04_MemAccessEn_WIDTH 1 |
| 110 | #define D0F0x04_MemAccessEn_MASK 0x2 |
| 111 | #define D0F0x04_BusMasterEn_OFFSET 2 |
| 112 | #define D0F0x04_BusMasterEn_WIDTH 1 |
| 113 | #define D0F0x04_BusMasterEn_MASK 0x4 |
| 114 | #define D0F0x04_SpecialCycleEn_OFFSET 3 |
| 115 | #define D0F0x04_SpecialCycleEn_WIDTH 1 |
| 116 | #define D0F0x04_SpecialCycleEn_MASK 0x8 |
| 117 | #define D0F0x04_MemWriteInvalidateEn_OFFSET 4 |
| 118 | #define D0F0x04_MemWriteInvalidateEn_WIDTH 1 |
| 119 | #define D0F0x04_MemWriteInvalidateEn_MASK 0x10 |
| 120 | #define D0F0x04_PalSnoopEn_OFFSET 5 |
| 121 | #define D0F0x04_PalSnoopEn_WIDTH 1 |
| 122 | #define D0F0x04_PalSnoopEn_MASK 0x20 |
| 123 | #define D0F0x04_ParityErrorEn_OFFSET 6 |
| 124 | #define D0F0x04_ParityErrorEn_WIDTH 1 |
| 125 | #define D0F0x04_ParityErrorEn_MASK 0x40 |
| 126 | #define D0F0x04_Reserved_7_7_OFFSET 7 |
| 127 | #define D0F0x04_Reserved_7_7_WIDTH 1 |
| 128 | #define D0F0x04_Reserved_7_7_MASK 0x80 |
| 129 | #define D0F0x04_SerrEn_OFFSET 8 |
| 130 | #define D0F0x04_SerrEn_WIDTH 1 |
| 131 | #define D0F0x04_SerrEn_MASK 0x100 |
| 132 | #define D0F0x04_FastB2BEn_OFFSET 9 |
| 133 | #define D0F0x04_FastB2BEn_WIDTH 1 |
| 134 | #define D0F0x04_FastB2BEn_MASK 0x200 |
| 135 | #define D0F0x04_Reserved_19_10_OFFSET 10 |
| 136 | #define D0F0x04_Reserved_19_10_WIDTH 10 |
| 137 | #define D0F0x04_Reserved_19_10_MASK 0xffc00 |
| 138 | #define D0F0x04_CapList_OFFSET 20 |
| 139 | #define D0F0x04_CapList_WIDTH 1 |
| 140 | #define D0F0x04_CapList_MASK 0x100000 |
| 141 | #define D0F0x04_PCI66En_OFFSET 21 |
| 142 | #define D0F0x04_PCI66En_WIDTH 1 |
| 143 | #define D0F0x04_PCI66En_MASK 0x200000 |
| 144 | #define D0F0x04_Reserved_22_22_OFFSET 22 |
| 145 | #define D0F0x04_Reserved_22_22_WIDTH 1 |
| 146 | #define D0F0x04_Reserved_22_22_MASK 0x400000 |
| 147 | #define D0F0x04_FastBackCapable_OFFSET 23 |
| 148 | #define D0F0x04_FastBackCapable_WIDTH 1 |
| 149 | #define D0F0x04_FastBackCapable_MASK 0x800000 |
| 150 | #define D0F0x04_Reserved_24_24_OFFSET 24 |
| 151 | #define D0F0x04_Reserved_24_24_WIDTH 1 |
| 152 | #define D0F0x04_Reserved_24_24_MASK 0x1000000 |
| 153 | #define D0F0x04_DevselTiming_OFFSET 25 |
| 154 | #define D0F0x04_DevselTiming_WIDTH 2 |
| 155 | #define D0F0x04_DevselTiming_MASK 0x6000000 |
| 156 | #define D0F0x04_SignalTargetAbort_OFFSET 27 |
| 157 | #define D0F0x04_SignalTargetAbort_WIDTH 1 |
| 158 | #define D0F0x04_SignalTargetAbort_MASK 0x8000000 |
| 159 | #define D0F0x04_ReceivedTargetAbort_OFFSET 28 |
| 160 | #define D0F0x04_ReceivedTargetAbort_WIDTH 1 |
| 161 | #define D0F0x04_ReceivedTargetAbort_MASK 0x10000000 |
| 162 | #define D0F0x04_ReceivedMasterAbort_OFFSET 29 |
| 163 | #define D0F0x04_ReceivedMasterAbort_WIDTH 1 |
| 164 | #define D0F0x04_ReceivedMasterAbort_MASK 0x20000000 |
| 165 | #define D0F0x04_SignaledSystemError_OFFSET 30 |
| 166 | #define D0F0x04_SignaledSystemError_WIDTH 1 |
| 167 | #define D0F0x04_SignaledSystemError_MASK 0x40000000 |
| 168 | #define D0F0x04_ParityErrorDetected_OFFSET 31 |
| 169 | #define D0F0x04_ParityErrorDetected_WIDTH 1 |
| 170 | #define D0F0x04_ParityErrorDetected_MASK 0x80000000 |
| 171 | |
| 172 | /// D0F0x04 |
| 173 | typedef union { |
| 174 | struct { ///< |
| 175 | UINT32 IoAccessEn:1 ; ///< |
| 176 | UINT32 MemAccessEn:1 ; ///< |
| 177 | UINT32 BusMasterEn:1 ; ///< |
| 178 | UINT32 SpecialCycleEn:1 ; ///< |
| 179 | UINT32 MemWriteInvalidateEn:1 ; ///< |
| 180 | UINT32 PalSnoopEn:1 ; ///< |
| 181 | UINT32 ParityErrorEn:1 ; ///< |
| 182 | UINT32 Reserved_7_7:1 ; ///< |
| 183 | UINT32 SerrEn:1 ; ///< |
| 184 | UINT32 FastB2BEn:1 ; ///< |
| 185 | UINT32 Reserved_19_10:10; ///< |
| 186 | UINT32 CapList:1 ; ///< |
| 187 | UINT32 PCI66En:1 ; ///< |
| 188 | UINT32 Reserved_22_22:1 ; ///< |
| 189 | UINT32 FastBackCapable:1 ; ///< |
| 190 | UINT32 Reserved_24_24:1 ; ///< |
| 191 | UINT32 DevselTiming:2 ; ///< |
| 192 | UINT32 SignalTargetAbort:1 ; ///< |
| 193 | UINT32 ReceivedTargetAbort:1 ; ///< |
| 194 | UINT32 ReceivedMasterAbort:1 ; ///< |
| 195 | UINT32 SignaledSystemError:1 ; ///< |
| 196 | UINT32 ParityErrorDetected:1 ; ///< |
| 197 | } Field; ///< |
| 198 | UINT32 Value; ///< |
| 199 | } D0F0x04_STRUCT; |
| 200 | |
| 201 | // **** D0F0x08 Register Definition **** |
| 202 | // Address |
| 203 | #define D0F0x08_ADDRESS 0x8 |
| 204 | |
| 205 | // Type |
| 206 | #define D0F0x08_TYPE TYPE_D0F0 |
| 207 | // Field Data |
| 208 | #define D0F0x08_RevID_OFFSET 0 |
| 209 | #define D0F0x08_RevID_WIDTH 8 |
| 210 | #define D0F0x08_RevID_MASK 0xff |
| 211 | #define D0F0x08_ClassCode_OFFSET 8 |
| 212 | #define D0F0x08_ClassCode_WIDTH 24 |
| 213 | #define D0F0x08_ClassCode_MASK 0xffffff00 |
| 214 | |
| 215 | /// D0F0x08 |
| 216 | typedef union { |
| 217 | struct { ///< |
| 218 | UINT32 RevID:8 ; ///< |
| 219 | UINT32 ClassCode:24; ///< |
| 220 | } Field; ///< |
| 221 | UINT32 Value; ///< |
| 222 | } D0F0x08_STRUCT; |
| 223 | |
| 224 | // **** D0F0x0C Register Definition **** |
| 225 | // Address |
| 226 | #define D0F0x0C_ADDRESS 0xc |
| 227 | |
| 228 | // Type |
| 229 | #define D0F0x0C_TYPE TYPE_D0F0 |
| 230 | // Field Data |
| 231 | #define D0F0x0C_CacheLineSize_OFFSET 0 |
| 232 | #define D0F0x0C_CacheLineSize_WIDTH 8 |
| 233 | #define D0F0x0C_CacheLineSize_MASK 0xff |
| 234 | #define D0F0x0C_LatencyTimer_OFFSET 8 |
| 235 | #define D0F0x0C_LatencyTimer_WIDTH 8 |
| 236 | #define D0F0x0C_LatencyTimer_MASK 0xff00 |
| 237 | #define D0F0x0C_HeaderTypeReg_OFFSET 16 |
| 238 | #define D0F0x0C_HeaderTypeReg_WIDTH 8 |
| 239 | #define D0F0x0C_HeaderTypeReg_MASK 0xff0000 |
| 240 | #define D0F0x0C_BIST_OFFSET 24 |
| 241 | #define D0F0x0C_BIST_WIDTH 8 |
| 242 | #define D0F0x0C_BIST_MASK 0xff000000 |
| 243 | |
| 244 | /// D0F0x0C |
| 245 | typedef union { |
| 246 | struct { ///< |
| 247 | UINT32 CacheLineSize:8 ; ///< |
| 248 | UINT32 LatencyTimer:8 ; ///< |
| 249 | UINT32 HeaderTypeReg:8 ; ///< |
| 250 | UINT32 BIST:8 ; ///< |
| 251 | } Field; ///< |
| 252 | UINT32 Value; ///< |
| 253 | } D0F0x0C_STRUCT; |
| 254 | |
| 255 | // **** D0F0x2C Register Definition **** |
| 256 | // Address |
| 257 | #define D0F0x2C_ADDRESS 0x2c |
| 258 | |
| 259 | // Type |
| 260 | #define D0F0x2C_TYPE TYPE_D0F0 |
| 261 | // Field Data |
| 262 | #define D0F0x2C_SubsystemVendorID_OFFSET 0 |
| 263 | #define D0F0x2C_SubsystemVendorID_WIDTH 16 |
| 264 | #define D0F0x2C_SubsystemVendorID_MASK 0xffff |
| 265 | #define D0F0x2C_SubsystemID_OFFSET 16 |
| 266 | #define D0F0x2C_SubsystemID_WIDTH 16 |
| 267 | #define D0F0x2C_SubsystemID_MASK 0xffff0000 |
| 268 | |
| 269 | /// D0F0x2C |
| 270 | typedef union { |
| 271 | struct { ///< |
| 272 | UINT32 SubsystemVendorID:16; ///< |
| 273 | UINT32 SubsystemID:16; ///< |
| 274 | } Field; ///< |
| 275 | UINT32 Value; ///< |
| 276 | } D0F0x2C_STRUCT; |
| 277 | |
| 278 | // **** D0F0x34 Register Definition **** |
| 279 | // Address |
| 280 | #define D0F0x34_ADDRESS 0x34 |
| 281 | |
| 282 | // Type |
| 283 | #define D0F0x34_TYPE TYPE_D0F0 |
| 284 | // Field Data |
| 285 | #define D0F0x34_CapPtr_OFFSET 0 |
| 286 | #define D0F0x34_CapPtr_WIDTH 8 |
| 287 | #define D0F0x34_CapPtr_MASK 0xff |
| 288 | #define D0F0x34_Reserved_31_8_OFFSET 8 |
| 289 | #define D0F0x34_Reserved_31_8_WIDTH 24 |
| 290 | #define D0F0x34_Reserved_31_8_MASK 0xffffff00 |
| 291 | |
| 292 | /// D0F0x34 |
| 293 | typedef union { |
| 294 | struct { ///< |
| 295 | UINT32 CapPtr:8 ; ///< |
| 296 | UINT32 Reserved_31_8:24; ///< |
| 297 | } Field; ///< |
| 298 | UINT32 Value; ///< |
| 299 | } D0F0x34_STRUCT; |
| 300 | |
| 301 | // **** D0F0x4C Register Definition **** |
| 302 | // Address |
| 303 | #define D0F0x4C_ADDRESS 0x4c |
| 304 | |
| 305 | // Type |
| 306 | #define D0F0x4C_TYPE TYPE_D0F0 |
| 307 | // Field Data |
| 308 | #define D0F0x4C_Function1Enable_OFFSET 0 |
| 309 | #define D0F0x4C_Function1Enable_WIDTH 1 |
| 310 | #define D0F0x4C_Function1Enable_MASK 0x1 |
| 311 | #define D0F0x4C_ApicEnable_OFFSET 1 |
| 312 | #define D0F0x4C_ApicEnable_WIDTH 1 |
| 313 | #define D0F0x4C_ApicEnable_MASK 0x2 |
| 314 | #define D0F0x4C_Reserved_2_2_OFFSET 2 |
| 315 | #define D0F0x4C_Reserved_2_2_WIDTH 1 |
| 316 | #define D0F0x4C_Reserved_2_2_MASK 0x4 |
| 317 | #define D0F0x4C_Cf8Dis_OFFSET 3 |
| 318 | #define D0F0x4C_Cf8Dis_WIDTH 1 |
| 319 | #define D0F0x4C_Cf8Dis_MASK 0x8 |
| 320 | #define D0F0x4C_PMEDis_OFFSET 4 |
| 321 | #define D0F0x4C_PMEDis_WIDTH 1 |
| 322 | #define D0F0x4C_PMEDis_MASK 0x10 |
| 323 | #define D0F0x4C_SerrDis_OFFSET 5 |
| 324 | #define D0F0x4C_SerrDis_WIDTH 1 |
| 325 | #define D0F0x4C_SerrDis_MASK 0x20 |
| 326 | #define D0F0x4C_Reserved_10_6_OFFSET 6 |
| 327 | #define D0F0x4C_Reserved_10_6_WIDTH 5 |
| 328 | #define D0F0x4C_Reserved_10_6_MASK 0x7c0 |
| 329 | #define D0F0x4C_CRS_OFFSET 11 |
| 330 | #define D0F0x4C_CRS_WIDTH 1 |
| 331 | #define D0F0x4C_CRS_MASK 0x800 |
| 332 | #define D0F0x4C_CfgRdTime_OFFSET 12 |
| 333 | #define D0F0x4C_CfgRdTime_WIDTH 3 |
| 334 | #define D0F0x4C_CfgRdTime_MASK 0x7000 |
| 335 | #define D0F0x4C_Reserved_22_15_OFFSET 15 |
| 336 | #define D0F0x4C_Reserved_22_15_WIDTH 8 |
| 337 | #define D0F0x4C_Reserved_22_15_MASK 0x7f8000 |
| 338 | #define D0F0x4C_MMIOEnable_OFFSET 23 |
| 339 | #define D0F0x4C_MMIOEnable_WIDTH 1 |
| 340 | #define D0F0x4C_MMIOEnable_MASK 0x800000 |
| 341 | #define D0F0x4C_Reserved_25_24_OFFSET 24 |
| 342 | #define D0F0x4C_Reserved_25_24_WIDTH 2 |
| 343 | #define D0F0x4C_Reserved_25_24_MASK 0x3000000 |
| 344 | #define D0F0x4C_HPDis_OFFSET 26 |
| 345 | #define D0F0x4C_HPDis_WIDTH 1 |
| 346 | #define D0F0x4C_HPDis_MASK 0x4000000 |
| 347 | #define D0F0x4C_Reserved_31_27_OFFSET 27 |
| 348 | #define D0F0x4C_Reserved_31_27_WIDTH 5 |
| 349 | #define D0F0x4C_Reserved_31_27_MASK 0xf8000000 |
| 350 | |
| 351 | /// D0F0x4C |
| 352 | typedef union { |
| 353 | struct { ///< |
| 354 | UINT32 Function1Enable:1 ; ///< |
| 355 | UINT32 ApicEnable:1 ; ///< |
| 356 | UINT32 Reserved_2_2:1 ; ///< |
| 357 | UINT32 Cf8Dis:1 ; ///< |
| 358 | UINT32 PMEDis:1 ; ///< |
| 359 | UINT32 SerrDis:1 ; ///< |
| 360 | UINT32 Reserved_10_6:5 ; ///< |
| 361 | UINT32 CRS:1 ; ///< |
| 362 | UINT32 CfgRdTime:3 ; ///< |
| 363 | UINT32 Reserved_22_15:8 ; ///< |
| 364 | UINT32 MMIOEnable:1 ; ///< |
| 365 | UINT32 Reserved_25_24:2 ; ///< |
| 366 | UINT32 HPDis:1 ; ///< |
| 367 | UINT32 Reserved_31_27:5 ; ///< |
| 368 | } Field; ///< |
| 369 | UINT32 Value; ///< |
| 370 | } D0F0x4C_STRUCT; |
| 371 | |
| 372 | // **** D0F0x60 Register Definition **** |
| 373 | // Address |
| 374 | #define D0F0x60_ADDRESS 0x60 |
| 375 | |
| 376 | // Type |
| 377 | #define D0F0x60_TYPE TYPE_D0F0 |
| 378 | // Field Data |
| 379 | #define D0F0x60_MiscIndAddr_OFFSET 0 |
| 380 | #define D0F0x60_MiscIndAddr_WIDTH 7 |
| 381 | #define D0F0x60_MiscIndAddr_MASK 0x7f |
| 382 | #define D0F0x60_MiscIndWrEn_OFFSET 7 |
| 383 | #define D0F0x60_MiscIndWrEn_WIDTH 1 |
| 384 | #define D0F0x60_MiscIndWrEn_MASK 0x80 |
| 385 | #define D0F0x60_Reserved_31_8_OFFSET 8 |
| 386 | #define D0F0x60_Reserved_31_8_WIDTH 24 |
| 387 | #define D0F0x60_Reserved_31_8_MASK 0xffffff00 |
| 388 | |
| 389 | /// D0F0x60 |
| 390 | typedef union { |
| 391 | struct { ///< |
| 392 | UINT32 MiscIndAddr:7 ; ///< |
| 393 | UINT32 MiscIndWrEn:1 ; ///< |
| 394 | UINT32 Reserved_31_8:24; ///< |
| 395 | } Field; ///< |
| 396 | UINT32 Value; ///< |
| 397 | } D0F0x60_STRUCT; |
| 398 | |
| 399 | // **** D0F0x64 Register Definition **** |
| 400 | // Address |
| 401 | #define D0F0x64_ADDRESS 0x64 |
| 402 | |
| 403 | // Type |
| 404 | #define D0F0x64_TYPE TYPE_D0F0 |
| 405 | // Field Data |
| 406 | #define D0F0x64_MiscIndData_OFFSET 0 |
| 407 | #define D0F0x64_MiscIndData_WIDTH 32 |
| 408 | #define D0F0x64_MiscIndData_MASK 0xffffffff |
| 409 | |
| 410 | /// D0F0x64 |
| 411 | typedef union { |
| 412 | struct { ///< |
| 413 | UINT32 MiscIndData:32; ///< |
| 414 | } Field; ///< |
| 415 | UINT32 Value; ///< |
| 416 | } D0F0x64_STRUCT; |
| 417 | |
| 418 | // **** D0F0x78 Register Definition **** |
| 419 | // Address |
| 420 | #define D0F0x78_ADDRESS 0x78 |
| 421 | |
| 422 | // Type |
| 423 | #define D0F0x78_TYPE TYPE_D0F0 |
| 424 | // Field Data |
| 425 | #define D0F0x78_Scratch_OFFSET 0 |
| 426 | #define D0F0x78_Scratch_WIDTH 32 |
| 427 | #define D0F0x78_Scratch_MASK 0xffffffff |
| 428 | |
| 429 | /// D0F0x78 |
| 430 | typedef union { |
| 431 | struct { ///< |
| 432 | UINT32 Scratch:32; ///< |
| 433 | } Field; ///< |
| 434 | UINT32 Value; ///< |
| 435 | } D0F0x78_STRUCT; |
| 436 | |
| 437 | // **** D0F0x7C Register Definition **** |
| 438 | // Address |
| 439 | #define D0F0x7C_ADDRESS 0x7c |
| 440 | |
| 441 | // Type |
| 442 | #define D0F0x7C_TYPE TYPE_D0F0 |
| 443 | // Field Data |
| 444 | #define D0F0x7C_ForceIntGFXDisable_OFFSET 0 |
| 445 | #define D0F0x7C_ForceIntGFXDisable_WIDTH 1 |
| 446 | #define D0F0x7C_ForceIntGFXDisable_MASK 0x1 |
| 447 | #define D0F0x7C_Reserved_31_1_OFFSET 1 |
| 448 | #define D0F0x7C_Reserved_31_1_WIDTH 31 |
| 449 | #define D0F0x7C_Reserved_31_1_MASK 0xfffffffe |
| 450 | |
| 451 | /// D0F0x7C |
| 452 | typedef union { |
| 453 | struct { ///< |
| 454 | UINT32 ForceIntGFXDisable:1 ; ///< |
| 455 | UINT32 Reserved_31_1:31; ///< |
| 456 | } Field; ///< |
| 457 | UINT32 Value; ///< |
| 458 | } D0F0x7C_STRUCT; |
| 459 | |
| 460 | // **** D0F0x84 Register Definition **** |
| 461 | // Address |
| 462 | #define D0F0x84_ADDRESS 0x84 |
| 463 | |
| 464 | // Type |
| 465 | #define D0F0x84_TYPE TYPE_D0F0 |
| 466 | // Field Data |
| 467 | #define D0F0x84_Reserved_3_0_OFFSET 0 |
| 468 | #define D0F0x84_Reserved_3_0_WIDTH 4 |
| 469 | #define D0F0x84_Reserved_3_0_MASK 0xf |
| 470 | #define D0F0x84_Ev6Mode_OFFSET 4 |
| 471 | #define D0F0x84_Ev6Mode_WIDTH 1 |
| 472 | #define D0F0x84_Ev6Mode_MASK 0x10 |
| 473 | #define D0F0x84_Reserved_7_5_OFFSET 5 |
| 474 | #define D0F0x84_Reserved_7_5_WIDTH 3 |
| 475 | #define D0F0x84_Reserved_7_5_MASK 0xe0 |
| 476 | #define D0F0x84_PmeMode_OFFSET 8 |
| 477 | #define D0F0x84_PmeMode_WIDTH 1 |
| 478 | #define D0F0x84_PmeMode_MASK 0x100 |
| 479 | #define D0F0x84_PmeTurnOff_OFFSET 9 |
| 480 | #define D0F0x84_PmeTurnOff_WIDTH 1 |
| 481 | #define D0F0x84_PmeTurnOff_MASK 0x200 |
| 482 | #define D0F0x84_Reserved_31_10_OFFSET 10 |
| 483 | #define D0F0x84_Reserved_31_10_WIDTH 22 |
| 484 | #define D0F0x84_Reserved_31_10_MASK 0xfffffc00 |
| 485 | |
| 486 | /// D0F0x84 |
| 487 | typedef union { |
| 488 | struct { ///< |
| 489 | UINT32 Reserved_3_0:4 ; ///< |
| 490 | UINT32 Ev6Mode:1 ; ///< |
| 491 | UINT32 Reserved_7_5:3 ; ///< |
| 492 | UINT32 PmeMode:1 ; ///< |
| 493 | UINT32 PmeTurnOff:1 ; ///< |
| 494 | UINT32 Reserved_31_10:22; ///< |
| 495 | } Field; ///< |
| 496 | UINT32 Value; ///< |
| 497 | } D0F0x84_STRUCT; |
| 498 | |
| 499 | // **** D0F0x90 Register Definition **** |
| 500 | // Address |
| 501 | #define D0F0x90_ADDRESS 0x90 |
| 502 | |
| 503 | // Type |
| 504 | #define D0F0x90_TYPE TYPE_D0F0 |
| 505 | // Field Data |
| 506 | #define D0F0x90_Reserved_22_0_OFFSET 0 |
| 507 | #define D0F0x90_Reserved_22_0_WIDTH 23 |
| 508 | #define D0F0x90_Reserved_22_0_MASK 0x7fffff |
| 509 | #define D0F0x90_TopOfDram_OFFSET 23 |
| 510 | #define D0F0x90_TopOfDram_WIDTH 9 |
| 511 | #define D0F0x90_TopOfDram_MASK 0xff800000 |
| 512 | |
| 513 | /// D0F0x90 |
| 514 | typedef union { |
| 515 | struct { ///< |
| 516 | UINT32 Reserved_22_0:23; ///< |
| 517 | UINT32 TopOfDram:9 ; ///< |
| 518 | } Field; ///< |
| 519 | UINT32 Value; ///< |
| 520 | } D0F0x90_STRUCT; |
| 521 | |
| 522 | // **** D0F0x94 Register Definition **** |
| 523 | // Address |
| 524 | #define D0F0x94_ADDRESS 0x94 |
| 525 | |
| 526 | // Type |
| 527 | #define D0F0x94_TYPE TYPE_D0F0 |
| 528 | // Field Data |
| 529 | #define D0F0x94_OrbIndAddr_OFFSET 0 |
| 530 | #define D0F0x94_OrbIndAddr_WIDTH 7 |
| 531 | #define D0F0x94_OrbIndAddr_MASK 0x7f |
| 532 | #define D0F0x94_Reserved_7_7_OFFSET 7 |
| 533 | #define D0F0x94_Reserved_7_7_WIDTH 1 |
| 534 | #define D0F0x94_Reserved_7_7_MASK 0x80 |
| 535 | #define D0F0x94_OrbIndWrEn_OFFSET 8 |
| 536 | #define D0F0x94_OrbIndWrEn_WIDTH 1 |
| 537 | #define D0F0x94_OrbIndWrEn_MASK 0x100 |
| 538 | #define D0F0x94_Reserved_31_9_OFFSET 9 |
| 539 | #define D0F0x94_Reserved_31_9_WIDTH 23 |
| 540 | #define D0F0x94_Reserved_31_9_MASK 0xfffffe00 |
| 541 | |
| 542 | /// D0F0x94 |
| 543 | typedef union { |
| 544 | struct { ///< |
| 545 | UINT32 OrbIndAddr:7 ; ///< |
| 546 | UINT32 Reserved_7_7:1 ; ///< |
| 547 | UINT32 OrbIndWrEn:1 ; ///< |
| 548 | UINT32 Reserved_31_9:23; ///< |
| 549 | } Field; ///< |
| 550 | UINT32 Value; ///< |
| 551 | } D0F0x94_STRUCT; |
| 552 | |
| 553 | // **** D0F0x98 Register Definition **** |
| 554 | // Address |
| 555 | #define D0F0x98_ADDRESS 0x98 |
| 556 | |
| 557 | // Type |
| 558 | #define D0F0x98_TYPE TYPE_D0F0 |
| 559 | // Field Data |
| 560 | #define D0F0x98_OrbIndData_OFFSET 0 |
| 561 | #define D0F0x98_OrbIndData_WIDTH 32 |
| 562 | #define D0F0x98_OrbIndData_MASK 0xffffffff |
| 563 | |
| 564 | /// D0F0x98 |
| 565 | typedef union { |
| 566 | struct { ///< |
| 567 | UINT32 OrbIndData:32; ///< |
| 568 | } Field; ///< |
| 569 | UINT32 Value; ///< |
| 570 | } D0F0x98_STRUCT; |
| 571 | |
| 572 | // **** D0F0xE0 Register Definition **** |
| 573 | // Address |
| 574 | #define D0F0xE0_ADDRESS 0xe0 |
| 575 | |
| 576 | // Type |
| 577 | #define D0F0xE0_TYPE TYPE_D0F0 |
| 578 | // Field Data |
| 579 | #define D0F0xE0_PcieIndxAddr_OFFSET 0 |
| 580 | #define D0F0xE0_PcieIndxAddr_WIDTH 16 |
| 581 | #define D0F0xE0_PcieIndxAddr_MASK 0xffff |
| 582 | #define D0F0xE0_FrameType_OFFSET 16 |
| 583 | #define D0F0xE0_FrameType_WIDTH 8 |
| 584 | #define D0F0xE0_FrameType_MASK 0xff0000 |
| 585 | #define D0F0xE0_BlockSelect_OFFSET 24 |
| 586 | #define D0F0xE0_BlockSelect_WIDTH 8 |
| 587 | #define D0F0xE0_BlockSelect_MASK 0xff000000 |
| 588 | |
| 589 | /// D0F0xE0 |
| 590 | typedef union { |
| 591 | struct { ///< |
| 592 | UINT32 PcieIndxAddr:16; ///< |
| 593 | UINT32 FrameType:8 ; ///< |
| 594 | UINT32 BlockSelect:8 ; ///< |
| 595 | } Field; ///< |
| 596 | UINT32 Value; ///< |
| 597 | } D0F0xE0_STRUCT; |
| 598 | |
| 599 | // **** D0F0xE4 Register Definition **** |
| 600 | // Address |
| 601 | #define D0F0xE4_ADDRESS 0xe4 |
| 602 | |
| 603 | // Type |
| 604 | #define D0F0xE4_TYPE TYPE_D0F0 |
| 605 | // Field Data |
| 606 | #define D0F0xE4_PcieIndxData_OFFSET 0 |
| 607 | #define D0F0xE4_PcieIndxData_WIDTH 32 |
| 608 | #define D0F0xE4_PcieIndxData_MASK 0xffffffff |
| 609 | |
| 610 | /// D0F0xE4 |
| 611 | typedef union { |
| 612 | struct { ///< |
| 613 | UINT32 PcieIndxData:32; ///< |
| 614 | } Field; ///< |
| 615 | UINT32 Value; ///< |
| 616 | } D0F0xE4_STRUCT; |
| 617 | |
| 618 | // **** D18F1xF0 Register Definition **** |
| 619 | // Address |
| 620 | #define D18F1xF0_ADDRESS 0xf0 |
| 621 | |
| 622 | // Type |
| 623 | #define D18F1xF0_TYPE TYPE_D18F1 |
| 624 | // Field Data |
| 625 | #define D18F1xF0_DramHoleValid_OFFSET 0 |
| 626 | #define D18F1xF0_DramHoleValid_WIDTH 1 |
| 627 | #define D18F1xF0_DramHoleValid_MASK 0x1 |
| 628 | #define D18F1xF0_Reserved_6_1_OFFSET 1 |
| 629 | #define D18F1xF0_Reserved_6_1_WIDTH 6 |
| 630 | #define D18F1xF0_Reserved_6_1_MASK 0x7e |
| 631 | #define D18F1xF0_DramHoleOffset_31_23__OFFSET 7 |
| 632 | #define D18F1xF0_DramHoleOffset_31_23__WIDTH 9 |
| 633 | #define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80 |
| 634 | #define D18F1xF0_Reserved_23_16_OFFSET 16 |
| 635 | #define D18F1xF0_Reserved_23_16_WIDTH 8 |
| 636 | #define D18F1xF0_Reserved_23_16_MASK 0xff0000 |
| 637 | #define D18F1xF0_DramHoleBase_31_24__OFFSET 24 |
| 638 | #define D18F1xF0_DramHoleBase_31_24__WIDTH 8 |
| 639 | #define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000 |
| 640 | |
| 641 | /// D18F1xF0 |
| 642 | typedef union { |
| 643 | struct { ///< |
| 644 | UINT32 DramHoleValid:1 ; ///< |
| 645 | UINT32 Reserved_6_1:6 ; ///< |
| 646 | UINT32 DramHoleOffset_31_23_:9 ; ///< |
| 647 | UINT32 Reserved_23_16:8 ; ///< |
| 648 | UINT32 DramHoleBase_31_24_:8 ; ///< |
| 649 | } Field; ///< |
| 650 | UINT32 Value; ///< |
| 651 | } D18F1xF0_STRUCT; |
| 652 | |
| 653 | // **** D18F2x00 Register Definition **** |
| 654 | // Address |
| 655 | #define D18F2x00_ADDRESS 0x0 |
| 656 | |
| 657 | // Type |
| 658 | #define D18F2x00_TYPE TYPE_D18F2 |
| 659 | // Field Data |
| 660 | #define D18F2x00_VendorID_OFFSET 0 |
| 661 | #define D18F2x00_VendorID_WIDTH 16 |
| 662 | #define D18F2x00_VendorID_MASK 0xffff |
| 663 | #define D18F2x00_DeviceID_OFFSET 16 |
| 664 | #define D18F2x00_DeviceID_WIDTH 16 |
| 665 | #define D18F2x00_DeviceID_MASK 0xffff0000 |
| 666 | |
| 667 | /// D18F2x00 |
| 668 | typedef union { |
| 669 | struct { ///< |
| 670 | UINT32 VendorID:16; ///< |
| 671 | UINT32 DeviceID:16; ///< |
| 672 | } Field; ///< |
| 673 | UINT32 Value; ///< |
| 674 | } D18F2x00_STRUCT; |
| 675 | |
| 676 | // **** D18F2x04 Register Definition **** |
| 677 | // Address |
| 678 | #define D18F2x04_ADDRESS 0x4 |
| 679 | |
| 680 | // Type |
| 681 | #define D18F2x04_TYPE TYPE_D18F2 |
| 682 | // Field Data |
| 683 | #define D18F2x04_Command_OFFSET 0 |
| 684 | #define D18F2x04_Command_WIDTH 16 |
| 685 | #define D18F2x04_Command_MASK 0xffff |
| 686 | #define D18F2x04_Status_OFFSET 16 |
| 687 | #define D18F2x04_Status_WIDTH 16 |
| 688 | #define D18F2x04_Status_MASK 0xffff0000 |
| 689 | |
| 690 | /// D18F2x04 |
| 691 | typedef union { |
| 692 | struct { ///< |
| 693 | UINT32 Command:16; ///< |
| 694 | UINT32 Status:16; ///< |
| 695 | } Field; ///< |
| 696 | UINT32 Value; ///< |
| 697 | } D18F2x04_STRUCT; |
| 698 | |
| 699 | // **** D18F2x08 Register Definition **** |
| 700 | // Address |
| 701 | #define D18F2x08_ADDRESS 0x8 |
| 702 | |
| 703 | // Type |
| 704 | #define D18F2x08_TYPE TYPE_D18F2 |
| 705 | // Field Data |
| 706 | #define D18F2x08_RevID_OFFSET 0 |
| 707 | #define D18F2x08_RevID_WIDTH 8 |
| 708 | #define D18F2x08_RevID_MASK 0xff |
| 709 | #define D18F2x08_ClassCode_OFFSET 8 |
| 710 | #define D18F2x08_ClassCode_WIDTH 24 |
| 711 | #define D18F2x08_ClassCode_MASK 0xffffff00 |
| 712 | |
| 713 | /// D18F2x08 |
| 714 | typedef union { |
| 715 | struct { ///< |
| 716 | UINT32 RevID:8 ; ///< |
| 717 | UINT32 ClassCode:24; ///< |
| 718 | } Field; ///< |
| 719 | UINT32 Value; ///< |
| 720 | } D18F2x08_STRUCT; |
| 721 | |
| 722 | // **** D18F2x0C Register Definition **** |
| 723 | // Address |
| 724 | #define D18F2x0C_ADDRESS 0xc |
| 725 | |
| 726 | // Type |
| 727 | #define D18F2x0C_TYPE TYPE_D18F2 |
| 728 | // Field Data |
| 729 | #define D18F2x0C_HeaderTypeReg_OFFSET 0 |
| 730 | #define D18F2x0C_HeaderTypeReg_WIDTH 32 |
| 731 | #define D18F2x0C_HeaderTypeReg_MASK 0xffffffff |
| 732 | |
| 733 | /// D18F2x0C |
| 734 | typedef union { |
| 735 | struct { ///< |
| 736 | UINT32 HeaderTypeReg:32; ///< |
| 737 | } Field; ///< |
| 738 | UINT32 Value; ///< |
| 739 | } D18F2x0C_STRUCT; |
| 740 | |
| 741 | // **** D18F2x34 Register Definition **** |
| 742 | // Address |
| 743 | #define D18F2x34_ADDRESS 0x34 |
| 744 | |
| 745 | // Type |
| 746 | #define D18F2x34_TYPE TYPE_D18F2 |
| 747 | // Field Data |
| 748 | #define D18F2x34_CapPtr_OFFSET 0 |
| 749 | #define D18F2x34_CapPtr_WIDTH 8 |
| 750 | #define D18F2x34_CapPtr_MASK 0xff |
| 751 | #define D18F2x34_Reserved_31_8_OFFSET 8 |
| 752 | #define D18F2x34_Reserved_31_8_WIDTH 24 |
| 753 | #define D18F2x34_Reserved_31_8_MASK 0xffffff00 |
| 754 | |
| 755 | /// D18F2x34 |
| 756 | typedef union { |
| 757 | struct { ///< |
| 758 | UINT32 CapPtr:8 ; ///< |
| 759 | UINT32 Reserved_31_8:24; ///< |
| 760 | } Field; ///< |
| 761 | UINT32 Value; ///< |
| 762 | } D18F2x34_STRUCT; |
| 763 | |
| 764 | // **** D18F2x40 Register Definition **** |
| 765 | // Address |
| 766 | #define D18F2x40_ADDRESS 0x40 |
| 767 | |
| 768 | // Type |
| 769 | #define D18F2x40_TYPE TYPE_D18F2 |
| 770 | // Field Data |
| 771 | #define D18F2x40_CSEnable_OFFSET 0 |
| 772 | #define D18F2x40_CSEnable_WIDTH 1 |
| 773 | #define D18F2x40_CSEnable_MASK 0x1 |
| 774 | #define D18F2x40_Reserved_1_1_OFFSET 1 |
| 775 | #define D18F2x40_Reserved_1_1_WIDTH 1 |
| 776 | #define D18F2x40_Reserved_1_1_MASK 0x2 |
| 777 | #define D18F2x40_TestFail_OFFSET 2 |
| 778 | #define D18F2x40_TestFail_WIDTH 1 |
| 779 | #define D18F2x40_TestFail_MASK 0x4 |
| 780 | #define D18F2x40_OnDimmMirror_OFFSET 3 |
| 781 | #define D18F2x40_OnDimmMirror_WIDTH 1 |
| 782 | #define D18F2x40_OnDimmMirror_MASK 0x8 |
| 783 | #define D18F2x40_Reserved_4_4_OFFSET 4 |
| 784 | #define D18F2x40_Reserved_4_4_WIDTH 1 |
| 785 | #define D18F2x40_Reserved_4_4_MASK 0x10 |
| 786 | #define D18F2x40_BaseAddr_21_13__OFFSET 5 |
| 787 | #define D18F2x40_BaseAddr_21_13__WIDTH 9 |
| 788 | #define D18F2x40_BaseAddr_21_13__MASK 0x3fe0 |
| 789 | #define D18F2x40_Reserved_18_14_OFFSET 14 |
| 790 | #define D18F2x40_Reserved_18_14_WIDTH 5 |
| 791 | #define D18F2x40_Reserved_18_14_MASK 0x7c000 |
| 792 | #define D18F2x40_BaseAddr_35_27__OFFSET 19 |
| 793 | #define D18F2x40_BaseAddr_35_27__WIDTH 9 |
| 794 | #define D18F2x40_BaseAddr_35_27__MASK 0xff80000 |
| 795 | #define D18F2x40_Reserved_28_28_OFFSET 28 |
| 796 | #define D18F2x40_Reserved_28_28_WIDTH 1 |
| 797 | #define D18F2x40_Reserved_28_28_MASK 0x10000000 |
| 798 | #define D18F2x40_Reserved_31_29_OFFSET 29 |
| 799 | #define D18F2x40_Reserved_31_29_WIDTH 3 |
| 800 | #define D18F2x40_Reserved_31_29_MASK 0xe0000000 |
| 801 | |
| 802 | /// D18F2x40 |
| 803 | typedef union { |
| 804 | struct { ///< |
| 805 | UINT32 CSEnable:1 ; ///< |
| 806 | UINT32 Reserved_1_1:1 ; ///< |
| 807 | UINT32 TestFail:1 ; ///< |
| 808 | UINT32 OnDimmMirror:1 ; ///< |
| 809 | UINT32 Reserved_4_4:1 ; ///< |
| 810 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 811 | UINT32 Reserved_18_14:5 ; ///< |
| 812 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 813 | UINT32 Reserved_28_28:1 ; ///< |
| 814 | UINT32 Reserved_31_29:3 ; ///< |
| 815 | } Field; ///< |
| 816 | UINT32 Value; ///< |
| 817 | } D18F2x40_STRUCT; |
| 818 | |
| 819 | // **** D18F2x44 Register Definition **** |
| 820 | // Address |
| 821 | #define D18F2x44_ADDRESS 0x44 |
| 822 | |
| 823 | // Type |
| 824 | #define D18F2x44_TYPE TYPE_D18F2 |
| 825 | // Field Data |
| 826 | #define D18F2x44_CSEnable_OFFSET 0 |
| 827 | #define D18F2x44_CSEnable_WIDTH 1 |
| 828 | #define D18F2x44_CSEnable_MASK 0x1 |
| 829 | #define D18F2x44_Reserved_1_1_OFFSET 1 |
| 830 | #define D18F2x44_Reserved_1_1_WIDTH 1 |
| 831 | #define D18F2x44_Reserved_1_1_MASK 0x2 |
| 832 | #define D18F2x44_TestFail_OFFSET 2 |
| 833 | #define D18F2x44_TestFail_WIDTH 1 |
| 834 | #define D18F2x44_TestFail_MASK 0x4 |
| 835 | #define D18F2x44_OnDimmMirror_OFFSET 3 |
| 836 | #define D18F2x44_OnDimmMirror_WIDTH 1 |
| 837 | #define D18F2x44_OnDimmMirror_MASK 0x8 |
| 838 | #define D18F2x44_Reserved_4_4_OFFSET 4 |
| 839 | #define D18F2x44_Reserved_4_4_WIDTH 1 |
| 840 | #define D18F2x44_Reserved_4_4_MASK 0x10 |
| 841 | #define D18F2x44_BaseAddr_21_13__OFFSET 5 |
| 842 | #define D18F2x44_BaseAddr_21_13__WIDTH 9 |
| 843 | #define D18F2x44_BaseAddr_21_13__MASK 0x3fe0 |
| 844 | #define D18F2x44_Reserved_18_14_OFFSET 14 |
| 845 | #define D18F2x44_Reserved_18_14_WIDTH 5 |
| 846 | #define D18F2x44_Reserved_18_14_MASK 0x7c000 |
| 847 | #define D18F2x44_BaseAddr_35_27__OFFSET 19 |
| 848 | #define D18F2x44_BaseAddr_35_27__WIDTH 9 |
| 849 | #define D18F2x44_BaseAddr_35_27__MASK 0xff80000 |
| 850 | #define D18F2x44_Reserved_28_28_OFFSET 28 |
| 851 | #define D18F2x44_Reserved_28_28_WIDTH 1 |
| 852 | #define D18F2x44_Reserved_28_28_MASK 0x10000000 |
| 853 | #define D18F2x44_Reserved_31_29_OFFSET 29 |
| 854 | #define D18F2x44_Reserved_31_29_WIDTH 3 |
| 855 | #define D18F2x44_Reserved_31_29_MASK 0xe0000000 |
| 856 | |
| 857 | /// D18F2x44 |
| 858 | typedef union { |
| 859 | struct { ///< |
| 860 | UINT32 CSEnable:1 ; ///< |
| 861 | UINT32 Reserved_1_1:1 ; ///< |
| 862 | UINT32 TestFail:1 ; ///< |
| 863 | UINT32 OnDimmMirror:1 ; ///< |
| 864 | UINT32 Reserved_4_4:1 ; ///< |
| 865 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 866 | UINT32 Reserved_18_14:5 ; ///< |
| 867 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 868 | UINT32 Reserved_28_28:1 ; ///< |
| 869 | UINT32 Reserved_31_29:3 ; ///< |
| 870 | } Field; ///< |
| 871 | UINT32 Value; ///< |
| 872 | } D18F2x44_STRUCT; |
| 873 | |
| 874 | // **** D18F2x48 Register Definition **** |
| 875 | // Address |
| 876 | #define D18F2x48_ADDRESS 0x48 |
| 877 | |
| 878 | // Type |
| 879 | #define D18F2x48_TYPE TYPE_D18F2 |
| 880 | // Field Data |
| 881 | #define D18F2x48_CSEnable_OFFSET 0 |
| 882 | #define D18F2x48_CSEnable_WIDTH 1 |
| 883 | #define D18F2x48_CSEnable_MASK 0x1 |
| 884 | #define D18F2x48_Reserved_1_1_OFFSET 1 |
| 885 | #define D18F2x48_Reserved_1_1_WIDTH 1 |
| 886 | #define D18F2x48_Reserved_1_1_MASK 0x2 |
| 887 | #define D18F2x48_TestFail_OFFSET 2 |
| 888 | #define D18F2x48_TestFail_WIDTH 1 |
| 889 | #define D18F2x48_TestFail_MASK 0x4 |
| 890 | #define D18F2x48_OnDimmMirror_OFFSET 3 |
| 891 | #define D18F2x48_OnDimmMirror_WIDTH 1 |
| 892 | #define D18F2x48_OnDimmMirror_MASK 0x8 |
| 893 | #define D18F2x48_Reserved_4_4_OFFSET 4 |
| 894 | #define D18F2x48_Reserved_4_4_WIDTH 1 |
| 895 | #define D18F2x48_Reserved_4_4_MASK 0x10 |
| 896 | #define D18F2x48_BaseAddr_21_13__OFFSET 5 |
| 897 | #define D18F2x48_BaseAddr_21_13__WIDTH 9 |
| 898 | #define D18F2x48_BaseAddr_21_13__MASK 0x3fe0 |
| 899 | #define D18F2x48_Reserved_18_14_OFFSET 14 |
| 900 | #define D18F2x48_Reserved_18_14_WIDTH 5 |
| 901 | #define D18F2x48_Reserved_18_14_MASK 0x7c000 |
| 902 | #define D18F2x48_BaseAddr_35_27__OFFSET 19 |
| 903 | #define D18F2x48_BaseAddr_35_27__WIDTH 9 |
| 904 | #define D18F2x48_BaseAddr_35_27__MASK 0xff80000 |
| 905 | #define D18F2x48_Reserved_28_28_OFFSET 28 |
| 906 | #define D18F2x48_Reserved_28_28_WIDTH 1 |
| 907 | #define D18F2x48_Reserved_28_28_MASK 0x10000000 |
| 908 | #define D18F2x48_Reserved_31_29_OFFSET 29 |
| 909 | #define D18F2x48_Reserved_31_29_WIDTH 3 |
| 910 | #define D18F2x48_Reserved_31_29_MASK 0xe0000000 |
| 911 | |
| 912 | /// D18F2x48 |
| 913 | typedef union { |
| 914 | struct { ///< |
| 915 | UINT32 CSEnable:1 ; ///< |
| 916 | UINT32 Reserved_1_1:1 ; ///< |
| 917 | UINT32 TestFail:1 ; ///< |
| 918 | UINT32 OnDimmMirror:1 ; ///< |
| 919 | UINT32 Reserved_4_4:1 ; ///< |
| 920 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 921 | UINT32 Reserved_18_14:5 ; ///< |
| 922 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 923 | UINT32 Reserved_28_28:1 ; ///< |
| 924 | UINT32 Reserved_31_29:3 ; ///< |
| 925 | } Field; ///< |
| 926 | UINT32 Value; ///< |
| 927 | } D18F2x48_STRUCT; |
| 928 | |
| 929 | // **** D18F2x4C Register Definition **** |
| 930 | // Address |
| 931 | #define D18F2x4C_ADDRESS 0x4c |
| 932 | |
| 933 | // Type |
| 934 | #define D18F2x4C_TYPE TYPE_D18F2 |
| 935 | // Field Data |
| 936 | #define D18F2x4C_CSEnable_OFFSET 0 |
| 937 | #define D18F2x4C_CSEnable_WIDTH 1 |
| 938 | #define D18F2x4C_CSEnable_MASK 0x1 |
| 939 | #define D18F2x4C_Reserved_1_1_OFFSET 1 |
| 940 | #define D18F2x4C_Reserved_1_1_WIDTH 1 |
| 941 | #define D18F2x4C_Reserved_1_1_MASK 0x2 |
| 942 | #define D18F2x4C_TestFail_OFFSET 2 |
| 943 | #define D18F2x4C_TestFail_WIDTH 1 |
| 944 | #define D18F2x4C_TestFail_MASK 0x4 |
| 945 | #define D18F2x4C_OnDimmMirror_OFFSET 3 |
| 946 | #define D18F2x4C_OnDimmMirror_WIDTH 1 |
| 947 | #define D18F2x4C_OnDimmMirror_MASK 0x8 |
| 948 | #define D18F2x4C_Reserved_4_4_OFFSET 4 |
| 949 | #define D18F2x4C_Reserved_4_4_WIDTH 1 |
| 950 | #define D18F2x4C_Reserved_4_4_MASK 0x10 |
| 951 | #define D18F2x4C_BaseAddr_21_13__OFFSET 5 |
| 952 | #define D18F2x4C_BaseAddr_21_13__WIDTH 9 |
| 953 | #define D18F2x4C_BaseAddr_21_13__MASK 0x3fe0 |
| 954 | #define D18F2x4C_Reserved_18_14_OFFSET 14 |
| 955 | #define D18F2x4C_Reserved_18_14_WIDTH 5 |
| 956 | #define D18F2x4C_Reserved_18_14_MASK 0x7c000 |
| 957 | #define D18F2x4C_BaseAddr_35_27__OFFSET 19 |
| 958 | #define D18F2x4C_BaseAddr_35_27__WIDTH 9 |
| 959 | #define D18F2x4C_BaseAddr_35_27__MASK 0xff80000 |
| 960 | #define D18F2x4C_Reserved_28_28_OFFSET 28 |
| 961 | #define D18F2x4C_Reserved_28_28_WIDTH 1 |
| 962 | #define D18F2x4C_Reserved_28_28_MASK 0x10000000 |
| 963 | #define D18F2x4C_Reserved_31_29_OFFSET 29 |
| 964 | #define D18F2x4C_Reserved_31_29_WIDTH 3 |
| 965 | #define D18F2x4C_Reserved_31_29_MASK 0xe0000000 |
| 966 | |
| 967 | /// D18F2x4C |
| 968 | typedef union { |
| 969 | struct { ///< |
| 970 | UINT32 CSEnable:1 ; ///< |
| 971 | UINT32 Reserved_1_1:1 ; ///< |
| 972 | UINT32 TestFail:1 ; ///< |
| 973 | UINT32 OnDimmMirror:1 ; ///< |
| 974 | UINT32 Reserved_4_4:1 ; ///< |
| 975 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 976 | UINT32 Reserved_18_14:5 ; ///< |
| 977 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 978 | UINT32 Reserved_28_28:1 ; ///< |
| 979 | UINT32 Reserved_31_29:3 ; ///< |
| 980 | } Field; ///< |
| 981 | UINT32 Value; ///< |
| 982 | } D18F2x4C_STRUCT; |
| 983 | |
| 984 | // **** D18F2x60 Register Definition **** |
| 985 | // Address |
| 986 | #define D18F2x60_ADDRESS 0x60 |
| 987 | |
| 988 | // Type |
| 989 | #define D18F2x60_TYPE TYPE_D18F2 |
| 990 | // Field Data |
| 991 | #define D18F2x60_Reserved_4_0_OFFSET 0 |
| 992 | #define D18F2x60_Reserved_4_0_WIDTH 5 |
| 993 | #define D18F2x60_Reserved_4_0_MASK 0x1f |
| 994 | #define D18F2x60_AddrMask_21_13__OFFSET 5 |
| 995 | #define D18F2x60_AddrMask_21_13__WIDTH 9 |
| 996 | #define D18F2x60_AddrMask_21_13__MASK 0x3fe0 |
| 997 | #define D18F2x60_Reserved_18_14_OFFSET 14 |
| 998 | #define D18F2x60_Reserved_18_14_WIDTH 5 |
| 999 | #define D18F2x60_Reserved_18_14_MASK 0x7c000 |
| 1000 | #define D18F2x60_AddrMask_35_27__OFFSET 19 |
| 1001 | #define D18F2x60_AddrMask_35_27__WIDTH 9 |
| 1002 | #define D18F2x60_AddrMask_35_27__MASK 0xff80000 |
| 1003 | #define D18F2x60_Reserved_28_28_OFFSET 28 |
| 1004 | #define D18F2x60_Reserved_28_28_WIDTH 1 |
| 1005 | #define D18F2x60_Reserved_28_28_MASK 0x10000000 |
| 1006 | #define D18F2x60_Reserved_31_29_OFFSET 29 |
| 1007 | #define D18F2x60_Reserved_31_29_WIDTH 3 |
| 1008 | #define D18F2x60_Reserved_31_29_MASK 0xe0000000 |
| 1009 | |
| 1010 | /// D18F2x60 |
| 1011 | typedef union { |
| 1012 | struct { ///< |
| 1013 | UINT32 Reserved_4_0:5 ; ///< |
| 1014 | UINT32 AddrMask_21_13_:9 ; ///< |
| 1015 | UINT32 Reserved_18_14:5 ; ///< |
| 1016 | UINT32 AddrMask_35_27_:9 ; ///< |
| 1017 | UINT32 Reserved_28_28:1 ; ///< |
| 1018 | UINT32 Reserved_31_29:3 ; ///< |
| 1019 | } Field; ///< |
| 1020 | UINT32 Value; ///< |
| 1021 | } D18F2x60_STRUCT; |
| 1022 | |
| 1023 | // **** D18F2x64 Register Definition **** |
| 1024 | // Address |
| 1025 | #define D18F2x64_ADDRESS 0x64 |
| 1026 | |
| 1027 | // Type |
| 1028 | #define D18F2x64_TYPE TYPE_D18F2 |
| 1029 | // Field Data |
| 1030 | #define D18F2x64_Reserved_4_0_OFFSET 0 |
| 1031 | #define D18F2x64_Reserved_4_0_WIDTH 5 |
| 1032 | #define D18F2x64_Reserved_4_0_MASK 0x1f |
| 1033 | #define D18F2x64_AddrMask_21_13__OFFSET 5 |
| 1034 | #define D18F2x64_AddrMask_21_13__WIDTH 9 |
| 1035 | #define D18F2x64_AddrMask_21_13__MASK 0x3fe0 |
| 1036 | #define D18F2x64_Reserved_18_14_OFFSET 14 |
| 1037 | #define D18F2x64_Reserved_18_14_WIDTH 5 |
| 1038 | #define D18F2x64_Reserved_18_14_MASK 0x7c000 |
| 1039 | #define D18F2x64_AddrMask_35_27__OFFSET 19 |
| 1040 | #define D18F2x64_AddrMask_35_27__WIDTH 9 |
| 1041 | #define D18F2x64_AddrMask_35_27__MASK 0xff80000 |
| 1042 | #define D18F2x64_Reserved_28_28_OFFSET 28 |
| 1043 | #define D18F2x64_Reserved_28_28_WIDTH 1 |
| 1044 | #define D18F2x64_Reserved_28_28_MASK 0x10000000 |
| 1045 | #define D18F2x64_Reserved_31_29_OFFSET 29 |
| 1046 | #define D18F2x64_Reserved_31_29_WIDTH 3 |
| 1047 | #define D18F2x64_Reserved_31_29_MASK 0xe0000000 |
| 1048 | |
| 1049 | /// D18F2x64 |
| 1050 | typedef union { |
| 1051 | struct { ///< |
| 1052 | UINT32 Reserved_4_0:5 ; ///< |
| 1053 | UINT32 AddrMask_21_13_:9 ; ///< |
| 1054 | UINT32 Reserved_18_14:5 ; ///< |
| 1055 | UINT32 AddrMask_35_27_:9 ; ///< |
| 1056 | UINT32 Reserved_28_28:1 ; ///< |
| 1057 | UINT32 Reserved_31_29:3 ; ///< |
| 1058 | } Field; ///< |
| 1059 | UINT32 Value; ///< |
| 1060 | } D18F2x64_STRUCT; |
| 1061 | |
| 1062 | // **** D18F2x78 Register Definition **** |
| 1063 | // Address |
| 1064 | #define D18F2x78_ADDRESS 0x78 |
| 1065 | |
| 1066 | // Type |
| 1067 | #define D18F2x78_TYPE TYPE_D18F2 |
| 1068 | // Field Data |
| 1069 | #define D18F2x78_RdPtrInit_OFFSET 0 |
| 1070 | #define D18F2x78_RdPtrInit_WIDTH 4 |
| 1071 | #define D18F2x78_RdPtrInit_MASK 0xf |
| 1072 | #define D18F2x78_Reserved_5_4_OFFSET 4 |
| 1073 | #define D18F2x78_Reserved_5_4_WIDTH 2 |
| 1074 | #define D18F2x78_Reserved_5_4_MASK 0x30 |
| 1075 | #define D18F2x78_RxPtrInitReq_OFFSET 6 |
| 1076 | #define D18F2x78_RxPtrInitReq_WIDTH 1 |
| 1077 | #define D18F2x78_RxPtrInitReq_MASK 0x40 |
| 1078 | #define D18F2x78_Reserved_7_7_OFFSET 7 |
| 1079 | #define D18F2x78_Reserved_7_7_WIDTH 1 |
| 1080 | #define D18F2x78_Reserved_7_7_MASK 0x80 |
| 1081 | #define D18F2x78_Twrrd_3_2__OFFSET 8 |
| 1082 | #define D18F2x78_Twrrd_3_2__WIDTH 2 |
| 1083 | #define D18F2x78_Twrrd_3_2__MASK 0x300 |
| 1084 | #define D18F2x78_Twrwr_3_2__OFFSET 10 |
| 1085 | #define D18F2x78_Twrwr_3_2__WIDTH 2 |
| 1086 | #define D18F2x78_Twrwr_3_2__MASK 0xc00 |
| 1087 | #define D18F2x78_Trdrd_3_2__OFFSET 12 |
| 1088 | #define D18F2x78_Trdrd_3_2__WIDTH 2 |
| 1089 | #define D18F2x78_Trdrd_3_2__MASK 0x3000 |
| 1090 | #define D18F2x78_Reserved_16_14_OFFSET 14 |
| 1091 | #define D18F2x78_Reserved_16_14_WIDTH 3 |
| 1092 | #define D18F2x78_Reserved_16_14_MASK 0x1c000 |
| 1093 | #define D18F2x78_AddrCmdTriEn_OFFSET 17 |
| 1094 | #define D18F2x78_AddrCmdTriEn_WIDTH 1 |
| 1095 | #define D18F2x78_AddrCmdTriEn_MASK 0x20000 |
| 1096 | #define D18F2x78_Reserved_19_18_OFFSET 18 |
| 1097 | #define D18F2x78_Reserved_19_18_WIDTH 2 |
| 1098 | #define D18F2x78_Reserved_19_18_MASK 0xc0000 |
| 1099 | #define D18F2x78_ForceCasToSlot0_OFFSET 20 |
| 1100 | #define D18F2x78_ForceCasToSlot0_WIDTH 1 |
| 1101 | #define D18F2x78_ForceCasToSlot0_MASK 0x100000 |
| 1102 | #define D18F2x78_DisCutThroughMode_OFFSET 21 |
| 1103 | #define D18F2x78_DisCutThroughMode_WIDTH 1 |
| 1104 | #define D18F2x78_DisCutThroughMode_MASK 0x200000 |
| 1105 | #define D18F2x78_MaxRdLatency_OFFSET 22 |
| 1106 | #define D18F2x78_MaxRdLatency_WIDTH 10 |
| 1107 | #define D18F2x78_MaxRdLatency_MASK 0xffc00000 |
| 1108 | |
| 1109 | /// D18F2x78 |
| 1110 | typedef union { |
| 1111 | struct { ///< |
| 1112 | UINT32 RdPtrInit:4 ; ///< |
| 1113 | UINT32 Reserved_5_4:2 ; ///< |
| 1114 | UINT32 RxPtrInitReq:1 ; ///< |
| 1115 | UINT32 Reserved_7_7:1 ; ///< |
| 1116 | UINT32 Twrrd_3_2_:2 ; ///< |
| 1117 | UINT32 Twrwr_3_2_:2 ; ///< |
| 1118 | UINT32 Trdrd_3_2_:2 ; ///< |
| 1119 | UINT32 Reserved_16_14:3 ; ///< |
| 1120 | UINT32 AddrCmdTriEn:1 ; ///< |
| 1121 | UINT32 Reserved_19_18:2 ; ///< |
| 1122 | UINT32 ForceCasToSlot0:1 ; ///< |
| 1123 | UINT32 DisCutThroughMode:1 ; ///< |
| 1124 | UINT32 MaxRdLatency:10; ///< |
| 1125 | } Field; ///< |
| 1126 | UINT32 Value; ///< |
| 1127 | } D18F2x78_STRUCT; |
| 1128 | |
| 1129 | // **** D18F2x7C Register Definition **** |
| 1130 | // Address |
| 1131 | #define D18F2x7C_ADDRESS 0x7c |
| 1132 | |
| 1133 | // Type |
| 1134 | #define D18F2x7C_TYPE TYPE_D18F2 |
| 1135 | // Field Data |
| 1136 | #define D18F2x7C_MrsAddress_OFFSET 0 |
| 1137 | #define D18F2x7C_MrsAddress_WIDTH 16 |
| 1138 | #define D18F2x7C_MrsAddress_MASK 0xffff |
| 1139 | #define D18F2x7C_MrsBank_OFFSET 16 |
| 1140 | #define D18F2x7C_MrsBank_WIDTH 3 |
| 1141 | #define D18F2x7C_MrsBank_MASK 0x70000 |
| 1142 | #define D18F2x7C_Reserved_19_19_OFFSET 19 |
| 1143 | #define D18F2x7C_Reserved_19_19_WIDTH 1 |
| 1144 | #define D18F2x7C_Reserved_19_19_MASK 0x80000 |
| 1145 | #define D18F2x7C_MrsChipSel_OFFSET 20 |
| 1146 | #define D18F2x7C_MrsChipSel_WIDTH 3 |
| 1147 | #define D18F2x7C_MrsChipSel_MASK 0x700000 |
| 1148 | #define D18F2x7C_Reserved_23_23_OFFSET 23 |
| 1149 | #define D18F2x7C_Reserved_23_23_WIDTH 1 |
| 1150 | #define D18F2x7C_Reserved_23_23_MASK 0x800000 |
| 1151 | #define D18F2x7C_SendPchgAll_OFFSET 24 |
| 1152 | #define D18F2x7C_SendPchgAll_WIDTH 1 |
| 1153 | #define D18F2x7C_SendPchgAll_MASK 0x1000000 |
| 1154 | #define D18F2x7C_SendAutoRefresh_OFFSET 25 |
| 1155 | #define D18F2x7C_SendAutoRefresh_WIDTH 1 |
| 1156 | #define D18F2x7C_SendAutoRefresh_MASK 0x2000000 |
| 1157 | #define D18F2x7C_SendMrsCmd_OFFSET 26 |
| 1158 | #define D18F2x7C_SendMrsCmd_WIDTH 1 |
| 1159 | #define D18F2x7C_SendMrsCmd_MASK 0x4000000 |
| 1160 | #define D18F2x7C_DeassertMemRstX_OFFSET 27 |
| 1161 | #define D18F2x7C_DeassertMemRstX_WIDTH 1 |
| 1162 | #define D18F2x7C_DeassertMemRstX_MASK 0x8000000 |
| 1163 | #define D18F2x7C_AssertCke_OFFSET 28 |
| 1164 | #define D18F2x7C_AssertCke_WIDTH 1 |
| 1165 | #define D18F2x7C_AssertCke_MASK 0x10000000 |
| 1166 | #define D18F2x7C_SendZQCmd_OFFSET 29 |
| 1167 | #define D18F2x7C_SendZQCmd_WIDTH 1 |
| 1168 | #define D18F2x7C_SendZQCmd_MASK 0x20000000 |
| 1169 | #define D18F2x7C_Reserved_30_30_OFFSET 30 |
| 1170 | #define D18F2x7C_Reserved_30_30_WIDTH 1 |
| 1171 | #define D18F2x7C_Reserved_30_30_MASK 0x40000000 |
| 1172 | #define D18F2x7C_EnDramInit_OFFSET 31 |
| 1173 | #define D18F2x7C_EnDramInit_WIDTH 1 |
| 1174 | #define D18F2x7C_EnDramInit_MASK 0x80000000 |
| 1175 | |
| 1176 | /// D18F2x7C |
| 1177 | typedef union { |
| 1178 | struct { ///< |
| 1179 | UINT32 MrsAddress:16; ///< |
| 1180 | UINT32 MrsBank:3 ; ///< |
| 1181 | UINT32 Reserved_19_19:1 ; ///< |
| 1182 | UINT32 MrsChipSel:3 ; ///< |
| 1183 | UINT32 Reserved_23_23:1 ; ///< |
| 1184 | UINT32 SendPchgAll:1 ; ///< |
| 1185 | UINT32 SendAutoRefresh:1 ; ///< |
| 1186 | UINT32 SendMrsCmd:1 ; ///< |
| 1187 | UINT32 DeassertMemRstX:1 ; ///< |
| 1188 | UINT32 AssertCke:1 ; ///< |
| 1189 | UINT32 SendZQCmd:1 ; ///< |
| 1190 | UINT32 Reserved_30_30:1 ; ///< |
| 1191 | UINT32 EnDramInit:1 ; ///< |
| 1192 | } Field; ///< |
| 1193 | UINT32 Value; ///< |
| 1194 | } D18F2x7C_STRUCT; |
| 1195 | |
| 1196 | // **** D18F2x80 Register Definition **** |
| 1197 | // Address |
| 1198 | #define D18F2x80_ADDRESS 0x80 |
| 1199 | |
| 1200 | // Type |
| 1201 | #define D18F2x80_TYPE TYPE_D18F2 |
| 1202 | // Field Data |
| 1203 | #define D18F2x80_Dimm0AddrMap_OFFSET 0 |
| 1204 | #define D18F2x80_Dimm0AddrMap_WIDTH 4 |
| 1205 | #define D18F2x80_Dimm0AddrMap_MASK 0xf |
| 1206 | #define D18F2x80_Dimm1AddrMap_OFFSET 4 |
| 1207 | #define D18F2x80_Dimm1AddrMap_WIDTH 4 |
| 1208 | #define D18F2x80_Dimm1AddrMap_MASK 0xf0 |
| 1209 | #define D18F2x80_Reserved_31_8_OFFSET 8 |
| 1210 | #define D18F2x80_Reserved_31_8_WIDTH 24 |
| 1211 | #define D18F2x80_Reserved_31_8_MASK 0xffffff00 |
| 1212 | |
| 1213 | /// D18F2x80 |
| 1214 | typedef union { |
| 1215 | struct { ///< |
| 1216 | UINT32 Dimm0AddrMap:4 ; ///< |
| 1217 | UINT32 Dimm1AddrMap:4 ; ///< |
| 1218 | UINT32 Reserved_31_8:24; ///< |
| 1219 | } Field; ///< |
| 1220 | UINT32 Value; ///< |
| 1221 | } D18F2x80_STRUCT; |
| 1222 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1223 | // **** D18F2x84 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1224 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1225 | #define D18F2x84_ADDRESS 0x84 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1226 | |
| 1227 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1228 | #define D18F2x84_TYPE TYPE_D18F2 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1229 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1230 | #define D18F2x84_BurstCtrl_OFFSET 0 |
| 1231 | #define D18F2x84_BurstCtrl_WIDTH 2 |
| 1232 | #define D18F2x84_BurstCtrl_MASK 0x3 |
| 1233 | #define D18F2x84_Reserved_3_2_OFFSET 2 |
| 1234 | #define D18F2x84_Reserved_3_2_WIDTH 2 |
| 1235 | #define D18F2x84_Reserved_3_2_MASK 0xc |
| 1236 | #define D18F2x84_Twr_OFFSET 4 |
| 1237 | #define D18F2x84_Twr_WIDTH 3 |
| 1238 | #define D18F2x84_Twr_MASK 0x70 |
| 1239 | #define D18F2x84_Reserved_19_7_OFFSET 7 |
| 1240 | #define D18F2x84_Reserved_19_7_WIDTH 13 |
| 1241 | #define D18F2x84_Reserved_19_7_MASK 0xfff80 |
| 1242 | #define D18F2x84_Tcwl_OFFSET 20 |
| 1243 | #define D18F2x84_Tcwl_WIDTH 3 |
| 1244 | #define D18F2x84_Tcwl_MASK 0x700000 |
| 1245 | #define D18F2x84_PchgPDModeSel_OFFSET 23 |
| 1246 | #define D18F2x84_PchgPDModeSel_WIDTH 1 |
| 1247 | #define D18F2x84_PchgPDModeSel_MASK 0x800000 |
| 1248 | #define D18F2x84_Reserved_31_24_OFFSET 24 |
| 1249 | #define D18F2x84_Reserved_31_24_WIDTH 8 |
| 1250 | #define D18F2x84_Reserved_31_24_MASK 0xff000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1251 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1252 | /// D18F2x84 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1253 | typedef union { |
| 1254 | struct { ///< |
| 1255 | UINT32 BurstCtrl:2 ; ///< |
| 1256 | UINT32 Reserved_3_2:2 ; ///< |
| 1257 | UINT32 Twr:3 ; ///< |
| 1258 | UINT32 Reserved_19_7:13; ///< |
| 1259 | UINT32 Tcwl:3 ; ///< |
| 1260 | UINT32 PchgPDModeSel:1 ; ///< |
| 1261 | UINT32 Reserved_31_24:8 ; ///< |
| 1262 | } Field; ///< |
| 1263 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1264 | } D18F2x84_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1265 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1266 | // **** D18F2x88 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1267 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1268 | #define D18F2x88_ADDRESS 0x88 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1269 | |
| 1270 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1271 | #define D18F2x88_TYPE TYPE_D18F2 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1272 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1273 | #define D18F2x88_Tcl_OFFSET 0 |
| 1274 | #define D18F2x88_Tcl_WIDTH 4 |
| 1275 | #define D18F2x88_Tcl_MASK 0xf |
| 1276 | #define D18F2x88_Reserved_23_4_OFFSET 4 |
| 1277 | #define D18F2x88_Reserved_23_4_WIDTH 20 |
| 1278 | #define D18F2x88_Reserved_23_4_MASK 0xfffff0 |
| 1279 | #define D18F2x88_MemClkDis_OFFSET 24 |
| 1280 | #define D18F2x88_MemClkDis_WIDTH 8 |
| 1281 | #define D18F2x88_MemClkDis_MASK 0xff000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1282 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1283 | /// D18F2x88 |
| 1284 | typedef union { |
| 1285 | struct { ///< |
| 1286 | UINT32 Tcl:4 ; ///< |
| 1287 | UINT32 Reserved_23_4:20; ///< |
| 1288 | UINT32 MemClkDis:8 ; ///< |
| 1289 | } Field; ///< |
| 1290 | UINT32 Value; ///< |
| 1291 | } D18F2x88_STRUCT; |
| 1292 | |
| 1293 | // **** D18F2x8C Register Definition **** |
| 1294 | // Address |
| 1295 | #define D18F2x8C_ADDRESS 0x8c |
| 1296 | |
| 1297 | // Type |
| 1298 | #define D18F2x8C_TYPE TYPE_D18F2 |
| 1299 | // Field Data |
| 1300 | #define D18F2x8C_TrwtWB_OFFSET 0 |
| 1301 | #define D18F2x8C_TrwtWB_WIDTH 4 |
| 1302 | #define D18F2x8C_TrwtWB_MASK 0xf |
| 1303 | #define D18F2x8C_TrwtTO_OFFSET 4 |
| 1304 | #define D18F2x8C_TrwtTO_WIDTH 4 |
| 1305 | #define D18F2x8C_TrwtTO_MASK 0xf0 |
| 1306 | #define D18F2x8C_Reserved_9_8_OFFSET 8 |
| 1307 | #define D18F2x8C_Reserved_9_8_WIDTH 2 |
| 1308 | #define D18F2x8C_Reserved_9_8_MASK 0x300 |
| 1309 | #define D18F2x8C_Twrrd_1_0__OFFSET 10 |
| 1310 | #define D18F2x8C_Twrrd_1_0__WIDTH 2 |
| 1311 | #define D18F2x8C_Twrrd_1_0__MASK 0xc00 |
| 1312 | #define D18F2x8C_Twrwr_1_0__OFFSET 12 |
| 1313 | #define D18F2x8C_Twrwr_1_0__WIDTH 2 |
| 1314 | #define D18F2x8C_Twrwr_1_0__MASK 0x3000 |
| 1315 | #define D18F2x8C_Trdrd_1_0__OFFSET 14 |
| 1316 | #define D18F2x8C_Trdrd_1_0__WIDTH 2 |
| 1317 | #define D18F2x8C_Trdrd_1_0__MASK 0xc000 |
| 1318 | #define D18F2x8C_Tref_OFFSET 16 |
| 1319 | #define D18F2x8C_Tref_WIDTH 2 |
| 1320 | #define D18F2x8C_Tref_MASK 0x30000 |
| 1321 | #define D18F2x8C_DisAutoRefresh_OFFSET 18 |
| 1322 | #define D18F2x8C_DisAutoRefresh_WIDTH 1 |
| 1323 | #define D18F2x8C_DisAutoRefresh_MASK 0x40000 |
| 1324 | #define D18F2x8C_Reserved_19_19_OFFSET 19 |
| 1325 | #define D18F2x8C_Reserved_19_19_WIDTH 1 |
| 1326 | #define D18F2x8C_Reserved_19_19_MASK 0x80000 |
| 1327 | #define D18F2x8C_Trfc0_OFFSET 20 |
| 1328 | #define D18F2x8C_Trfc0_WIDTH 3 |
| 1329 | #define D18F2x8C_Trfc0_MASK 0x700000 |
| 1330 | #define D18F2x8C_Trfc1_OFFSET 23 |
| 1331 | #define D18F2x8C_Trfc1_WIDTH 3 |
| 1332 | #define D18F2x8C_Trfc1_MASK 0x3800000 |
| 1333 | #define D18F2x8C_Reserved_31_26_OFFSET 26 |
| 1334 | #define D18F2x8C_Reserved_31_26_WIDTH 6 |
| 1335 | #define D18F2x8C_Reserved_31_26_MASK 0xfc000000 |
| 1336 | |
| 1337 | /// D18F2x8C |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1338 | typedef union { |
| 1339 | struct { ///< |
| 1340 | UINT32 TrwtWB:4 ; ///< |
| 1341 | UINT32 TrwtTO:4 ; ///< |
| 1342 | UINT32 Reserved_9_8:2 ; ///< |
| 1343 | UINT32 Twrrd_1_0_:2 ; ///< |
| 1344 | UINT32 Twrwr_1_0_:2 ; ///< |
| 1345 | UINT32 Trdrd_1_0_:2 ; ///< |
| 1346 | UINT32 Tref:2 ; ///< |
| 1347 | UINT32 DisAutoRefresh:1 ; ///< |
| 1348 | UINT32 Reserved_19_19:1 ; ///< |
| 1349 | UINT32 Trfc0:3 ; ///< |
| 1350 | UINT32 Trfc1:3 ; ///< |
| 1351 | UINT32 Reserved_31_26:6 ; ///< |
| 1352 | } Field; ///< |
| 1353 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1354 | } D18F2x8C_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1355 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1356 | // **** D18F2x90 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1357 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1358 | #define D18F2x90_ADDRESS 0x90 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1359 | |
| 1360 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1361 | #define D18F2x90_TYPE TYPE_D18F2 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1362 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1363 | #define D18F2x90_Reserved_0_0_OFFSET 0 |
| 1364 | #define D18F2x90_Reserved_0_0_WIDTH 1 |
| 1365 | #define D18F2x90_Reserved_0_0_MASK 0x1 |
| 1366 | #define D18F2x90_ExitSelfRef_OFFSET 1 |
| 1367 | #define D18F2x90_ExitSelfRef_WIDTH 1 |
| 1368 | #define D18F2x90_ExitSelfRef_MASK 0x2 |
| 1369 | #define D18F2x90_Reserved_16_2_OFFSET 2 |
| 1370 | #define D18F2x90_Reserved_16_2_WIDTH 15 |
| 1371 | #define D18F2x90_Reserved_16_2_MASK 0x1fffc |
| 1372 | #define D18F2x90_EnterSelfRef_OFFSET 17 |
| 1373 | #define D18F2x90_EnterSelfRef_WIDTH 1 |
| 1374 | #define D18F2x90_EnterSelfRef_MASK 0x20000 |
| 1375 | #define D18F2x90_Reserved_19_18_OFFSET 18 |
| 1376 | #define D18F2x90_Reserved_19_18_WIDTH 2 |
| 1377 | #define D18F2x90_Reserved_19_18_MASK 0xc0000 |
| 1378 | #define D18F2x90_DynPageCloseEn_OFFSET 20 |
| 1379 | #define D18F2x90_DynPageCloseEn_WIDTH 1 |
| 1380 | #define D18F2x90_DynPageCloseEn_MASK 0x100000 |
| 1381 | #define D18F2x90_IdleCycInit_OFFSET 21 |
| 1382 | #define D18F2x90_IdleCycInit_WIDTH 2 |
| 1383 | #define D18F2x90_IdleCycInit_MASK 0x600000 |
| 1384 | #define D18F2x90_ForceAutoPchg_OFFSET 23 |
| 1385 | #define D18F2x90_ForceAutoPchg_WIDTH 1 |
| 1386 | #define D18F2x90_ForceAutoPchg_MASK 0x800000 |
| 1387 | #define D18F2x90_Reserved_24_24_OFFSET 24 |
| 1388 | #define D18F2x90_Reserved_24_24_WIDTH 1 |
| 1389 | #define D18F2x90_Reserved_24_24_MASK 0x1000000 |
| 1390 | #define D18F2x90_EnDispAutoPrecharge_OFFSET 25 |
| 1391 | #define D18F2x90_EnDispAutoPrecharge_WIDTH 1 |
| 1392 | #define D18F2x90_EnDispAutoPrecharge_MASK 0x2000000 |
| 1393 | #define D18F2x90_DbeSkidBufDis_OFFSET 26 |
| 1394 | #define D18F2x90_DbeSkidBufDis_WIDTH 1 |
| 1395 | #define D18F2x90_DbeSkidBufDis_MASK 0x4000000 |
| 1396 | #define D18F2x90_DisDllShutdownSR_OFFSET 27 |
| 1397 | #define D18F2x90_DisDllShutdownSR_WIDTH 1 |
| 1398 | #define D18F2x90_DisDllShutdownSR_MASK 0x8000000 |
| 1399 | #define D18F2x90_Reserved_31_28_OFFSET 28 |
| 1400 | #define D18F2x90_Reserved_31_28_WIDTH 4 |
| 1401 | #define D18F2x90_Reserved_31_28_MASK 0xf0000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1402 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1403 | /// D18F2x90 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1404 | typedef union { |
| 1405 | struct { ///< |
| 1406 | UINT32 Reserved_0_0:1 ; ///< |
| 1407 | UINT32 ExitSelfRef:1 ; ///< |
| 1408 | UINT32 Reserved_16_2:15; ///< |
| 1409 | UINT32 EnterSelfRef:1 ; ///< |
| 1410 | UINT32 Reserved_19_18:2 ; ///< |
| 1411 | UINT32 DynPageCloseEn:1 ; ///< |
| 1412 | UINT32 IdleCycInit:2 ; ///< |
| 1413 | UINT32 ForceAutoPchg:1 ; ///< |
| 1414 | UINT32 Reserved_24_24:1 ; ///< |
| 1415 | UINT32 EnDispAutoPrecharge:1 ; ///< |
| 1416 | UINT32 DbeSkidBufDis:1 ; ///< |
| 1417 | UINT32 DisDllShutdownSR:1 ; ///< |
| 1418 | UINT32 Reserved_31_28:4 ; ///< |
| 1419 | } Field; ///< |
| 1420 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1421 | } D18F2x90_STRUCT; |
| 1422 | |
| 1423 | // **** D18F2x94 Register Definition **** |
| 1424 | // Address |
| 1425 | #define D18F2x94_ADDRESS 0x94 |
| 1426 | |
| 1427 | // Type |
| 1428 | #define D18F2x94_TYPE TYPE_D18F2 |
| 1429 | // Field Data |
| 1430 | #define D18F2x94_MemClkFreq_OFFSET 0 |
| 1431 | #define D18F2x94_MemClkFreq_WIDTH 5 |
| 1432 | #define D18F2x94_MemClkFreq_MASK 0x1f |
| 1433 | #define D18F2x94_Reserved_6_5_OFFSET 5 |
| 1434 | #define D18F2x94_Reserved_6_5_WIDTH 2 |
| 1435 | #define D18F2x94_Reserved_6_5_MASK 0x60 |
| 1436 | #define D18F2x94_MemClkFreqVal_OFFSET 7 |
| 1437 | #define D18F2x94_MemClkFreqVal_WIDTH 1 |
| 1438 | #define D18F2x94_MemClkFreqVal_MASK 0x80 |
| 1439 | #define D18F2x94_Reserved_9_8_OFFSET 8 |
| 1440 | #define D18F2x94_Reserved_9_8_WIDTH 2 |
| 1441 | #define D18F2x94_Reserved_9_8_MASK 0x300 |
| 1442 | #define D18F2x94_ZqcsInterval_OFFSET 10 |
| 1443 | #define D18F2x94_ZqcsInterval_WIDTH 2 |
| 1444 | #define D18F2x94_ZqcsInterval_MASK 0xc00 |
| 1445 | #define D18F2x94_Reserved_13_12_OFFSET 12 |
| 1446 | #define D18F2x94_Reserved_13_12_WIDTH 2 |
| 1447 | #define D18F2x94_Reserved_13_12_MASK 0x3000 |
| 1448 | #define D18F2x94_DisDramInterface_OFFSET 14 |
| 1449 | #define D18F2x94_DisDramInterface_WIDTH 1 |
| 1450 | #define D18F2x94_DisDramInterface_MASK 0x4000 |
| 1451 | #define D18F2x94_PowerDownEn_OFFSET 15 |
| 1452 | #define D18F2x94_PowerDownEn_WIDTH 1 |
| 1453 | #define D18F2x94_PowerDownEn_MASK 0x8000 |
| 1454 | #define D18F2x94_PowerDownMode_OFFSET 16 |
| 1455 | #define D18F2x94_PowerDownMode_WIDTH 1 |
| 1456 | #define D18F2x94_PowerDownMode_MASK 0x10000 |
| 1457 | #define D18F2x94_Reserved_19_17_OFFSET 17 |
| 1458 | #define D18F2x94_Reserved_19_17_WIDTH 3 |
| 1459 | #define D18F2x94_Reserved_19_17_MASK 0xe0000 |
| 1460 | #define D18F2x94_SlowAccessMode_OFFSET 20 |
| 1461 | #define D18F2x94_SlowAccessMode_WIDTH 1 |
| 1462 | #define D18F2x94_SlowAccessMode_MASK 0x100000 |
| 1463 | #define D18F2x94_Reserved_21_21_OFFSET 21 |
| 1464 | #define D18F2x94_Reserved_21_21_WIDTH 1 |
| 1465 | #define D18F2x94_Reserved_21_21_MASK 0x200000 |
| 1466 | #define D18F2x94_BankSwizzleMode_OFFSET 22 |
| 1467 | #define D18F2x94_BankSwizzleMode_WIDTH 1 |
| 1468 | #define D18F2x94_BankSwizzleMode_MASK 0x400000 |
| 1469 | #define D18F2x94_ProcOdtDis_OFFSET 23 |
| 1470 | #define D18F2x94_ProcOdtDis_WIDTH 1 |
| 1471 | #define D18F2x94_ProcOdtDis_MASK 0x800000 |
| 1472 | #define D18F2x94_DcqBypassMax_OFFSET 24 |
| 1473 | #define D18F2x94_DcqBypassMax_WIDTH 4 |
| 1474 | #define D18F2x94_DcqBypassMax_MASK 0xf000000 |
| 1475 | #define D18F2x94_FourActWindow_OFFSET 28 |
| 1476 | #define D18F2x94_FourActWindow_WIDTH 4 |
| 1477 | #define D18F2x94_FourActWindow_MASK 0xf0000000 |
| 1478 | |
| 1479 | /// D18F2x94 |
| 1480 | typedef union { |
| 1481 | struct { ///< |
| 1482 | UINT32 MemClkFreq:5 ; ///< |
| 1483 | UINT32 Reserved_6_5:2 ; ///< |
| 1484 | UINT32 MemClkFreqVal:1 ; ///< |
| 1485 | UINT32 Reserved_9_8:2 ; ///< |
| 1486 | UINT32 ZqcsInterval:2 ; ///< |
| 1487 | UINT32 Reserved_13_12:3 ; ///< |
| 1488 | UINT32 DisDramInterface:1 ; ///< |
| 1489 | UINT32 PowerDownEn:1 ; ///< |
| 1490 | UINT32 PowerDownMode:1 ; ///< |
| 1491 | UINT32 Reserved_19_17:3 ; ///< |
| 1492 | UINT32 SlowAccessMode:1 ; ///< |
| 1493 | UINT32 Reserved_21_21:1 ; ///< |
| 1494 | UINT32 BankSwizzleMode:1 ; ///< |
| 1495 | UINT32 ProcOdtDis:1 ; ///< |
| 1496 | UINT32 DcqBypassMax:4 ; ///< |
| 1497 | UINT32 FourActWindow:4 ; ///< |
| 1498 | } Field; ///< |
| 1499 | UINT32 Value; ///< |
| 1500 | } D18F2x94_STRUCT; |
| 1501 | |
| 1502 | // **** D18F2x98 Register Definition **** |
| 1503 | // Address |
| 1504 | #define D18F2x98_ADDRESS 0x98 |
| 1505 | |
| 1506 | // Type |
| 1507 | #define D18F2x98_TYPE TYPE_D18F2 |
| 1508 | // Field Data |
| 1509 | #define D18F2x98_DctOffset_OFFSET 0 |
| 1510 | #define D18F2x98_DctOffset_WIDTH 30 |
| 1511 | #define D18F2x98_DctOffset_MASK 0x3fffffff |
| 1512 | #define D18F2x98_DctAccessWrite_OFFSET 30 |
| 1513 | #define D18F2x98_DctAccessWrite_WIDTH 1 |
| 1514 | #define D18F2x98_DctAccessWrite_MASK 0x40000000 |
| 1515 | #define D18F2x98_DctAccessDone_OFFSET 31 |
| 1516 | #define D18F2x98_DctAccessDone_WIDTH 1 |
| 1517 | #define D18F2x98_DctAccessDone_MASK 0x80000000 |
| 1518 | |
| 1519 | /// D18F2x98 |
| 1520 | typedef union { |
| 1521 | struct { ///< |
| 1522 | UINT32 DctOffset:30; ///< |
| 1523 | UINT32 DctAccessWrite:1 ; ///< |
| 1524 | UINT32 DctAccessDone:1 ; ///< |
| 1525 | } Field; ///< |
| 1526 | UINT32 Value; ///< |
| 1527 | } D18F2x98_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1528 | |
| 1529 | // **** D18F2x9C Register Definition **** |
| 1530 | // Address |
| 1531 | #define D18F2x9C_ADDRESS 0x9c |
| 1532 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1533 | // Type |
| 1534 | #define D18F2x9C_TYPE TYPE_D18F2 |
| 1535 | // Field Data |
| 1536 | #define D18F2x9C_DctDataPort_OFFSET 0 |
| 1537 | #define D18F2x9C_DctDataPort_WIDTH 32 |
| 1538 | #define D18F2x9C_DctDataPort_MASK 0xffffffff |
| 1539 | |
| 1540 | /// D18F2x9C |
| 1541 | typedef union { |
| 1542 | struct { ///< |
| 1543 | UINT32 DctDataPort:32; ///< |
| 1544 | } Field; ///< |
| 1545 | UINT32 Value; ///< |
| 1546 | } D18F2x9C_STRUCT; |
| 1547 | |
| 1548 | // **** D18F2x09C_x0D0FE00A Register Definition **** |
| 1549 | // Address |
| 1550 | #define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A |
| 1551 | |
| 1552 | // Type |
| 1553 | #define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C |
| 1554 | // Field Data |
| 1555 | #define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 |
| 1556 | #define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 |
| 1557 | #define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF |
| 1558 | #define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 |
| 1559 | #define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 |
| 1560 | #define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 |
| 1561 | #define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 |
| 1562 | #define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 |
| 1563 | #define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 |
| 1564 | #define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 |
| 1565 | #define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 |
| 1566 | #define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 |
| 1567 | #define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 |
| 1568 | #define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 |
| 1569 | #define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 |
| 1570 | #define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 |
| 1571 | #define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 |
| 1572 | #define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 |
| 1573 | |
| 1574 | /// D18F2x09C_x0D0FE00A |
| 1575 | typedef union { |
| 1576 | struct { ///< |
| 1577 | UINT32 Reserved_3_0:4; ///< |
| 1578 | UINT32 SkewMemClk:1; ///< |
| 1579 | UINT32 Reserved_11_5:7; ///< |
| 1580 | UINT32 CsrPhySrPllPdMode:2; ///< |
| 1581 | UINT32 SelCsrPllPdMode:1; ///< |
| 1582 | UINT32 Reserved_31_15:17; ///< |
| 1583 | } Field; ///< |
| 1584 | UINT32 Value; ///< |
| 1585 | } D18F2x09C_x0D0FE00A_STRUCT; |
| 1586 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1587 | // **** D18F2xA0 Register Definition **** |
| 1588 | // Address |
| 1589 | #define D18F2xA0_ADDRESS 0xa0 |
| 1590 | |
| 1591 | // Type |
| 1592 | #define D18F2xA0_TYPE TYPE_D18F2 |
| 1593 | // Field Data |
| 1594 | #define D18F2xA0_Reserved_31_0_OFFSET 0 |
| 1595 | #define D18F2xA0_Reserved_31_0_WIDTH 32 |
| 1596 | #define D18F2xA0_Reserved_31_0_MASK 0xffffffff |
| 1597 | |
| 1598 | /// D18F2xA0 |
| 1599 | typedef union { |
| 1600 | struct { ///< |
| 1601 | UINT32 Reserved_31_0:32; ///< |
| 1602 | } Field; ///< |
| 1603 | UINT32 Value; ///< |
| 1604 | } D18F2xA0_STRUCT; |
| 1605 | |
| 1606 | // **** D18F2xA4 Register Definition **** |
| 1607 | // Address |
| 1608 | #define D18F2xA4_ADDRESS 0xa4 |
| 1609 | |
| 1610 | // Type |
| 1611 | #define D18F2xA4_TYPE TYPE_D18F2 |
| 1612 | // Field Data |
| 1613 | #define D18F2xA4_DoubleTrefRateEn_OFFSET 0 |
| 1614 | #define D18F2xA4_DoubleTrefRateEn_WIDTH 1 |
| 1615 | #define D18F2xA4_DoubleTrefRateEn_MASK 0x1 |
| 1616 | #define D18F2xA4_ThrottleEn_OFFSET 1 |
| 1617 | #define D18F2xA4_ThrottleEn_WIDTH 2 |
| 1618 | #define D18F2xA4_ThrottleEn_MASK 0x6 |
| 1619 | #define D18F2xA4_Reserved_31_3_OFFSET 3 |
| 1620 | #define D18F2xA4_Reserved_31_3_WIDTH 29 |
| 1621 | #define D18F2xA4_Reserved_31_3_MASK 0xfffffff8 |
| 1622 | |
| 1623 | /// D18F2xA4 |
| 1624 | typedef union { |
| 1625 | struct { ///< |
| 1626 | UINT32 DoubleTrefRateEn:1 ; ///< |
| 1627 | UINT32 ThrottleEn:2 ; ///< |
| 1628 | UINT32 Reserved_31_3:29; ///< |
| 1629 | } Field; ///< |
| 1630 | UINT32 Value; ///< |
| 1631 | } D18F2xA4_STRUCT; |
| 1632 | |
| 1633 | // **** D18F2xA8 Register Definition **** |
| 1634 | // Address |
| 1635 | #define D18F2xA8_ADDRESS 0xa8 |
| 1636 | |
| 1637 | // Type |
| 1638 | #define D18F2xA8_TYPE TYPE_D18F2 |
| 1639 | // Field Data |
| 1640 | #define D18F2xA8_Reserved_19_0_OFFSET 0 |
| 1641 | #define D18F2xA8_Reserved_19_0_WIDTH 20 |
| 1642 | #define D18F2xA8_Reserved_19_0_MASK 0xfffff |
| 1643 | #define D18F2xA8_BankSwap_OFFSET 20 |
| 1644 | #define D18F2xA8_BankSwap_WIDTH 1 |
| 1645 | #define D18F2xA8_BankSwap_MASK 0x100000 |
| 1646 | #define D18F2xA8_DbeGskMemClkAlignMode_OFFSET 21 |
| 1647 | #define D18F2xA8_DbeGskMemClkAlignMode_WIDTH 2 |
| 1648 | #define D18F2xA8_DbeGskMemClkAlignMode_MASK 0x600000 |
| 1649 | #define D18F2xA8_Reserved_31_23_OFFSET 23 |
| 1650 | #define D18F2xA8_Reserved_31_23_WIDTH 9 |
| 1651 | #define D18F2xA8_Reserved_31_23_MASK 0xff800000 |
| 1652 | |
| 1653 | /// D18F2xA8 |
| 1654 | typedef union { |
| 1655 | struct { ///< |
| 1656 | UINT32 Reserved_19_0:20; ///< |
| 1657 | UINT32 BankSwap:1 ; ///< |
| 1658 | UINT32 DbeGskMemClkAlignMode:2 ; ///< |
| 1659 | UINT32 Reserved_31_23:9 ; ///< |
| 1660 | } Field; ///< |
| 1661 | UINT32 Value; ///< |
| 1662 | } D18F2xA8_STRUCT; |
| 1663 | |
| 1664 | // **** D18F2xAC Register Definition **** |
| 1665 | // Address |
| 1666 | #define D18F2xAC_ADDRESS 0xac |
| 1667 | |
| 1668 | // Type |
| 1669 | #define D18F2xAC_TYPE TYPE_D18F2 |
| 1670 | // Field Data |
| 1671 | #define D18F2xAC_MemTempHot_OFFSET 0 |
| 1672 | #define D18F2xAC_MemTempHot_WIDTH 1 |
| 1673 | #define D18F2xAC_MemTempHot_MASK 0x1 |
| 1674 | #define D18F2xAC_Reserved_31_1_OFFSET 1 |
| 1675 | #define D18F2xAC_Reserved_31_1_WIDTH 31 |
| 1676 | #define D18F2xAC_Reserved_31_1_MASK 0xfffffffe |
| 1677 | |
| 1678 | /// D18F2xAC |
| 1679 | typedef union { |
| 1680 | struct { ///< |
| 1681 | UINT32 MemTempHot:1 ; ///< |
| 1682 | UINT32 Reserved_31_1:31; ///< |
| 1683 | } Field; ///< |
| 1684 | UINT32 Value; ///< |
| 1685 | } D18F2xAC_STRUCT; |
| 1686 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1687 | // **** D18F2xB0 Register Definition **** |
| 1688 | // Address |
| 1689 | #define D18F2xB0_ADDRESS 0xb0 |
| 1690 | |
| 1691 | // Type |
| 1692 | #define D18F2xB0_TYPE TYPE_D18F2 |
| 1693 | // Field Data |
| 1694 | #define D18F2xB0_TscLow_OFFSET 0 |
| 1695 | #define D18F2xB0_TscLow_WIDTH 32 |
| 1696 | #define D18F2xB0_TscLow_MASK 0xffffffff |
| 1697 | |
| 1698 | /// D18F2xB0 |
| 1699 | typedef union { |
| 1700 | struct { ///< |
| 1701 | UINT32 TscLow:32; ///< |
| 1702 | } Field; ///< |
| 1703 | UINT32 Value; ///< |
| 1704 | } D18F2xB0_STRUCT; |
| 1705 | |
| 1706 | // **** D18F2xB4 Register Definition **** |
| 1707 | // Address |
| 1708 | #define D18F2xB4_ADDRESS 0xb4 |
| 1709 | |
| 1710 | // Type |
| 1711 | #define D18F2xB4_TYPE TYPE_D18F2 |
| 1712 | // Field Data |
| 1713 | #define D18F2xB4_TscHigh_OFFSET 0 |
| 1714 | #define D18F2xB4_TscHigh_WIDTH 32 |
| 1715 | #define D18F2xB4_TscHigh_MASK 0xffffffff |
| 1716 | |
| 1717 | /// D18F2xB4 |
| 1718 | typedef union { |
| 1719 | struct { ///< |
| 1720 | UINT32 TscHigh:32; ///< |
| 1721 | } Field; ///< |
| 1722 | UINT32 Value; ///< |
| 1723 | } D18F2xB4_STRUCT; |
| 1724 | |
| 1725 | // **** D18F2xB8 Register Definition **** |
| 1726 | // Address |
| 1727 | #define D18F2xB8_ADDRESS 0xb8 |
| 1728 | |
| 1729 | // Type |
| 1730 | #define D18F2xB8_TYPE TYPE_D18F2 |
| 1731 | // Field Data |
| 1732 | #define D18F2xB8_TrcBufDramBase_35_24__OFFSET 0 |
| 1733 | #define D18F2xB8_TrcBufDramBase_35_24__WIDTH 12 |
| 1734 | #define D18F2xB8_TrcBufDramBase_35_24__MASK 0xfff |
| 1735 | #define D18F2xB8_TrcBufDramBase_39_36__OFFSET 12 |
| 1736 | #define D18F2xB8_TrcBufDramBase_39_36__WIDTH 4 |
| 1737 | #define D18F2xB8_TrcBufDramBase_39_36__MASK 0xf000 |
| 1738 | #define D18F2xB8_TrcBufDramLimit_35_24__OFFSET 16 |
| 1739 | #define D18F2xB8_TrcBufDramLimit_35_24__WIDTH 12 |
| 1740 | #define D18F2xB8_TrcBufDramLimit_35_24__MASK 0xfff0000 |
| 1741 | #define D18F2xB8_TrcBufDramLimit_39_36__OFFSET 28 |
| 1742 | #define D18F2xB8_TrcBufDramLimit_39_36__WIDTH 4 |
| 1743 | #define D18F2xB8_TrcBufDramLimit_39_36__MASK 0xf0000000 |
| 1744 | |
| 1745 | /// D18F2xB8 |
| 1746 | typedef union { |
| 1747 | struct { ///< |
| 1748 | UINT32 TrcBufDramBase_35_24_:12; ///< |
| 1749 | UINT32 TrcBufDramBase_39_36_:4 ; ///< |
| 1750 | UINT32 TrcBufDramLimit_35_24_:12; ///< |
| 1751 | UINT32 TrcBufDramLimit_39_36_:4 ; ///< |
| 1752 | } Field; ///< |
| 1753 | UINT32 Value; ///< |
| 1754 | } D18F2xB8_STRUCT; |
| 1755 | |
| 1756 | // **** D18F2xBC Register Definition **** |
| 1757 | // Address |
| 1758 | #define D18F2xBC_ADDRESS 0xbc |
| 1759 | |
| 1760 | // Type |
| 1761 | #define D18F2xBC_TYPE TYPE_D18F2 |
| 1762 | // Field Data |
| 1763 | #define D18F2xBC_TrcBufAdrPtr_35_6__OFFSET 0 |
| 1764 | #define D18F2xBC_TrcBufAdrPtr_35_6__WIDTH 30 |
| 1765 | #define D18F2xBC_TrcBufAdrPtr_35_6__MASK 0x3fffffff |
| 1766 | #define D18F2xBC_TrcBufAdrPtr_37_36__OFFSET 30 |
| 1767 | #define D18F2xBC_TrcBufAdrPtr_37_36__WIDTH 2 |
| 1768 | #define D18F2xBC_TrcBufAdrPtr_37_36__MASK 0xc0000000 |
| 1769 | |
| 1770 | /// D18F2xBC |
| 1771 | typedef union { |
| 1772 | struct { ///< |
| 1773 | UINT32 TrcBufAdrPtr_35_6_:30; ///< |
| 1774 | UINT32 TrcBufAdrPtr_37_36_:2 ; ///< |
| 1775 | } Field; ///< |
| 1776 | UINT32 Value; ///< |
| 1777 | } D18F2xBC_STRUCT; |
| 1778 | |
| 1779 | // **** D18F2xC0 Register Definition **** |
| 1780 | // Address |
| 1781 | #define D18F2xC0_ADDRESS 0xc0 |
| 1782 | |
| 1783 | // Type |
| 1784 | #define D18F2xC0_TYPE TYPE_D18F2 |
| 1785 | // Field Data |
| 1786 | #define D18F2xC0_TraceModeEn_OFFSET 0 |
| 1787 | #define D18F2xC0_TraceModeEn_WIDTH 1 |
| 1788 | #define D18F2xC0_TraceModeEn_MASK 0x1 |
| 1789 | #define D18F2xC0_TcbModeEn_OFFSET 1 |
| 1790 | #define D18F2xC0_TcbModeEn_WIDTH 1 |
| 1791 | #define D18F2xC0_TcbModeEn_MASK 0x2 |
| 1792 | #define D18F2xC0_Reserved_3_2_OFFSET 2 |
| 1793 | #define D18F2xC0_Reserved_3_2_WIDTH 2 |
| 1794 | #define D18F2xC0_Reserved_3_2_MASK 0xc |
| 1795 | #define D18F2xC0_ncHTEn0_OFFSET 4 |
| 1796 | #define D18F2xC0_ncHTEn0_WIDTH 1 |
| 1797 | #define D18F2xC0_ncHTEn0_MASK 0x10 |
| 1798 | #define D18F2xC0_ncHTEn1_OFFSET 5 |
| 1799 | #define D18F2xC0_ncHTEn1_WIDTH 1 |
| 1800 | #define D18F2xC0_ncHTEn1_MASK 0x20 |
| 1801 | #define D18F2xC0_Reserved_11_6_OFFSET 6 |
| 1802 | #define D18F2xC0_Reserved_11_6_WIDTH 6 |
| 1803 | #define D18F2xC0_Reserved_11_6_MASK 0xfc0 |
| 1804 | #define D18F2xC0_FlushTcb_OFFSET 12 |
| 1805 | #define D18F2xC0_FlushTcb_WIDTH 1 |
| 1806 | #define D18F2xC0_FlushTcb_MASK 0x1000 |
| 1807 | #define D18F2xC0_Reserved_14_13_OFFSET 13 |
| 1808 | #define D18F2xC0_Reserved_14_13_WIDTH 2 |
| 1809 | #define D18F2xC0_Reserved_14_13_MASK 0x6000 |
| 1810 | #define D18F2xC0_TraceCmdMtchReq_OFFSET 15 |
| 1811 | #define D18F2xC0_TraceCmdMtchReq_WIDTH 1 |
| 1812 | #define D18F2xC0_TraceCmdMtchReq_MASK 0x8000 |
| 1813 | #define D18F2xC0_Reserved_17_16_OFFSET 16 |
| 1814 | #define D18F2xC0_Reserved_17_16_WIDTH 2 |
| 1815 | #define D18F2xC0_Reserved_17_16_MASK 0x30000 |
| 1816 | #define D18F2xC0_MultiLevelSingleEvent_OFFSET 18 |
| 1817 | #define D18F2xC0_MultiLevelSingleEvent_WIDTH 1 |
| 1818 | #define D18F2xC0_MultiLevelSingleEvent_MASK 0x40000 |
| 1819 | #define D18F2xC0_MultiLevelMultiEvent_OFFSET 19 |
| 1820 | #define D18F2xC0_MultiLevelMultiEvent_WIDTH 1 |
| 1821 | #define D18F2xC0_MultiLevelMultiEvent_MASK 0x80000 |
| 1822 | #define D18F2xC0_Reserved_20_20_OFFSET 20 |
| 1823 | #define D18F2xC0_Reserved_20_20_WIDTH 1 |
| 1824 | #define D18F2xC0_Reserved_20_20_MASK 0x100000 |
| 1825 | #define D18F2xC0_TraceSrcDstAndEn_OFFSET 21 |
| 1826 | #define D18F2xC0_TraceSrcDstAndEn_WIDTH 1 |
| 1827 | #define D18F2xC0_TraceSrcDstAndEn_MASK 0x200000 |
| 1828 | #define D18F2xC0_TraceFlushOnDbReq_OFFSET 22 |
| 1829 | #define D18F2xC0_TraceFlushOnDbReq_WIDTH 1 |
| 1830 | #define D18F2xC0_TraceFlushOnDbReq_MASK 0x400000 |
| 1831 | #define D18F2xC0_TraceOneShotEn_OFFSET 23 |
| 1832 | #define D18F2xC0_TraceOneShotEn_WIDTH 1 |
| 1833 | #define D18F2xC0_TraceOneShotEn_MASK 0x800000 |
| 1834 | #define D18F2xC0_Reserved_31_24_OFFSET 24 |
| 1835 | #define D18F2xC0_Reserved_31_24_WIDTH 8 |
| 1836 | #define D18F2xC0_Reserved_31_24_MASK 0xff000000 |
| 1837 | |
| 1838 | /// D18F2xC0 |
| 1839 | typedef union { |
| 1840 | struct { ///< |
| 1841 | UINT32 TraceModeEn:1 ; ///< |
| 1842 | UINT32 TcbModeEn:1 ; ///< |
| 1843 | UINT32 Reserved_3_2:2 ; ///< |
| 1844 | UINT32 ncHTEn0:1 ; ///< |
| 1845 | UINT32 ncHTEn1:1 ; ///< |
| 1846 | UINT32 Reserved_11_6:6 ; ///< |
| 1847 | UINT32 FlushTcb:1 ; ///< |
| 1848 | UINT32 Reserved_14_13:2 ; ///< |
| 1849 | UINT32 TraceCmdMtchReq:1 ; ///< |
| 1850 | UINT32 Reserved_17_16:2 ; ///< |
| 1851 | UINT32 MultiLevelSingleEvent:1 ; ///< |
| 1852 | UINT32 MultiLevelMultiEvent:1 ; ///< |
| 1853 | UINT32 Reserved_20_20:1 ; ///< |
| 1854 | UINT32 TraceSrcDstAndEn:1 ; ///< |
| 1855 | UINT32 TraceFlushOnDbReq:1 ; ///< |
| 1856 | UINT32 TraceOneShotEn:1 ; ///< |
| 1857 | UINT32 Reserved_31_24:8 ; ///< |
| 1858 | } Field; ///< |
| 1859 | UINT32 Value; ///< |
| 1860 | } D18F2xC0_STRUCT; |
| 1861 | |
| 1862 | // **** D18F2xC4 Register Definition **** |
| 1863 | // Address |
| 1864 | #define D18F2xC4_ADDRESS 0xc4 |
| 1865 | |
| 1866 | // Type |
| 1867 | #define D18F2xC4_TYPE TYPE_D18F2 |
| 1868 | // Field Data |
| 1869 | #define D18F2xC4_StartCmd0_OFFSET 0 |
| 1870 | #define D18F2xC4_StartCmd0_WIDTH 1 |
| 1871 | #define D18F2xC4_StartCmd0_MASK 0x1 |
| 1872 | #define D18F2xC4_StartCmd1_OFFSET 1 |
| 1873 | #define D18F2xC4_StartCmd1_WIDTH 1 |
| 1874 | #define D18F2xC4_StartCmd1_MASK 0x2 |
| 1875 | #define D18F2xC4_Reserved_21_2_OFFSET 2 |
| 1876 | #define D18F2xC4_Reserved_21_2_WIDTH 20 |
| 1877 | #define D18F2xC4_Reserved_21_2_MASK 0x3ffffc |
| 1878 | #define D18F2xC4_StartDbRdy_OFFSET 22 |
| 1879 | #define D18F2xC4_StartDbRdy_WIDTH 1 |
| 1880 | #define D18F2xC4_StartDbRdy_MASK 0x400000 |
| 1881 | #define D18F2xC4_StartDbReq_OFFSET 23 |
| 1882 | #define D18F2xC4_StartDbReq_WIDTH 1 |
| 1883 | #define D18F2xC4_StartDbReq_MASK 0x800000 |
| 1884 | #define D18F2xC4_StartPerfMon0_OFFSET 24 |
| 1885 | #define D18F2xC4_StartPerfMon0_WIDTH 1 |
| 1886 | #define D18F2xC4_StartPerfMon0_MASK 0x1000000 |
| 1887 | #define D18F2xC4_StartPerfMon1_OFFSET 25 |
| 1888 | #define D18F2xC4_StartPerfMon1_WIDTH 1 |
| 1889 | #define D18F2xC4_StartPerfMon1_MASK 0x2000000 |
| 1890 | #define D18F2xC4_StartPerfMon2_OFFSET 26 |
| 1891 | #define D18F2xC4_StartPerfMon2_WIDTH 1 |
| 1892 | #define D18F2xC4_StartPerfMon2_MASK 0x4000000 |
| 1893 | #define D18F2xC4_StartPerfMon3_OFFSET 27 |
| 1894 | #define D18F2xC4_StartPerfMon3_WIDTH 1 |
| 1895 | #define D18F2xC4_StartPerfMon3_MASK 0x8000000 |
| 1896 | #define D18F2xC4_StartMCE_OFFSET 28 |
| 1897 | #define D18F2xC4_StartMCE_WIDTH 1 |
| 1898 | #define D18F2xC4_StartMCE_MASK 0x10000000 |
| 1899 | #define D18F2xC4_Reserved_29_29_OFFSET 29 |
| 1900 | #define D18F2xC4_Reserved_29_29_WIDTH 1 |
| 1901 | #define D18F2xC4_Reserved_29_29_MASK 0x20000000 |
| 1902 | #define D18F2xC4_StartTSC_OFFSET 30 |
| 1903 | #define D18F2xC4_StartTSC_WIDTH 1 |
| 1904 | #define D18F2xC4_StartTSC_MASK 0x40000000 |
| 1905 | #define D18F2xC4_StartNow_OFFSET 31 |
| 1906 | #define D18F2xC4_StartNow_WIDTH 1 |
| 1907 | #define D18F2xC4_StartNow_MASK 0x80000000 |
| 1908 | |
| 1909 | /// D18F2xC4 |
| 1910 | typedef union { |
| 1911 | struct { ///< |
| 1912 | UINT32 StartCmd0:1 ; ///< |
| 1913 | UINT32 StartCmd1:1 ; ///< |
| 1914 | UINT32 Reserved_21_2:20; ///< |
| 1915 | UINT32 StartDbRdy:1 ; ///< |
| 1916 | UINT32 StartDbReq:1 ; ///< |
| 1917 | UINT32 StartPerfMon0:1 ; ///< |
| 1918 | UINT32 StartPerfMon1:1 ; ///< |
| 1919 | UINT32 StartPerfMon2:1 ; ///< |
| 1920 | UINT32 StartPerfMon3:1 ; ///< |
| 1921 | UINT32 StartMCE:1 ; ///< |
| 1922 | UINT32 Reserved_29_29:1 ; ///< |
| 1923 | UINT32 StartTSC:1 ; ///< |
| 1924 | UINT32 StartNow:1 ; ///< |
| 1925 | } Field; ///< |
| 1926 | UINT32 Value; ///< |
| 1927 | } D18F2xC4_STRUCT; |
| 1928 | |
| 1929 | // **** D18F2xC8 Register Definition **** |
| 1930 | // Address |
| 1931 | #define D18F2xC8_ADDRESS 0xc8 |
| 1932 | |
| 1933 | // Type |
| 1934 | #define D18F2xC8_TYPE TYPE_D18F2 |
| 1935 | // Field Data |
| 1936 | #define D18F2xC8_StopCmd0_OFFSET 0 |
| 1937 | #define D18F2xC8_StopCmd0_WIDTH 1 |
| 1938 | #define D18F2xC8_StopCmd0_MASK 0x1 |
| 1939 | #define D18F2xC8_StopCmd1_OFFSET 1 |
| 1940 | #define D18F2xC8_StopCmd1_WIDTH 1 |
| 1941 | #define D18F2xC8_StopCmd1_MASK 0x2 |
| 1942 | #define D18F2xC8_Reserved_21_2_OFFSET 2 |
| 1943 | #define D18F2xC8_Reserved_21_2_WIDTH 20 |
| 1944 | #define D18F2xC8_Reserved_21_2_MASK 0x3ffffc |
| 1945 | #define D18F2xC8_StopDbRdy_OFFSET 22 |
| 1946 | #define D18F2xC8_StopDbRdy_WIDTH 1 |
| 1947 | #define D18F2xC8_StopDbRdy_MASK 0x400000 |
| 1948 | #define D18F2xC8_StopDbReq_OFFSET 23 |
| 1949 | #define D18F2xC8_StopDbReq_WIDTH 1 |
| 1950 | #define D18F2xC8_StopDbReq_MASK 0x800000 |
| 1951 | #define D18F2xC8_StopPerfMon0_OFFSET 24 |
| 1952 | #define D18F2xC8_StopPerfMon0_WIDTH 1 |
| 1953 | #define D18F2xC8_StopPerfMon0_MASK 0x1000000 |
| 1954 | #define D18F2xC8_StopPerfMon1_OFFSET 25 |
| 1955 | #define D18F2xC8_StopPerfMon1_WIDTH 1 |
| 1956 | #define D18F2xC8_StopPerfMon1_MASK 0x2000000 |
| 1957 | #define D18F2xC8_StopPerfMon2_OFFSET 26 |
| 1958 | #define D18F2xC8_StopPerfMon2_WIDTH 1 |
| 1959 | #define D18F2xC8_StopPerfMon2_MASK 0x4000000 |
| 1960 | #define D18F2xC8_StopPerfMon3_OFFSET 27 |
| 1961 | #define D18F2xC8_StopPerfMon3_WIDTH 1 |
| 1962 | #define D18F2xC8_StopPerfMon3_MASK 0x8000000 |
| 1963 | #define D18F2xC8_StopMCE_OFFSET 28 |
| 1964 | #define D18F2xC8_StopMCE_WIDTH 1 |
| 1965 | #define D18F2xC8_StopMCE_MASK 0x10000000 |
| 1966 | #define D18F2xC8_StopTrcBufFull_OFFSET 29 |
| 1967 | #define D18F2xC8_StopTrcBufFull_WIDTH 1 |
| 1968 | #define D18F2xC8_StopTrcBufFull_MASK 0x20000000 |
| 1969 | #define D18F2xC8_StopTSC_OFFSET 30 |
| 1970 | #define D18F2xC8_StopTSC_WIDTH 1 |
| 1971 | #define D18F2xC8_StopTSC_MASK 0x40000000 |
| 1972 | #define D18F2xC8_StopNow_OFFSET 31 |
| 1973 | #define D18F2xC8_StopNow_WIDTH 1 |
| 1974 | #define D18F2xC8_StopNow_MASK 0x80000000 |
| 1975 | |
| 1976 | /// D18F2xC8 |
| 1977 | typedef union { |
| 1978 | struct { ///< |
| 1979 | UINT32 StopCmd0:1 ; ///< |
| 1980 | UINT32 StopCmd1:1 ; ///< |
| 1981 | UINT32 Reserved_21_2:20; ///< |
| 1982 | UINT32 StopDbRdy:1 ; ///< |
| 1983 | UINT32 StopDbReq:1 ; ///< |
| 1984 | UINT32 StopPerfMon0:1 ; ///< |
| 1985 | UINT32 StopPerfMon1:1 ; ///< |
| 1986 | UINT32 StopPerfMon2:1 ; ///< |
| 1987 | UINT32 StopPerfMon3:1 ; ///< |
| 1988 | UINT32 StopMCE:1 ; ///< |
| 1989 | UINT32 StopTrcBufFull:1 ; ///< |
| 1990 | UINT32 StopTSC:1 ; ///< |
| 1991 | UINT32 StopNow:1 ; ///< |
| 1992 | } Field; ///< |
| 1993 | UINT32 Value; ///< |
| 1994 | } D18F2xC8_STRUCT; |
| 1995 | |
| 1996 | // **** D18F2xCC Register Definition **** |
| 1997 | // Address |
| 1998 | #define D18F2xCC_ADDRESS 0xcc |
| 1999 | |
| 2000 | // Type |
| 2001 | #define D18F2xCC_TYPE TYPE_D18F2 |
| 2002 | // Field Data |
| 2003 | #define D18F2xCC_TrcCmd0_OFFSET 0 |
| 2004 | #define D18F2xCC_TrcCmd0_WIDTH 1 |
| 2005 | #define D18F2xCC_TrcCmd0_MASK 0x1 |
| 2006 | #define D18F2xCC_TrcCmd1_OFFSET 1 |
| 2007 | #define D18F2xCC_TrcCmd1_WIDTH 1 |
| 2008 | #define D18F2xCC_TrcCmd1_MASK 0x2 |
| 2009 | #define D18F2xCC_Reserved_3_2_OFFSET 2 |
| 2010 | #define D18F2xCC_Reserved_3_2_WIDTH 2 |
| 2011 | #define D18F2xCC_Reserved_3_2_MASK 0xc |
| 2012 | #define D18F2xCC_TrcRsp0_OFFSET 4 |
| 2013 | #define D18F2xCC_TrcRsp0_WIDTH 1 |
| 2014 | #define D18F2xCC_TrcRsp0_MASK 0x10 |
| 2015 | #define D18F2xCC_TrcRsp1_OFFSET 5 |
| 2016 | #define D18F2xCC_TrcRsp1_WIDTH 1 |
| 2017 | #define D18F2xCC_TrcRsp1_MASK 0x20 |
| 2018 | #define D18F2xCC_Reserved_11_6_OFFSET 6 |
| 2019 | #define D18F2xCC_Reserved_11_6_WIDTH 6 |
| 2020 | #define D18F2xCC_Reserved_11_6_MASK 0xfc0 |
| 2021 | #define D18F2xCC_TrcDat0_OFFSET 12 |
| 2022 | #define D18F2xCC_TrcDat0_WIDTH 1 |
| 2023 | #define D18F2xCC_TrcDat0_MASK 0x1000 |
| 2024 | #define D18F2xCC_TrcDat1_OFFSET 13 |
| 2025 | #define D18F2xCC_TrcDat1_WIDTH 1 |
| 2026 | #define D18F2xCC_TrcDat1_MASK 0x2000 |
| 2027 | #define D18F2xCC_MultiDatXbarSel_OFFSET 14 |
| 2028 | #define D18F2xCC_MultiDatXbarSel_WIDTH 1 |
| 2029 | #define D18F2xCC_MultiDatXbarSel_MASK 0x4000 |
| 2030 | #define D18F2xCC_TrcCmdSrcPtr_OFFSET 15 |
| 2031 | #define D18F2xCC_TrcCmdSrcPtr_WIDTH 7 |
| 2032 | #define D18F2xCC_TrcCmdSrcPtr_MASK 0x3f8000 |
| 2033 | #define D18F2xCC_MultiTscCapture_OFFSET 22 |
| 2034 | #define D18F2xCC_MultiTscCapture_WIDTH 1 |
| 2035 | #define D18F2xCC_MultiTscCapture_MASK 0x400000 |
| 2036 | #define D18F2xCC_TscBase_OFFSET 23 |
| 2037 | #define D18F2xCC_TscBase_WIDTH 1 |
| 2038 | #define D18F2xCC_TscBase_MASK 0x800000 |
| 2039 | #define D18F2xCC_TrcCmdDstPtr_OFFSET 24 |
| 2040 | #define D18F2xCC_TrcCmdDstPtr_WIDTH 6 |
| 2041 | #define D18F2xCC_TrcCmdDstPtr_MASK 0x3f000000 |
| 2042 | #define D18F2xCC_DisTscCapture_OFFSET 30 |
| 2043 | #define D18F2xCC_DisTscCapture_WIDTH 1 |
| 2044 | #define D18F2xCC_DisTscCapture_MASK 0x40000000 |
| 2045 | #define D18F2xCC_TrcDatSrcDst_OFFSET 31 |
| 2046 | #define D18F2xCC_TrcDatSrcDst_WIDTH 1 |
| 2047 | #define D18F2xCC_TrcDatSrcDst_MASK 0x80000000 |
| 2048 | |
| 2049 | /// D18F2xCC |
| 2050 | typedef union { |
| 2051 | struct { ///< |
| 2052 | UINT32 TrcCmd0:1 ; ///< |
| 2053 | UINT32 TrcCmd1:1 ; ///< |
| 2054 | UINT32 Reserved_3_2:2 ; ///< |
| 2055 | UINT32 TrcRsp0:1 ; ///< |
| 2056 | UINT32 TrcRsp1:1 ; ///< |
| 2057 | UINT32 Reserved_11_6:6 ; ///< |
| 2058 | UINT32 TrcDat0:1 ; ///< |
| 2059 | UINT32 TrcDat1:1 ; ///< |
| 2060 | UINT32 MultiDatXbarSel:1 ; ///< |
| 2061 | UINT32 TrcCmdSrcPtr:7 ; ///< |
| 2062 | UINT32 MultiTscCapture:1 ; ///< |
| 2063 | UINT32 TscBase:1 ; ///< |
| 2064 | UINT32 TrcCmdDstPtr:6 ; ///< |
| 2065 | UINT32 DisTscCapture:1 ; ///< |
| 2066 | UINT32 TrcDatSrcDst:1 ; ///< |
| 2067 | } Field; ///< |
| 2068 | UINT32 Value; ///< |
| 2069 | } D18F2xCC_STRUCT; |
| 2070 | |
| 2071 | // **** D18F2xD0 Register Definition **** |
| 2072 | // Address |
| 2073 | #define D18F2xD0_ADDRESS 0xd0 |
| 2074 | |
| 2075 | // Type |
| 2076 | #define D18F2xD0_TYPE TYPE_D18F2 |
| 2077 | // Field Data |
| 2078 | #define D18F2xD0_HTCmdLow_OFFSET 0 |
| 2079 | #define D18F2xD0_HTCmdLow_WIDTH 32 |
| 2080 | #define D18F2xD0_HTCmdLow_MASK 0xffffffff |
| 2081 | |
| 2082 | /// D18F2xD0 |
| 2083 | typedef union { |
| 2084 | struct { ///< |
| 2085 | UINT32 HTCmdLow:32; ///< |
| 2086 | } Field; ///< |
| 2087 | UINT32 Value; ///< |
| 2088 | } D18F2xD0_STRUCT; |
| 2089 | |
| 2090 | // **** D18F2xD4 Register Definition **** |
| 2091 | // Address |
| 2092 | #define D18F2xD4_ADDRESS 0xd4 |
| 2093 | |
| 2094 | // Type |
| 2095 | #define D18F2xD4_TYPE TYPE_D18F2 |
| 2096 | // Field Data |
| 2097 | #define D18F2xD4_HTCmdHigh_OFFSET 0 |
| 2098 | #define D18F2xD4_HTCmdHigh_WIDTH 32 |
| 2099 | #define D18F2xD4_HTCmdHigh_MASK 0xffffffff |
| 2100 | |
| 2101 | /// D18F2xD4 |
| 2102 | typedef union { |
| 2103 | struct { ///< |
| 2104 | UINT32 HTCmdHigh:32; ///< |
| 2105 | } Field; ///< |
| 2106 | UINT32 Value; ///< |
| 2107 | } D18F2xD4_STRUCT; |
| 2108 | |
| 2109 | // **** D18F2xD8 Register Definition **** |
| 2110 | // Address |
| 2111 | #define D18F2xD8_ADDRESS 0xd8 |
| 2112 | |
| 2113 | // Type |
| 2114 | #define D18F2xD8_TYPE TYPE_D18F2 |
| 2115 | // Field Data |
| 2116 | #define D18F2xD8_HTMaskLow_OFFSET 0 |
| 2117 | #define D18F2xD8_HTMaskLow_WIDTH 32 |
| 2118 | #define D18F2xD8_HTMaskLow_MASK 0xffffffff |
| 2119 | |
| 2120 | /// D18F2xD8 |
| 2121 | typedef union { |
| 2122 | struct { ///< |
| 2123 | UINT32 HTMaskLow:32; ///< |
| 2124 | } Field; ///< |
| 2125 | UINT32 Value; ///< |
| 2126 | } D18F2xD8_STRUCT; |
| 2127 | |
| 2128 | // **** D18F2xDC Register Definition **** |
| 2129 | // Address |
| 2130 | #define D18F2xDC_ADDRESS 0xdc |
| 2131 | |
| 2132 | // Type |
| 2133 | #define D18F2xDC_TYPE TYPE_D18F2 |
| 2134 | // Field Data |
| 2135 | #define D18F2xDC_HTMaskHigh_OFFSET 0 |
| 2136 | #define D18F2xDC_HTMaskHigh_WIDTH 32 |
| 2137 | #define D18F2xDC_HTMaskHigh_MASK 0xffffffff |
| 2138 | |
| 2139 | /// D18F2xDC |
| 2140 | typedef union { |
| 2141 | struct { ///< |
| 2142 | UINT32 HTMaskHigh:32; ///< |
| 2143 | } Field; ///< |
| 2144 | UINT32 Value; ///< |
| 2145 | } D18F2xDC_STRUCT; |
| 2146 | |
| 2147 | // **** D18F2xE0 Register Definition **** |
| 2148 | // Address |
| 2149 | #define D18F2xE0_ADDRESS 0xe0 |
| 2150 | |
| 2151 | // Type |
| 2152 | #define D18F2xE0_TYPE TYPE_D18F2 |
| 2153 | // Field Data |
| 2154 | #define D18F2xE0_HTCmdLow_OFFSET 0 |
| 2155 | #define D18F2xE0_HTCmdLow_WIDTH 32 |
| 2156 | #define D18F2xE0_HTCmdLow_MASK 0xffffffff |
| 2157 | |
| 2158 | /// D18F2xE0 |
| 2159 | typedef union { |
| 2160 | struct { ///< |
| 2161 | UINT32 HTCmdLow:32; ///< |
| 2162 | } Field; ///< |
| 2163 | UINT32 Value; ///< |
| 2164 | } D18F2xE0_STRUCT; |
| 2165 | |
| 2166 | // **** D18F2xE4 Register Definition **** |
| 2167 | // Address |
| 2168 | #define D18F2xE4_ADDRESS 0xe4 |
| 2169 | |
| 2170 | // Type |
| 2171 | #define D18F2xE4_TYPE TYPE_D18F2 |
| 2172 | // Field Data |
| 2173 | #define D18F2xE4_HTCmdHigh_OFFSET 0 |
| 2174 | #define D18F2xE4_HTCmdHigh_WIDTH 32 |
| 2175 | #define D18F2xE4_HTCmdHigh_MASK 0xffffffff |
| 2176 | |
| 2177 | /// D18F2xE4 |
| 2178 | typedef union { |
| 2179 | struct { ///< |
| 2180 | UINT32 HTCmdHigh:32; ///< |
| 2181 | } Field; ///< |
| 2182 | UINT32 Value; ///< |
| 2183 | } D18F2xE4_STRUCT; |
| 2184 | |
| 2185 | // **** D18F2xE8 Register Definition **** |
| 2186 | // Address |
| 2187 | #define D18F2xE8_ADDRESS 0xe8 |
| 2188 | |
| 2189 | // Type |
| 2190 | #define D18F2xE8_TYPE TYPE_D18F2 |
| 2191 | // Field Data |
| 2192 | #define D18F2xE8_HTMaskLow_OFFSET 0 |
| 2193 | #define D18F2xE8_HTMaskLow_WIDTH 32 |
| 2194 | #define D18F2xE8_HTMaskLow_MASK 0xffffffff |
| 2195 | |
| 2196 | /// D18F2xE8 |
| 2197 | typedef union { |
| 2198 | struct { ///< |
| 2199 | UINT32 HTMaskLow:32; ///< |
| 2200 | } Field; ///< |
| 2201 | UINT32 Value; ///< |
| 2202 | } D18F2xE8_STRUCT; |
| 2203 | |
| 2204 | // **** D18F2xEC Register Definition **** |
| 2205 | // Address |
| 2206 | #define D18F2xEC_ADDRESS 0xec |
| 2207 | |
| 2208 | // Type |
| 2209 | #define D18F2xEC_TYPE TYPE_D18F2 |
| 2210 | // Field Data |
| 2211 | #define D18F2xEC_HTMaskHigh_OFFSET 0 |
| 2212 | #define D18F2xEC_HTMaskHigh_WIDTH 32 |
| 2213 | #define D18F2xEC_HTMaskHigh_MASK 0xffffffff |
| 2214 | |
| 2215 | /// D18F2xEC |
| 2216 | typedef union { |
| 2217 | struct { ///< |
| 2218 | UINT32 HTMaskHigh:32; ///< |
| 2219 | } Field; ///< |
| 2220 | UINT32 Value; ///< |
| 2221 | } D18F2xEC_STRUCT; |
| 2222 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 2223 | // **** D18F2xF0 Register Definition **** |
| 2224 | // Address |
| 2225 | #define D18F2xF0_ADDRESS 0xf0 |
| 2226 | |
| 2227 | // Type |
| 2228 | #define D18F2xF0_TYPE TYPE_D18F2 |
| 2229 | // Field Data |
| 2230 | #define D18F2xF0_DctOffset_OFFSET 0 |
| 2231 | #define D18F2xF0_DctOffset_WIDTH 28 |
| 2232 | #define D18F2xF0_DctOffset_MASK 0xfffffff |
| 2233 | #define D18F2xF0_Reserved_29_28_OFFSET 28 |
| 2234 | #define D18F2xF0_Reserved_29_28_WIDTH 2 |
| 2235 | #define D18F2xF0_Reserved_29_28_MASK 0x30000000 |
| 2236 | #define D18F2xF0_DctAccessWrite_OFFSET 30 |
| 2237 | #define D18F2xF0_DctAccessWrite_WIDTH 1 |
| 2238 | #define D18F2xF0_DctAccessWrite_MASK 0x40000000 |
| 2239 | #define D18F2xF0_DctAccessDone_OFFSET 31 |
| 2240 | #define D18F2xF0_DctAccessDone_WIDTH 1 |
| 2241 | #define D18F2xF0_DctAccessDone_MASK 0x80000000 |
| 2242 | |
| 2243 | /// D18F2xF0 |
| 2244 | typedef union { |
| 2245 | struct { ///< |
| 2246 | UINT32 DctOffset:28; ///< |
| 2247 | UINT32 Reserved_29_28:2 ; ///< |
| 2248 | UINT32 DctAccessWrite:1 ; ///< |
| 2249 | UINT32 DctAccessDone:1 ; ///< |
| 2250 | } Field; ///< |
| 2251 | UINT32 Value; ///< |
| 2252 | } D18F2xF0_STRUCT; |
| 2253 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 2254 | // **** D18F2x184 Register Definition **** |
| 2255 | // Address |
| 2256 | #define D18F2x184_ADDRESS 0x184 |
| 2257 | |
| 2258 | // **** D18F2x18C Register Definition **** |
| 2259 | // Address |
| 2260 | #define D18F2x18C_ADDRESS 0x18c |
| 2261 | |
| 2262 | // **** D18F2x190 Register Definition **** |
| 2263 | // Address |
| 2264 | #define D18F2x190_ADDRESS 0x190 |
| 2265 | |
| 2266 | // **** D18F2x194 Register Definition **** |
| 2267 | // Address |
| 2268 | #define D18F2x194_ADDRESS 0x194 |
| 2269 | |
| 2270 | // **** D18F2x198 Register Definition **** |
| 2271 | // Address |
| 2272 | #define D18F2x198_ADDRESS 0x198 |
| 2273 | |
| 2274 | // **** D18F2x1F0 Register Definition **** |
| 2275 | // Address |
| 2276 | #define D18F2x1F0_ADDRESS 0x1f0 |
| 2277 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 2278 | // **** D18F2xF4 Register Definition **** |
| 2279 | // Address |
| 2280 | #define D18F2xF4_ADDRESS 0xf4 |
| 2281 | |
| 2282 | // Type |
| 2283 | #define D18F2xF4_TYPE TYPE_D18F2 |
| 2284 | // Field Data |
| 2285 | #define D18F2xF4_DctExtDataPort_OFFSET 0 |
| 2286 | #define D18F2xF4_DctExtDataPort_WIDTH 32 |
| 2287 | #define D18F2xF4_DctExtDataPort_MASK 0xffffffff |
| 2288 | |
| 2289 | /// D18F2xF4 |
| 2290 | typedef union { |
| 2291 | struct { ///< |
| 2292 | UINT32 DctExtDataPort:32; ///< |
| 2293 | } Field; ///< |
| 2294 | UINT32 Value; ///< |
| 2295 | } D18F2xF4_STRUCT; |
| 2296 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 2297 | // **** D18F2x0F4_x40 Register Definition **** |
| 2298 | // Address |
| 2299 | #define D18F2x0F4_x40_ADDRESS 0x40 |
| 2300 | |
| 2301 | // Type |
| 2302 | #define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 |
| 2303 | // Field Data |
| 2304 | #define D18F2x0F4_x40_Trcd_OFFSET 0 |
| 2305 | #define D18F2x0F4_x40_Trcd_WIDTH 4 |
| 2306 | #define D18F2x0F4_x40_Trcd_MASK 0xf |
| 2307 | #define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 |
| 2308 | #define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 |
| 2309 | #define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 |
| 2310 | #define D18F2x0F4_x40_Trp_OFFSET 8 |
| 2311 | #define D18F2x0F4_x40_Trp_WIDTH 4 |
| 2312 | #define D18F2x0F4_x40_Trp_MASK 0xf00 |
| 2313 | #define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 |
| 2314 | #define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 |
| 2315 | #define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 |
| 2316 | #define D18F2x0F4_x40_Tras_OFFSET 16 |
| 2317 | #define D18F2x0F4_x40_Tras_WIDTH 5 |
| 2318 | #define D18F2x0F4_x40_Tras_MASK 0x1f0000 |
| 2319 | #define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 |
| 2320 | #define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 |
| 2321 | #define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 |
| 2322 | #define D18F2x0F4_x40_Trc_OFFSET 24 |
| 2323 | #define D18F2x0F4_x40_Trc_WIDTH 6 |
| 2324 | #define D18F2x0F4_x40_Trc_MASK 0x3f000000 |
| 2325 | #define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 |
| 2326 | #define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 |
| 2327 | #define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 |
| 2328 | |
| 2329 | /// D18F2x0F4_x40 |
| 2330 | typedef union { |
| 2331 | struct { ///< |
| 2332 | UINT32 Trcd:4 ; ///< |
| 2333 | UINT32 Reserved_7_4:4 ; ///< |
| 2334 | UINT32 Trp:4 ; ///< |
| 2335 | UINT32 Reserved_15_12:4 ; ///< |
| 2336 | UINT32 Tras:5 ; ///< |
| 2337 | UINT32 Reserved_23_21:3 ; ///< |
| 2338 | UINT32 Trc:6 ; ///< |
| 2339 | UINT32 Reserved_31_30:2 ; ///< |
| 2340 | } Field; ///< |
| 2341 | UINT32 Value; ///< |
| 2342 | } D18F2x0F4_x40_STRUCT; |
| 2343 | |
| 2344 | // **** D18F2x0F4_x41 Register Definition **** |
| 2345 | // Address |
| 2346 | #define D18F2x0F4_x41_ADDRESS 0x41 |
| 2347 | |
| 2348 | // Type |
| 2349 | #define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 |
| 2350 | // Field Data |
| 2351 | #define D18F2x0F4_x41_Trtp_OFFSET 0 |
| 2352 | #define D18F2x0F4_x41_Trtp_WIDTH 3 |
| 2353 | #define D18F2x0F4_x41_Trtp_MASK 0x7 |
| 2354 | #define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 |
| 2355 | #define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 |
| 2356 | #define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 |
| 2357 | #define D18F2x0F4_x41_Trrd_OFFSET 8 |
| 2358 | #define D18F2x0F4_x41_Trrd_WIDTH 3 |
| 2359 | #define D18F2x0F4_x41_Trrd_MASK 0x700 |
| 2360 | #define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 |
| 2361 | #define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 |
| 2362 | #define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 |
| 2363 | #define D18F2x0F4_x41_Twtr_OFFSET 16 |
| 2364 | #define D18F2x0F4_x41_Twtr_WIDTH 3 |
| 2365 | #define D18F2x0F4_x41_Twtr_MASK 0x70000 |
| 2366 | #define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 |
| 2367 | #define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 |
| 2368 | #define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 |
| 2369 | |
| 2370 | /// D18F2x0F4_x41 |
| 2371 | typedef union { |
| 2372 | struct { ///< |
| 2373 | UINT32 Trtp:3 ; ///< |
| 2374 | UINT32 Reserved_7_3:5 ; ///< |
| 2375 | UINT32 Trrd:3 ; ///< |
| 2376 | UINT32 Reserved_15_11:5 ; ///< |
| 2377 | UINT32 Twtr:3 ; ///< |
| 2378 | UINT32 Reserved_31_19:13; ///< |
| 2379 | } Field; ///< |
| 2380 | UINT32 Value; ///< |
| 2381 | } D18F2x0F4_x41_STRUCT; |
| 2382 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 2383 | // **** D18F2x110 Register Definition **** |
| 2384 | // Address |
| 2385 | #define D18F2x110_ADDRESS 0x110 |
| 2386 | |
| 2387 | // Type |
| 2388 | #define D18F2x110_TYPE TYPE_D18F2 |
| 2389 | // Field Data |
| 2390 | #define D18F2x110_Reserved_2_0_OFFSET 0 |
| 2391 | #define D18F2x110_Reserved_2_0_WIDTH 3 |
| 2392 | #define D18F2x110_Reserved_2_0_MASK 0x7 |
| 2393 | #define D18F2x110_MemClrInit_OFFSET 3 |
| 2394 | #define D18F2x110_MemClrInit_WIDTH 1 |
| 2395 | #define D18F2x110_MemClrInit_MASK 0x8 |
| 2396 | #define D18F2x110_Reserved_7_4_OFFSET 4 |
| 2397 | #define D18F2x110_Reserved_7_4_WIDTH 4 |
| 2398 | #define D18F2x110_Reserved_7_4_MASK 0xf0 |
| 2399 | #define D18F2x110_DramEnable_OFFSET 8 |
| 2400 | #define D18F2x110_DramEnable_WIDTH 1 |
| 2401 | #define D18F2x110_DramEnable_MASK 0x100 |
| 2402 | #define D18F2x110_MemClrBusy_OFFSET 9 |
| 2403 | #define D18F2x110_MemClrBusy_WIDTH 1 |
| 2404 | #define D18F2x110_MemClrBusy_MASK 0x200 |
| 2405 | #define D18F2x110_MemCleared_OFFSET 10 |
| 2406 | #define D18F2x110_MemCleared_WIDTH 1 |
| 2407 | #define D18F2x110_MemCleared_MASK 0x400 |
| 2408 | #define D18F2x110_Reserved_31_11_OFFSET 11 |
| 2409 | #define D18F2x110_Reserved_31_11_WIDTH 21 |
| 2410 | #define D18F2x110_Reserved_31_11_MASK 0xfffff800 |
| 2411 | |
| 2412 | /// D18F2x110 |
| 2413 | typedef union { |
| 2414 | struct { ///< |
| 2415 | UINT32 Reserved_2_0:3 ; ///< |
| 2416 | UINT32 MemClrInit:1 ; ///< |
| 2417 | UINT32 Reserved_7_4:4 ; ///< |
| 2418 | UINT32 DramEnable:1 ; ///< |
| 2419 | UINT32 MemClrBusy:1 ; ///< |
| 2420 | UINT32 MemCleared:1 ; ///< |
| 2421 | UINT32 Reserved_31_11:21; ///< |
| 2422 | } Field; ///< |
| 2423 | UINT32 Value; ///< |
| 2424 | } D18F2x110_STRUCT; |
| 2425 | |
| 2426 | // **** D18F2x114 Register Definition **** |
| 2427 | // Address |
| 2428 | #define D18F2x114_ADDRESS 0x114 |
| 2429 | |
| 2430 | // Type |
| 2431 | #define D18F2x114_TYPE TYPE_D18F2 |
| 2432 | // Field Data |
| 2433 | #define D18F2x114_Reserved_8_0_OFFSET 0 |
| 2434 | #define D18F2x114_Reserved_8_0_WIDTH 9 |
| 2435 | #define D18F2x114_Reserved_8_0_MASK 0x1ff |
| 2436 | #define D18F2x114_DctSelBankSwap_OFFSET 9 |
| 2437 | #define D18F2x114_DctSelBankSwap_WIDTH 1 |
| 2438 | #define D18F2x114_DctSelBankSwap_MASK 0x200 |
| 2439 | #define D18F2x114_Reserved_31_10_OFFSET 10 |
| 2440 | #define D18F2x114_Reserved_31_10_WIDTH 22 |
| 2441 | #define D18F2x114_Reserved_31_10_MASK 0xfffffc00 |
| 2442 | |
| 2443 | /// D18F2x114 |
| 2444 | typedef union { |
| 2445 | struct { ///< |
| 2446 | UINT32 Reserved_8_0:9 ; ///< |
| 2447 | UINT32 DctSelBankSwap:1 ; ///< |
| 2448 | UINT32 Reserved_31_10:22; ///< |
| 2449 | } Field; ///< |
| 2450 | UINT32 Value; ///< |
| 2451 | } D18F2x114_STRUCT; |
| 2452 | |
| 2453 | // **** D18F3x64 Register Definition **** |
| 2454 | // Address |
| 2455 | #define D18F3x64_ADDRESS 0x64 |
| 2456 | |
| 2457 | // Type |
| 2458 | #define D18F3x64_TYPE TYPE_D18F3 |
| 2459 | // Field Data |
| 2460 | #define D18F3x64_HtcEn_OFFSET 0 |
| 2461 | #define D18F3x64_HtcEn_WIDTH 1 |
| 2462 | #define D18F3x64_HtcEn_MASK 0x1 |
| 2463 | #define D18F3x64_Reserved_3_1_OFFSET 1 |
| 2464 | #define D18F3x64_Reserved_3_1_WIDTH 3 |
| 2465 | #define D18F3x64_Reserved_3_1_MASK 0xe |
| 2466 | #define D18F3x64_HtcAct_OFFSET 4 |
| 2467 | #define D18F3x64_HtcAct_WIDTH 1 |
| 2468 | #define D18F3x64_HtcAct_MASK 0x10 |
| 2469 | #define D18F3x64_HtcActSts_OFFSET 5 |
| 2470 | #define D18F3x64_HtcActSts_WIDTH 1 |
| 2471 | #define D18F3x64_HtcActSts_MASK 0x20 |
| 2472 | #define D18F3x64_PslApicHiEn_OFFSET 6 |
| 2473 | #define D18F3x64_PslApicHiEn_WIDTH 1 |
| 2474 | #define D18F3x64_PslApicHiEn_MASK 0x40 |
| 2475 | #define D18F3x64_PslApicLoEn_OFFSET 7 |
| 2476 | #define D18F3x64_PslApicLoEn_WIDTH 1 |
| 2477 | #define D18F3x64_PslApicLoEn_MASK 0x80 |
| 2478 | #define D18F3x64_Reserved_15_8_OFFSET 8 |
| 2479 | #define D18F3x64_Reserved_15_8_WIDTH 8 |
| 2480 | #define D18F3x64_Reserved_15_8_MASK 0xff00 |
| 2481 | #define D18F3x64_HtcTmpLmt_OFFSET 16 |
| 2482 | #define D18F3x64_HtcTmpLmt_WIDTH 7 |
| 2483 | #define D18F3x64_HtcTmpLmt_MASK 0x7f0000 |
| 2484 | #define D18F3x64_HtcSlewSel_OFFSET 23 |
| 2485 | #define D18F3x64_HtcSlewSel_WIDTH 1 |
| 2486 | #define D18F3x64_HtcSlewSel_MASK 0x800000 |
| 2487 | #define D18F3x64_HtcHystLmt_OFFSET 24 |
| 2488 | #define D18F3x64_HtcHystLmt_WIDTH 4 |
| 2489 | #define D18F3x64_HtcHystLmt_MASK 0xf000000 |
| 2490 | #define D18F3x64_HtcPstateLimit_OFFSET 28 |
| 2491 | #define D18F3x64_HtcPstateLimit_WIDTH 3 |
| 2492 | #define D18F3x64_HtcPstateLimit_MASK 0x70000000 |
| 2493 | #define D18F3x64_HtcLock_OFFSET 31 |
| 2494 | #define D18F3x64_HtcLock_WIDTH 1 |
| 2495 | #define D18F3x64_HtcLock_MASK 0x80000000 |
| 2496 | |
| 2497 | /// D18F3x64 |
| 2498 | typedef union { |
| 2499 | struct { ///< |
| 2500 | UINT32 HtcEn:1 ; ///< |
| 2501 | UINT32 Reserved_3_1:3 ; ///< |
| 2502 | UINT32 HtcAct:1 ; ///< |
| 2503 | UINT32 HtcActSts:1 ; ///< |
| 2504 | UINT32 PslApicHiEn:1 ; ///< |
| 2505 | UINT32 PslApicLoEn:1 ; ///< |
| 2506 | UINT32 Reserved_15_8:8 ; ///< |
| 2507 | UINT32 HtcTmpLmt:7 ; ///< |
| 2508 | UINT32 HtcSlewSel:1 ; ///< |
| 2509 | UINT32 HtcHystLmt:4 ; ///< |
| 2510 | UINT32 HtcPstateLimit:3 ; ///< |
| 2511 | UINT32 HtcLock:1 ; ///< |
| 2512 | } Field; ///< |
| 2513 | UINT32 Value; ///< |
| 2514 | } D18F3x64_STRUCT; |
| 2515 | |
| 2516 | // **** D18F3x6C Register Definition **** |
| 2517 | // Address |
| 2518 | #define D18F3x6C_ADDRESS 0x6c |
| 2519 | |
| 2520 | // Type |
| 2521 | #define D18F3x6C_TYPE TYPE_D18F3 |
| 2522 | // Field Data |
| 2523 | #define D18F3x6C_UpLoPreqDBC_OFFSET 0 |
| 2524 | #define D18F3x6C_UpLoPreqDBC_WIDTH 4 |
| 2525 | #define D18F3x6C_UpLoPreqDBC_MASK 0xf |
| 2526 | #define D18F3x6C_UpLoNpreqDBC_OFFSET 4 |
| 2527 | #define D18F3x6C_UpLoNpreqDBC_WIDTH 4 |
| 2528 | #define D18F3x6C_UpLoNpreqDBC_MASK 0xf0 |
| 2529 | #define D18F3x6C_UpLoRespDBC_OFFSET 8 |
| 2530 | #define D18F3x6C_UpLoRespDBC_WIDTH 4 |
| 2531 | #define D18F3x6C_UpLoRespDBC_MASK 0xf00 |
| 2532 | #define D18F3x6C_Reserved_15_12_OFFSET 12 |
| 2533 | #define D18F3x6C_Reserved_15_12_WIDTH 4 |
| 2534 | #define D18F3x6C_Reserved_15_12_MASK 0xf000 |
| 2535 | #define D18F3x6C_UpHiPreqDBC_OFFSET 16 |
| 2536 | #define D18F3x6C_UpHiPreqDBC_WIDTH 4 |
| 2537 | #define D18F3x6C_UpHiPreqDBC_MASK 0xf0000 |
| 2538 | #define D18F3x6C_UpHiNpreqDBC_OFFSET 20 |
| 2539 | #define D18F3x6C_UpHiNpreqDBC_WIDTH 4 |
| 2540 | #define D18F3x6C_UpHiNpreqDBC_MASK 0xf00000 |
| 2541 | #define D18F3x6C_Reserved_31_24_OFFSET 24 |
| 2542 | #define D18F3x6C_Reserved_31_24_WIDTH 8 |
| 2543 | #define D18F3x6C_Reserved_31_24_MASK 0xff000000 |
| 2544 | |
| 2545 | /// D18F3x6C |
| 2546 | typedef union { |
| 2547 | struct { ///< |
| 2548 | UINT32 UpLoPreqDBC:4 ; ///< |
| 2549 | UINT32 UpLoNpreqDBC:4 ; ///< |
| 2550 | UINT32 UpLoRespDBC:4 ; ///< |
| 2551 | UINT32 Reserved_15_12:4 ; ///< |
| 2552 | UINT32 UpHiPreqDBC:4 ; ///< |
| 2553 | UINT32 UpHiNpreqDBC:4 ; ///< |
| 2554 | UINT32 Reserved_31_24:8 ; ///< |
| 2555 | } Field; ///< |
| 2556 | UINT32 Value; ///< |
| 2557 | } D18F3x6C_STRUCT; |
| 2558 | |
| 2559 | // **** D18F3x74 Register Definition **** |
| 2560 | // Address |
| 2561 | #define D18F3x74_ADDRESS 0x74 |
| 2562 | |
| 2563 | // Type |
| 2564 | #define D18F3x74_TYPE TYPE_D18F3 |
| 2565 | // Field Data |
| 2566 | #define D18F3x74_UpLoPreqCBC_OFFSET 0 |
| 2567 | #define D18F3x74_UpLoPreqCBC_WIDTH 4 |
| 2568 | #define D18F3x74_UpLoPreqCBC_MASK 0xf |
| 2569 | #define D18F3x74_UpLoNpreqCBC_OFFSET 4 |
| 2570 | #define D18F3x74_UpLoNpreqCBC_WIDTH 4 |
| 2571 | #define D18F3x74_UpLoNpreqCBC_MASK 0xf0 |
| 2572 | #define D18F3x74_UpLoRespCBC_OFFSET 8 |
| 2573 | #define D18F3x74_UpLoRespCBC_WIDTH 4 |
| 2574 | #define D18F3x74_UpLoRespCBC_MASK 0xf00 |
| 2575 | #define D18F3x74_Reserved_15_12_OFFSET 12 |
| 2576 | #define D18F3x74_Reserved_15_12_WIDTH 4 |
| 2577 | #define D18F3x74_Reserved_15_12_MASK 0xf000 |
| 2578 | #define D18F3x74_UpHiPreqCBC_OFFSET 16 |
| 2579 | #define D18F3x74_UpHiPreqCBC_WIDTH 4 |
| 2580 | #define D18F3x74_UpHiPreqCBC_MASK 0xf0000 |
| 2581 | #define D18F3x74_UpHiNpreqCBC_OFFSET 20 |
| 2582 | #define D18F3x74_UpHiNpreqCBC_WIDTH 4 |
| 2583 | #define D18F3x74_UpHiNpreqCBC_MASK 0xf00000 |
| 2584 | #define D18F3x74_Reserved_31_24_OFFSET 24 |
| 2585 | #define D18F3x74_Reserved_31_24_WIDTH 8 |
| 2586 | #define D18F3x74_Reserved_31_24_MASK 0xff000000 |
| 2587 | |
| 2588 | /// D18F3x74 |
| 2589 | typedef union { |
| 2590 | struct { ///< |
| 2591 | UINT32 UpLoPreqCBC:4 ; ///< |
| 2592 | UINT32 UpLoNpreqCBC:4 ; ///< |
| 2593 | UINT32 UpLoRespCBC:4 ; ///< |
| 2594 | UINT32 Reserved_15_12:4 ; ///< |
| 2595 | UINT32 UpHiPreqCBC:4 ; ///< |
| 2596 | UINT32 UpHiNpreqCBC:4 ; ///< |
| 2597 | UINT32 Reserved_31_24:8 ; ///< |
| 2598 | } Field; ///< |
| 2599 | UINT32 Value; ///< |
| 2600 | } D18F3x74_STRUCT; |
| 2601 | |
| 2602 | // **** D18F3x7C Register Definition **** |
| 2603 | // Address |
| 2604 | #define D18F3x7C_ADDRESS 0x7c |
| 2605 | |
| 2606 | // Type |
| 2607 | #define D18F3x7C_TYPE TYPE_D18F3 |
| 2608 | // Field Data |
| 2609 | #define D18F3x7C_CpuBC_OFFSET 0 |
| 2610 | #define D18F3x7C_CpuBC_WIDTH 6 |
| 2611 | #define D18F3x7C_CpuBC_MASK 0x3f |
| 2612 | #define D18F3x7C_Reserved_7_6_OFFSET 6 |
| 2613 | #define D18F3x7C_Reserved_7_6_WIDTH 2 |
| 2614 | #define D18F3x7C_Reserved_7_6_MASK 0xc0 |
| 2615 | #define D18F3x7C_LoPriPBC_OFFSET 8 |
| 2616 | #define D18F3x7C_LoPriPBC_WIDTH 6 |
| 2617 | #define D18F3x7C_LoPriPBC_MASK 0x3f00 |
| 2618 | #define D18F3x7C_Reserved_15_14_OFFSET 14 |
| 2619 | #define D18F3x7C_Reserved_15_14_WIDTH 2 |
| 2620 | #define D18F3x7C_Reserved_15_14_MASK 0xc000 |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 2621 | #define D18F3x7C_LoPriNpBC_OFFSET 16 |
| 2622 | #define D18F3x7C_LoPriNpBC_WIDTH 6 |
| 2623 | #define D18F3x7C_LoPriNpBC_MASK 0x3f0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 2624 | #define D18F3x7C_Reserved_23_22_OFFSET 22 |
| 2625 | #define D18F3x7C_Reserved_23_22_WIDTH 2 |
| 2626 | #define D18F3x7C_Reserved_23_22_MASK 0xc00000 |
| 2627 | #define D18F3x7C_FreePoolBC_OFFSET 24 |
| 2628 | #define D18F3x7C_FreePoolBC_WIDTH 6 |
| 2629 | #define D18F3x7C_FreePoolBC_MASK 0x3f000000 |
| 2630 | #define D18F3x7C_Reserved_31_30_OFFSET 30 |
| 2631 | #define D18F3x7C_Reserved_31_30_WIDTH 2 |
| 2632 | #define D18F3x7C_Reserved_31_30_MASK 0xc0000000 |
| 2633 | |
| 2634 | /// D18F3x7C |
| 2635 | typedef union { |
| 2636 | struct { ///< |
| 2637 | UINT32 CpuBC:6 ; ///< |
| 2638 | UINT32 Reserved_7_6:2 ; ///< |
| 2639 | UINT32 LoPriPBC:6 ; ///< |
| 2640 | UINT32 Reserved_15_14:2 ; ///< |
| 2641 | UINT32 LoPriNPBC:6 ; ///< |
| 2642 | UINT32 Reserved_23_22:2 ; ///< |
| 2643 | UINT32 FreePoolBC:6 ; ///< |
| 2644 | UINT32 Reserved_31_30:2 ; ///< |
| 2645 | } Field; ///< |
| 2646 | UINT32 Value; ///< |
| 2647 | } D18F3x7C_STRUCT; |
| 2648 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 2649 | // **** D18F3xD4 Register Definition **** |
| 2650 | // Address |
| 2651 | #define D18F3xD4_ADDRESS 0xd4 |
| 2652 | |
| 2653 | // Type |
| 2654 | #define D18F3xD4_TYPE TYPE_D18F3 |
| 2655 | // Field Data |
| 2656 | #define D18F3xD4_MainPllOpFreqId_OFFSET 0 |
| 2657 | #define D18F3xD4_MainPllOpFreqId_WIDTH 6 |
| 2658 | #define D18F3xD4_MainPllOpFreqId_MASK 0x3f |
| 2659 | #define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6 |
| 2660 | #define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1 |
| 2661 | #define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40 |
| 2662 | #define D18F3xD4_Reserved_7_7_OFFSET 7 |
| 2663 | #define D18F3xD4_Reserved_7_7_WIDTH 1 |
| 2664 | #define D18F3xD4_Reserved_7_7_MASK 0x80 |
| 2665 | #define D18F3xD4_ClkRampHystSel_OFFSET 8 |
| 2666 | #define D18F3xD4_ClkRampHystSel_WIDTH 4 |
| 2667 | #define D18F3xD4_ClkRampHystSel_MASK 0xf00 |
| 2668 | #define D18F3xD4_NbOutHyst_OFFSET 12 |
| 2669 | #define D18F3xD4_NbOutHyst_WIDTH 4 |
| 2670 | #define D18F3xD4_NbOutHyst_MASK 0xf000 |
| 2671 | #define D18F3xD4_DisNclkGatingIdle_OFFSET 16 |
| 2672 | #define D18F3xD4_DisNclkGatingIdle_WIDTH 1 |
| 2673 | #define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 |
| 2674 | #define D18F3xD4_ClockGatingEnDram_OFFSET 17 |
| 2675 | #define D18F3xD4_ClockGatingEnDram_WIDTH 1 |
| 2676 | #define D18F3xD4_ClockGatingEnDram_MASK 0x20000 |
| 2677 | #define D18F3xD4_Reserved_18_18_OFFSET 18 |
| 2678 | #define D18F3xD4_Reserved_18_18_WIDTH 1 |
| 2679 | #define D18F3xD4_Reserved_18_18_MASK 0x40000 |
| 2680 | #define D18F3xD4_Reserved_31_19_OFFSET 19 |
| 2681 | #define D18F3xD4_Reserved_31_19_WIDTH 13 |
| 2682 | #define D18F3xD4_Reserved_31_19_MASK 0xfff80000 |
| 2683 | |
| 2684 | /// D18F3xD4 |
| 2685 | typedef union { |
| 2686 | struct { ///< |
| 2687 | UINT32 MainPllOpFreqId:6 ; ///< |
| 2688 | UINT32 MainPllOpFreqIdEn:1 ; ///< |
| 2689 | UINT32 Reserved_7_7:1 ; ///< |
| 2690 | UINT32 ClkRampHystSel:4 ; ///< |
| 2691 | UINT32 NbOutHyst:4 ; ///< |
| 2692 | UINT32 DisNclkGatingIdle:1 ; ///< |
| 2693 | UINT32 ClockGatingEnDram:1 ; ///< |
| 2694 | UINT32 Reserved_18_18:1 ; ///< |
| 2695 | UINT32 Reserved_31_19:13; ///< |
| 2696 | } Field; ///< |
| 2697 | UINT32 Value; ///< |
| 2698 | } D18F3xD4_STRUCT; |
| 2699 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 2700 | // **** D18F3xD8 Register Definition **** |
| 2701 | // Address |
| 2702 | #define D18F3xD8_ADDRESS 0xd8 |
| 2703 | |
| 2704 | // Type |
| 2705 | #define D18F3xD8_TYPE TYPE_D18F3 |
| 2706 | // Field Data |
| 2707 | #define D18F3xD8_Reserved_3_0_OFFSET 0 |
| 2708 | #define D18F3xD8_Reserved_3_0_WIDTH 4 |
| 2709 | #define D18F3xD8_Reserved_3_0_MASK 0xf |
| 2710 | #define D18F3xD8_VSRampSlamTime_OFFSET 4 |
| 2711 | #define D18F3xD8_VSRampSlamTime_WIDTH 3 |
| 2712 | #define D18F3xD8_VSRampSlamTime_MASK 0x70 |
| 2713 | #define D18F3xD8_ExtndTriDly_OFFSET 7 |
| 2714 | #define D18F3xD8_ExtndTriDly_WIDTH 5 |
| 2715 | #define D18F3xD8_ExtndTriDly_MASK 0xf80 |
| 2716 | #define D18F3xD8_Reserved_31_12_OFFSET 12 |
| 2717 | #define D18F3xD8_Reserved_31_12_WIDTH 20 |
| 2718 | #define D18F3xD8_Reserved_31_12_MASK 0xfffff000 |
| 2719 | |
| 2720 | /// D18F3xD8 |
| 2721 | typedef union { |
| 2722 | struct { ///< |
| 2723 | UINT32 Reserved_3_0:4 ; ///< |
| 2724 | UINT32 VSRampSlamTime:3 ; ///< |
| 2725 | UINT32 ExtndTriDly:5 ; ///< |
| 2726 | UINT32 Reserved_31_12:20; ///< |
| 2727 | } Field; ///< |
| 2728 | UINT32 Value; ///< |
| 2729 | } D18F3xD8_STRUCT; |
| 2730 | |
| 2731 | // **** D18F3xDC Register Definition **** |
| 2732 | // Address |
| 2733 | #define D18F3xDC_ADDRESS 0xdc |
| 2734 | |
| 2735 | // Type |
| 2736 | #define D18F3xDC_TYPE TYPE_D18F3 |
| 2737 | // Field Data |
| 2738 | #define D18F3xDC_Reserved_7_0_OFFSET 0 |
| 2739 | #define D18F3xDC_Reserved_7_0_WIDTH 8 |
| 2740 | #define D18F3xDC_Reserved_7_0_MASK 0xff |
| 2741 | #define D18F3xDC_PstateMaxVal_OFFSET 8 |
| 2742 | #define D18F3xDC_PstateMaxVal_WIDTH 3 |
| 2743 | #define D18F3xDC_PstateMaxVal_MASK 0x700 |
| 2744 | #define D18F3xDC_Reserved_11_11_OFFSET 11 |
| 2745 | #define D18F3xDC_Reserved_11_11_WIDTH 1 |
| 2746 | #define D18F3xDC_Reserved_11_11_MASK 0x800 |
| 2747 | #define D18F3xDC_NbPs0Vid_OFFSET 12 |
| 2748 | #define D18F3xDC_NbPs0Vid_WIDTH 7 |
| 2749 | #define D18F3xDC_NbPs0Vid_MASK 0x7f000 |
| 2750 | #define D18F3xDC_NclkFreqDone_OFFSET 19 |
| 2751 | #define D18F3xDC_NclkFreqDone_WIDTH 1 |
| 2752 | #define D18F3xDC_NclkFreqDone_MASK 0x80000 |
| 2753 | #define D18F3xDC_NbPs0NclkDiv_OFFSET 20 |
| 2754 | #define D18F3xDC_NbPs0NclkDiv_WIDTH 7 |
| 2755 | #define D18F3xDC_NbPs0NclkDiv_MASK 0x7f00000 |
| 2756 | #define D18F3xDC_NbClockGateHyst_OFFSET 27 |
| 2757 | #define D18F3xDC_NbClockGateHyst_WIDTH 3 |
| 2758 | #define D18F3xDC_NbClockGateHyst_MASK 0x38000000 |
| 2759 | #define D18F3xDC_NbClockGateEn_OFFSET 30 |
| 2760 | #define D18F3xDC_NbClockGateEn_WIDTH 1 |
| 2761 | #define D18F3xDC_NbClockGateEn_MASK 0x40000000 |
| 2762 | #define D18F3xDC_CnbCifClockGateEn_OFFSET 31 |
| 2763 | #define D18F3xDC_CnbCifClockGateEn_WIDTH 1 |
| 2764 | #define D18F3xDC_CnbCifClockGateEn_MASK 0x80000000 |
| 2765 | |
| 2766 | /// D18F3xDC |
| 2767 | typedef union { |
| 2768 | struct { ///< |
| 2769 | UINT32 Reserved_7_0:8 ; ///< |
| 2770 | UINT32 PstateMaxVal:3 ; ///< |
| 2771 | UINT32 Reserved_11_11:1 ; ///< |
| 2772 | UINT32 NbPs0Vid:7 ; ///< |
| 2773 | UINT32 NclkFreqDone:1 ; ///< |
| 2774 | UINT32 NbPs0NclkDiv:7 ; ///< |
| 2775 | UINT32 NbClockGateHyst:3 ; ///< |
| 2776 | UINT32 NbClockGateEn:1 ; ///< |
| 2777 | UINT32 CnbCifClockGateEn:1 ; ///< |
| 2778 | } Field; ///< |
| 2779 | UINT32 Value; ///< |
| 2780 | } D18F3xDC_STRUCT; |
| 2781 | |
| 2782 | // **** D18F3x15C Register Definition **** |
| 2783 | // Address |
| 2784 | #define D18F3x15C_ADDRESS 0x15c |
| 2785 | |
| 2786 | // Type |
| 2787 | #define D18F3x15C_TYPE TYPE_D18F3 |
| 2788 | // Field Data |
| 2789 | #define D18F3x15C_SclkVidLevel0_OFFSET 0 |
| 2790 | #define D18F3x15C_SclkVidLevel0_WIDTH 7 |
| 2791 | #define D18F3x15C_SclkVidLevel0_MASK 0x7f |
| 2792 | #define D18F3x15C_Reserved_7_7_OFFSET 7 |
| 2793 | #define D18F3x15C_Reserved_7_7_WIDTH 1 |
| 2794 | #define D18F3x15C_Reserved_7_7_MASK 0x80 |
| 2795 | #define D18F3x15C_SclkVidLevel1_OFFSET 8 |
| 2796 | #define D18F3x15C_SclkVidLevel1_WIDTH 7 |
| 2797 | #define D18F3x15C_SclkVidLevel1_MASK 0x7f00 |
| 2798 | #define D18F3x15C_Reserved_15_15_OFFSET 15 |
| 2799 | #define D18F3x15C_Reserved_15_15_WIDTH 1 |
| 2800 | #define D18F3x15C_Reserved_15_15_MASK 0x8000 |
| 2801 | #define D18F3x15C_SclkVidLevel2_OFFSET 16 |
| 2802 | #define D18F3x15C_SclkVidLevel2_WIDTH 7 |
| 2803 | #define D18F3x15C_SclkVidLevel2_MASK 0x7f0000 |
| 2804 | #define D18F3x15C_Reserved_23_23_OFFSET 23 |
| 2805 | #define D18F3x15C_Reserved_23_23_WIDTH 1 |
| 2806 | #define D18F3x15C_Reserved_23_23_MASK 0x800000 |
| 2807 | #define D18F3x15C_SclkVidLevel3_OFFSET 24 |
| 2808 | #define D18F3x15C_SclkVidLevel3_WIDTH 7 |
| 2809 | #define D18F3x15C_SclkVidLevel3_MASK 0x7f000000 |
| 2810 | #define D18F3x15C_Reserved_31_31_OFFSET 31 |
| 2811 | #define D18F3x15C_Reserved_31_31_WIDTH 1 |
| 2812 | #define D18F3x15C_Reserved_31_31_MASK 0x80000000 |
| 2813 | |
| 2814 | /// D18F3x15C |
| 2815 | typedef union { |
| 2816 | struct { ///< |
| 2817 | UINT32 SclkVidLevel0:7 ; ///< |
| 2818 | UINT32 Reserved_7_7:1 ; ///< |
| 2819 | UINT32 SclkVidLevel1:7 ; ///< |
| 2820 | UINT32 Reserved_15_15:1 ; ///< |
| 2821 | UINT32 SclkVidLevel2:7 ; ///< |
| 2822 | UINT32 Reserved_23_23:1 ; ///< |
| 2823 | UINT32 SclkVidLevel3:7 ; ///< |
| 2824 | UINT32 Reserved_31_31:1 ; ///< |
| 2825 | } Field; ///< |
| 2826 | UINT32 Value; ///< |
| 2827 | } D18F3x15C_STRUCT; |
| 2828 | |
| 2829 | // **** D18F3x17C Register Definition **** |
| 2830 | // Address |
| 2831 | #define D18F3x17C_ADDRESS 0x17c |
| 2832 | |
| 2833 | // Type |
| 2834 | #define D18F3x17C_TYPE TYPE_D18F3 |
| 2835 | // Field Data |
| 2836 | #define D18F3x17C_HiPriPBC_OFFSET 0 |
| 2837 | #define D18F3x17C_HiPriPBC_WIDTH 6 |
| 2838 | #define D18F3x17C_HiPriPBC_MASK 0x3f |
| 2839 | #define D18F3x17C_Reserved_7_6_OFFSET 6 |
| 2840 | #define D18F3x17C_Reserved_7_6_WIDTH 2 |
| 2841 | #define D18F3x17C_Reserved_7_6_MASK 0xc0 |
| 2842 | #define D18F3x17C_HiPriNPBC_OFFSET 8 |
| 2843 | #define D18F3x17C_HiPriNPBC_WIDTH 6 |
| 2844 | #define D18F3x17C_HiPriNPBC_MASK 0x3f00 |
| 2845 | #define D18F3x17C_Reserved_31_14_OFFSET 14 |
| 2846 | #define D18F3x17C_Reserved_31_14_WIDTH 18 |
| 2847 | #define D18F3x17C_Reserved_31_14_MASK 0xffffc000 |
| 2848 | |
| 2849 | /// D18F3x17C |
| 2850 | typedef union { |
| 2851 | struct { ///< |
| 2852 | UINT32 HiPriPBC:6 ; ///< |
| 2853 | UINT32 Reserved_7_6:2 ; ///< |
| 2854 | UINT32 HiPriNPBC:6 ; ///< |
| 2855 | UINT32 Reserved_31_14:18; ///< |
| 2856 | } Field; ///< |
| 2857 | UINT32 Value; ///< |
| 2858 | } D18F3x17C_STRUCT; |
| 2859 | |
| 2860 | // **** D18F4x12C Register Definition **** |
| 2861 | // Address |
| 2862 | #define D18F4x12C_ADDRESS 0x12c |
| 2863 | |
| 2864 | // Type |
| 2865 | #define D18F4x12C_TYPE TYPE_D18F4 |
| 2866 | // Field Data |
| 2867 | #define D18F4x12C_C6Base_35_24__OFFSET 0 |
| 2868 | #define D18F4x12C_C6Base_35_24__WIDTH 12 |
| 2869 | #define D18F4x12C_C6Base_35_24__MASK 0xfff |
| 2870 | #define D18F4x12C_Reserved_31_12_OFFSET 12 |
| 2871 | #define D18F4x12C_Reserved_31_12_WIDTH 20 |
| 2872 | #define D18F4x12C_Reserved_31_12_MASK 0xfffff000 |
| 2873 | |
| 2874 | /// D18F4x12C |
| 2875 | typedef union { |
| 2876 | struct { ///< |
| 2877 | UINT32 C6Base_35_24_:12; ///< |
| 2878 | UINT32 Reserved_31_12:20; ///< |
| 2879 | } Field; ///< |
| 2880 | UINT32 Value; ///< |
| 2881 | } D18F4x12C_STRUCT; |
| 2882 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 2883 | // **** D18F4x15C Register Definition **** |
| 2884 | // Address |
| 2885 | #define D18F4x15C_ADDRESS 0x15c |
| 2886 | |
| 2887 | // Type |
| 2888 | #define D18F4x15C_TYPE TYPE_D18F4 |
| 2889 | // Field Data |
| 2890 | #define D18F4x15C_BoostSrc_OFFSET 0 |
| 2891 | #define D18F4x15C_BoostSrc_WIDTH 2 |
| 2892 | #define D18F4x15C_BoostSrc_MASK 0x3 |
| 2893 | #define D18F4x15C_NumBoostStates_OFFSET 2 |
| 2894 | #define D18F4x15C_NumBoostStates_WIDTH 3 |
| 2895 | #define D18F4x15C_NumBoostStates_MASK 0x1c |
| 2896 | #define D18F4x15C_Reserved_28_5_OFFSET 5 |
| 2897 | #define D18F4x15C_Reserved_28_5_WIDTH 24 |
| 2898 | #define D18F4x15C_Reserved_28_5_MASK 0x1fffffe0 |
| 2899 | #define D18F4x15C_BoostEnAllCores_OFFSET 29 |
| 2900 | #define D18F4x15C_BoostEnAllCores_WIDTH 1 |
| 2901 | #define D18F4x15C_BoostEnAllCores_MASK 0x20000000 |
| 2902 | #define D18F4x15C_Reserved_31_30_OFFSET 30 |
| 2903 | #define D18F4x15C_Reserved_31_30_WIDTH 2 |
| 2904 | #define D18F4x15C_Reserved_31_30_MASK 0xc0000000 |
| 2905 | |
| 2906 | /// D18F4x15C |
| 2907 | typedef union { |
| 2908 | struct { ///< |
| 2909 | UINT32 BoostSrc:2 ; ///< |
| 2910 | UINT32 NumBoostStates:3 ; ///< |
| 2911 | UINT32 Reserved_28_5:24; ///< |
| 2912 | UINT32 BoostEnAllCores:1 ; ///< |
| 2913 | UINT32 Reserved_31_30:2 ; ///< |
| 2914 | } Field; ///< |
| 2915 | UINT32 Value; ///< |
| 2916 | } D18F4x15C_STRUCT; |
| 2917 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 2918 | // **** D18F4x164 Register Definition **** |
| 2919 | // Address |
| 2920 | #define D18F4x164_ADDRESS 0x164 |
| 2921 | |
| 2922 | // Type |
| 2923 | #define D18F4x164_TYPE TYPE_D18F4 |
| 2924 | // Field Data |
| 2925 | #define D18F4x164_FixedErrata_OFFSET 0 |
| 2926 | #define D18F4x164_FixedErrata_WIDTH 32 |
| 2927 | #define D18F4x164_FixedErrata_MASK 0xffffffff |
| 2928 | |
| 2929 | /// D18F4x164 |
| 2930 | typedef union { |
| 2931 | struct { ///< |
| 2932 | UINT32 FixedErrata:32; ///< |
| 2933 | } Field; ///< |
| 2934 | UINT32 Value; ///< |
| 2935 | } D18F4x164_STRUCT; |
| 2936 | |
| 2937 | // **** D18F6x90 Register Definition **** |
| 2938 | // Address |
| 2939 | #define D18F6x90_ADDRESS 0x90 |
| 2940 | |
| 2941 | // Type |
| 2942 | #define D18F6x90_TYPE TYPE_D18F6 |
| 2943 | // Field Data |
| 2944 | #define D18F6x90_NbPs1NclkDiv_OFFSET 0 |
| 2945 | #define D18F6x90_NbPs1NclkDiv_WIDTH 7 |
| 2946 | #define D18F6x90_NbPs1NclkDiv_MASK 0x7f |
| 2947 | #define D18F6x90_Reserved_7_7_OFFSET 7 |
| 2948 | #define D18F6x90_Reserved_7_7_WIDTH 1 |
| 2949 | #define D18F6x90_Reserved_7_7_MASK 0x80 |
| 2950 | #define D18F6x90_NbPs1Vid_OFFSET 8 |
| 2951 | #define D18F6x90_NbPs1Vid_WIDTH 7 |
| 2952 | #define D18F6x90_NbPs1Vid_MASK 0x7f00 |
| 2953 | #define D18F6x90_Reserved_15_15_OFFSET 15 |
| 2954 | #define D18F6x90_Reserved_15_15_WIDTH 1 |
| 2955 | #define D18F6x90_Reserved_15_15_MASK 0x8000 |
| 2956 | #define D18F6x90_NbPs1GnbSlowIgn_OFFSET 16 |
| 2957 | #define D18F6x90_NbPs1GnbSlowIgn_WIDTH 1 |
| 2958 | #define D18F6x90_NbPs1GnbSlowIgn_MASK 0x10000 |
| 2959 | #define D18F6x90_Reserved_19_17_OFFSET 17 |
| 2960 | #define D18F6x90_Reserved_19_17_WIDTH 3 |
| 2961 | #define D18F6x90_Reserved_19_17_MASK 0xe0000 |
| 2962 | #define D18F6x90_NbPsLock_OFFSET 20 |
| 2963 | #define D18F6x90_NbPsLock_WIDTH 1 |
| 2964 | #define D18F6x90_NbPsLock_MASK 0x100000 |
| 2965 | #define D18F6x90_Reserved_27_21_OFFSET 21 |
| 2966 | #define D18F6x90_Reserved_27_21_WIDTH 7 |
| 2967 | #define D18F6x90_Reserved_27_21_MASK 0xfe00000 |
| 2968 | #define D18F6x90_NbPsForceReq_OFFSET 28 |
| 2969 | #define D18F6x90_NbPsForceReq_WIDTH 1 |
| 2970 | #define D18F6x90_NbPsForceReq_MASK 0x10000000 |
| 2971 | #define D18F6x90_NbPsForceSel_OFFSET 29 |
| 2972 | #define D18F6x90_NbPsForceSel_WIDTH 1 |
| 2973 | #define D18F6x90_NbPsForceSel_MASK 0x20000000 |
| 2974 | #define D18F6x90_NbPsCtrlDis_OFFSET 30 |
| 2975 | #define D18F6x90_NbPsCtrlDis_WIDTH 1 |
| 2976 | #define D18F6x90_NbPsCtrlDis_MASK 0x40000000 |
| 2977 | #define D18F6x90_NbPsCap_OFFSET 31 |
| 2978 | #define D18F6x90_NbPsCap_WIDTH 1 |
| 2979 | #define D18F6x90_NbPsCap_MASK 0x80000000 |
| 2980 | |
| 2981 | /// D18F6x90 |
| 2982 | typedef union { |
| 2983 | struct { ///< |
| 2984 | UINT32 NbPs1NclkDiv:7 ; ///< |
| 2985 | UINT32 Reserved_7_7:1 ; ///< |
| 2986 | UINT32 NbPs1Vid:7 ; ///< |
| 2987 | UINT32 Reserved_15_15:1 ; ///< |
| 2988 | UINT32 NbPs1GnbSlowIgn:1 ; ///< |
| 2989 | UINT32 Reserved_19_17:3 ; ///< |
| 2990 | UINT32 NbPsLock:1 ; ///< |
| 2991 | UINT32 Reserved_27_21:7 ; ///< |
| 2992 | UINT32 NbPsForceReq:1 ; ///< |
| 2993 | UINT32 NbPsForceSel:1 ; ///< |
| 2994 | UINT32 NbPsCtrlDis:1 ; ///< |
| 2995 | UINT32 NbPsCap:1 ; ///< |
| 2996 | } Field; ///< |
| 2997 | UINT32 Value; ///< |
| 2998 | } D18F6x90_STRUCT; |
| 2999 | |
| 3000 | // **** D18F6x94 Register Definition **** |
| 3001 | // Address |
| 3002 | #define D18F6x94_ADDRESS 0x94 |
| 3003 | |
| 3004 | // Type |
| 3005 | #define D18F6x94_TYPE TYPE_D18F6 |
| 3006 | // Field Data |
| 3007 | #define D18F6x94_CpuPstateThr_OFFSET 0 |
| 3008 | #define D18F6x94_CpuPstateThr_WIDTH 3 |
| 3009 | #define D18F6x94_CpuPstateThr_MASK 0x7 |
| 3010 | #define D18F6x94_CpuPstateThrEn_OFFSET 3 |
| 3011 | #define D18F6x94_CpuPstateThrEn_WIDTH 1 |
| 3012 | #define D18F6x94_CpuPstateThrEn_MASK 0x8 |
| 3013 | #define D18F6x94_NbPsNoTransOnDma_OFFSET 4 |
| 3014 | #define D18F6x94_NbPsNoTransOnDma_WIDTH 1 |
| 3015 | #define D18F6x94_NbPsNoTransOnDma_MASK 0x10 |
| 3016 | #define D18F6x94_Reserved_19_5_OFFSET 5 |
| 3017 | #define D18F6x94_Reserved_19_5_WIDTH 15 |
| 3018 | #define D18F6x94_Reserved_19_5_MASK 0xfffe0 |
| 3019 | #define D18F6x94_NbPsNonC0Timer_OFFSET 20 |
| 3020 | #define D18F6x94_NbPsNonC0Timer_WIDTH 3 |
| 3021 | #define D18F6x94_NbPsNonC0Timer_MASK 0x700000 |
| 3022 | #define D18F6x94_NbPsC0Timer_OFFSET 23 |
| 3023 | #define D18F6x94_NbPsC0Timer_WIDTH 3 |
| 3024 | #define D18F6x94_NbPsC0Timer_MASK 0x3800000 |
| 3025 | #define D18F6x94_NbPs1ResTmrMin_OFFSET 26 |
| 3026 | #define D18F6x94_NbPs1ResTmrMin_WIDTH 3 |
| 3027 | #define D18F6x94_NbPs1ResTmrMin_MASK 0x1c000000 |
| 3028 | #define D18F6x94_NbPs0ResTmrMin_OFFSET 29 |
| 3029 | #define D18F6x94_NbPs0ResTmrMin_WIDTH 3 |
| 3030 | #define D18F6x94_NbPs0ResTmrMin_MASK 0xe0000000 |
| 3031 | |
| 3032 | /// D18F6x94 |
| 3033 | typedef union { |
| 3034 | struct { ///< |
| 3035 | UINT32 CpuPstateThr:3 ; ///< |
| 3036 | UINT32 CpuPstateThrEn:1 ; ///< |
| 3037 | UINT32 NbPsNoTransOnDma:1 ; ///< |
| 3038 | UINT32 Reserved_19_5:15; ///< |
| 3039 | UINT32 NbPsNonC0Timer:3 ; ///< |
| 3040 | UINT32 NbPsC0Timer:3 ; ///< |
| 3041 | UINT32 NbPs1ResTmrMin:3 ; ///< |
| 3042 | UINT32 NbPs0ResTmrMin:3 ; ///< |
| 3043 | } Field; ///< |
| 3044 | UINT32 Value; ///< |
| 3045 | } D18F6x94_STRUCT; |
| 3046 | |
| 3047 | // **** D18F6x98 Register Definition **** |
| 3048 | // Address |
| 3049 | #define D18F6x98_ADDRESS 0x98 |
| 3050 | |
| 3051 | // Type |
| 3052 | #define D18F6x98_TYPE TYPE_D18F6 |
| 3053 | // Field Data |
| 3054 | #define D18F6x98_NbPsTransInFlight_OFFSET 0 |
| 3055 | #define D18F6x98_NbPsTransInFlight_WIDTH 1 |
| 3056 | #define D18F6x98_NbPsTransInFlight_MASK 0x1 |
| 3057 | #define D18F6x98_NbPs1ActSts_OFFSET 1 |
| 3058 | #define D18F6x98_NbPs1ActSts_WIDTH 1 |
| 3059 | #define D18F6x98_NbPs1ActSts_MASK 0x2 |
| 3060 | #define D18F6x98_NbPs1Act_OFFSET 2 |
| 3061 | #define D18F6x98_NbPs1Act_WIDTH 1 |
| 3062 | #define D18F6x98_NbPs1Act_MASK 0x4 |
| 3063 | #define D18F6x98_Reserved_29_3_OFFSET 3 |
| 3064 | #define D18F6x98_Reserved_29_3_WIDTH 27 |
| 3065 | #define D18F6x98_Reserved_29_3_MASK 0x3ffffff8 |
| 3066 | #define D18F6x98_NbPsCsrAccSel_OFFSET 30 |
| 3067 | #define D18F6x98_NbPsCsrAccSel_WIDTH 1 |
| 3068 | #define D18F6x98_NbPsCsrAccSel_MASK 0x40000000 |
| 3069 | #define D18F6x98_NbPsDbgEn_OFFSET 31 |
| 3070 | #define D18F6x98_NbPsDbgEn_WIDTH 1 |
| 3071 | #define D18F6x98_NbPsDbgEn_MASK 0x80000000 |
| 3072 | |
| 3073 | /// D18F6x98 |
| 3074 | typedef union { |
| 3075 | struct { ///< |
| 3076 | UINT32 NbPsTransInFlight:1 ; ///< |
| 3077 | UINT32 NbPs1ActSts:1 ; ///< |
| 3078 | UINT32 NbPs1Act:1 ; ///< |
| 3079 | UINT32 Reserved_29_3:27; ///< |
| 3080 | UINT32 NbPsCsrAccSel:1 ; ///< |
| 3081 | UINT32 NbPsDbgEn:1 ; ///< |
| 3082 | } Field; ///< |
| 3083 | UINT32 Value; ///< |
| 3084 | } D18F6x98_STRUCT; |
| 3085 | |
| 3086 | // **** D18F6x9C Register Definition **** |
| 3087 | // Address |
| 3088 | #define D18F6x9C_ADDRESS 0x9c |
| 3089 | |
| 3090 | // Type |
| 3091 | #define D18F6x9C_TYPE TYPE_D18F6 |
| 3092 | // Field Data |
| 3093 | #define D18F6x9C_NclkRedDiv_OFFSET 0 |
| 3094 | #define D18F6x9C_NclkRedDiv_WIDTH 7 |
| 3095 | #define D18F6x9C_NclkRedDiv_MASK 0x7f |
| 3096 | #define D18F6x9C_NclkRedSelfRefrAlways_OFFSET 7 |
| 3097 | #define D18F6x9C_NclkRedSelfRefrAlways_WIDTH 1 |
| 3098 | #define D18F6x9C_NclkRedSelfRefrAlways_MASK 0x80 |
| 3099 | #define D18F6x9C_NclkRampWithDllRelock_OFFSET 8 |
| 3100 | #define D18F6x9C_NclkRampWithDllRelock_WIDTH 1 |
| 3101 | #define D18F6x9C_NclkRampWithDllRelock_MASK 0x100 |
| 3102 | #define D18F6x9C_Reserved_31_9_OFFSET 9 |
| 3103 | #define D18F6x9C_Reserved_31_9_WIDTH 23 |
| 3104 | #define D18F6x9C_Reserved_31_9_MASK 0xfffffe00 |
| 3105 | |
| 3106 | /// D18F6x9C |
| 3107 | typedef union { |
| 3108 | struct { ///< |
| 3109 | UINT32 NclkRedDiv:7 ; ///< |
| 3110 | UINT32 NclkRedSelfRefrAlways:1 ; ///< |
| 3111 | UINT32 NclkRampWithDllRelock:1 ; ///< |
| 3112 | UINT32 Reserved_31_9:23; ///< |
| 3113 | } Field; ///< |
| 3114 | UINT32 Value; ///< |
| 3115 | } D18F6x9C_STRUCT; |
| 3116 | |
| 3117 | // **** DxF0x00 Register Definition **** |
| 3118 | // Address |
| 3119 | #define DxF0x00_ADDRESS 0x0 |
| 3120 | |
| 3121 | // Type |
| 3122 | #define DxF0x00_TYPE TYPE_D4F0 |
| 3123 | // Field Data |
| 3124 | #define DxF0x00_VendorID_OFFSET 0 |
| 3125 | #define DxF0x00_VendorID_WIDTH 16 |
| 3126 | #define DxF0x00_VendorID_MASK 0xffff |
| 3127 | #define DxF0x00_DeviceID_OFFSET 16 |
| 3128 | #define DxF0x00_DeviceID_WIDTH 16 |
| 3129 | #define DxF0x00_DeviceID_MASK 0xffff0000 |
| 3130 | |
| 3131 | /// DxF0x00 |
| 3132 | typedef union { |
| 3133 | struct { ///< |
| 3134 | UINT32 VendorID:16; ///< |
| 3135 | UINT32 DeviceID:16; ///< |
| 3136 | } Field; ///< |
| 3137 | UINT32 Value; ///< |
| 3138 | } DxF0x00_STRUCT; |
| 3139 | |
| 3140 | // **** DxF0x04 Register Definition **** |
| 3141 | // Address |
| 3142 | #define DxF0x04_ADDRESS 0x4 |
| 3143 | |
| 3144 | // Type |
| 3145 | #define DxF0x04_TYPE TYPE_D4F0 |
| 3146 | // Field Data |
| 3147 | #define DxF0x04_IoAccessEn_OFFSET 0 |
| 3148 | #define DxF0x04_IoAccessEn_WIDTH 1 |
| 3149 | #define DxF0x04_IoAccessEn_MASK 0x1 |
| 3150 | #define DxF0x04_MemAccessEn_OFFSET 1 |
| 3151 | #define DxF0x04_MemAccessEn_WIDTH 1 |
| 3152 | #define DxF0x04_MemAccessEn_MASK 0x2 |
| 3153 | #define DxF0x04_BusMasterEn_OFFSET 2 |
| 3154 | #define DxF0x04_BusMasterEn_WIDTH 1 |
| 3155 | #define DxF0x04_BusMasterEn_MASK 0x4 |
| 3156 | #define DxF0x04_SpecialCycleEn_OFFSET 3 |
| 3157 | #define DxF0x04_SpecialCycleEn_WIDTH 1 |
| 3158 | #define DxF0x04_SpecialCycleEn_MASK 0x8 |
| 3159 | #define DxF0x04_MemWriteInvalidateEn_OFFSET 4 |
| 3160 | #define DxF0x04_MemWriteInvalidateEn_WIDTH 1 |
| 3161 | #define DxF0x04_MemWriteInvalidateEn_MASK 0x10 |
| 3162 | #define DxF0x04_PalSnoopEn_OFFSET 5 |
| 3163 | #define DxF0x04_PalSnoopEn_WIDTH 1 |
| 3164 | #define DxF0x04_PalSnoopEn_MASK 0x20 |
| 3165 | #define DxF0x04_ParityErrorEn_OFFSET 6 |
| 3166 | #define DxF0x04_ParityErrorEn_WIDTH 1 |
| 3167 | #define DxF0x04_ParityErrorEn_MASK 0x40 |
| 3168 | #define DxF0x04_IdselStepping_OFFSET 7 |
| 3169 | #define DxF0x04_IdselStepping_WIDTH 1 |
| 3170 | #define DxF0x04_IdselStepping_MASK 0x80 |
| 3171 | #define DxF0x04_SerrEn_OFFSET 8 |
| 3172 | #define DxF0x04_SerrEn_WIDTH 1 |
| 3173 | #define DxF0x04_SerrEn_MASK 0x100 |
| 3174 | #define DxF0x04_FastB2BEn_OFFSET 9 |
| 3175 | #define DxF0x04_FastB2BEn_WIDTH 1 |
| 3176 | #define DxF0x04_FastB2BEn_MASK 0x200 |
| 3177 | #define DxF0x04_IntDis_OFFSET 10 |
| 3178 | #define DxF0x04_IntDis_WIDTH 1 |
| 3179 | #define DxF0x04_IntDis_MASK 0x400 |
| 3180 | #define DxF0x04_Reserved_18_11_OFFSET 11 |
| 3181 | #define DxF0x04_Reserved_18_11_WIDTH 8 |
| 3182 | #define DxF0x04_Reserved_18_11_MASK 0x7f800 |
| 3183 | #define DxF0x04_IntStatus_OFFSET 19 |
| 3184 | #define DxF0x04_IntStatus_WIDTH 1 |
| 3185 | #define DxF0x04_IntStatus_MASK 0x80000 |
| 3186 | #define DxF0x04_CapList_OFFSET 20 |
| 3187 | #define DxF0x04_CapList_WIDTH 1 |
| 3188 | #define DxF0x04_CapList_MASK 0x100000 |
| 3189 | #define DxF0x04_PCI66En_OFFSET 21 |
| 3190 | #define DxF0x04_PCI66En_WIDTH 1 |
| 3191 | #define DxF0x04_PCI66En_MASK 0x200000 |
| 3192 | #define DxF0x04_UDFEn_OFFSET 22 |
| 3193 | #define DxF0x04_UDFEn_WIDTH 1 |
| 3194 | #define DxF0x04_UDFEn_MASK 0x400000 |
| 3195 | #define DxF0x04_FastBackCapable_OFFSET 23 |
| 3196 | #define DxF0x04_FastBackCapable_WIDTH 1 |
| 3197 | #define DxF0x04_FastBackCapable_MASK 0x800000 |
| 3198 | #define DxF0x04_MasterDataPerr_OFFSET 24 |
| 3199 | #define DxF0x04_MasterDataPerr_WIDTH 1 |
| 3200 | #define DxF0x04_MasterDataPerr_MASK 0x1000000 |
| 3201 | #define DxF0x04_DevselTiming_OFFSET 25 |
| 3202 | #define DxF0x04_DevselTiming_WIDTH 2 |
| 3203 | #define DxF0x04_DevselTiming_MASK 0x6000000 |
| 3204 | #define DxF0x04_SignaledTargetAbort_OFFSET 27 |
| 3205 | #define DxF0x04_SignaledTargetAbort_WIDTH 1 |
| 3206 | #define DxF0x04_SignaledTargetAbort_MASK 0x8000000 |
| 3207 | #define DxF0x04_ReceivedTargetAbort_OFFSET 28 |
| 3208 | #define DxF0x04_ReceivedTargetAbort_WIDTH 1 |
| 3209 | #define DxF0x04_ReceivedTargetAbort_MASK 0x10000000 |
| 3210 | #define DxF0x04_ReceivedMasterAbort_OFFSET 29 |
| 3211 | #define DxF0x04_ReceivedMasterAbort_WIDTH 1 |
| 3212 | #define DxF0x04_ReceivedMasterAbort_MASK 0x20000000 |
| 3213 | #define DxF0x04_SignaledSystemError_OFFSET 30 |
| 3214 | #define DxF0x04_SignaledSystemError_WIDTH 1 |
| 3215 | #define DxF0x04_SignaledSystemError_MASK 0x40000000 |
| 3216 | #define DxF0x04_ParityErrorDetected_OFFSET 31 |
| 3217 | #define DxF0x04_ParityErrorDetected_WIDTH 1 |
| 3218 | #define DxF0x04_ParityErrorDetected_MASK 0x80000000 |
| 3219 | |
| 3220 | /// DxF0x04 |
| 3221 | typedef union { |
| 3222 | struct { ///< |
| 3223 | UINT32 IoAccessEn:1 ; ///< |
| 3224 | UINT32 MemAccessEn:1 ; ///< |
| 3225 | UINT32 BusMasterEn:1 ; ///< |
| 3226 | UINT32 SpecialCycleEn:1 ; ///< |
| 3227 | UINT32 MemWriteInvalidateEn:1 ; ///< |
| 3228 | UINT32 PalSnoopEn:1 ; ///< |
| 3229 | UINT32 ParityErrorEn:1 ; ///< |
| 3230 | UINT32 IdselStepping:1 ; ///< |
| 3231 | UINT32 SerrEn:1 ; ///< |
| 3232 | UINT32 FastB2BEn:1 ; ///< |
| 3233 | UINT32 IntDis:1 ; ///< |
| 3234 | UINT32 Reserved_18_11:8 ; ///< |
| 3235 | UINT32 IntStatus:1 ; ///< |
| 3236 | UINT32 CapList:1 ; ///< |
| 3237 | UINT32 PCI66En:1 ; ///< |
| 3238 | UINT32 UDFEn:1 ; ///< |
| 3239 | UINT32 FastBackCapable:1 ; ///< |
| 3240 | UINT32 MasterDataPerr:1 ; ///< |
| 3241 | UINT32 DevselTiming:2 ; ///< |
| 3242 | UINT32 SignaledTargetAbort:1 ; ///< |
| 3243 | UINT32 ReceivedTargetAbort:1 ; ///< |
| 3244 | UINT32 ReceivedMasterAbort:1 ; ///< |
| 3245 | UINT32 SignaledSystemError:1 ; ///< |
| 3246 | UINT32 ParityErrorDetected:1 ; ///< |
| 3247 | } Field; ///< |
| 3248 | UINT32 Value; ///< |
| 3249 | } DxF0x04_STRUCT; |
| 3250 | |
| 3251 | // **** DxF0x08 Register Definition **** |
| 3252 | // Address |
| 3253 | #define DxF0x08_ADDRESS 0x8 |
| 3254 | |
| 3255 | // Type |
| 3256 | #define DxF0x08_TYPE TYPE_D4F0 |
| 3257 | // Field Data |
| 3258 | #define DxF0x08_RevID_OFFSET 0 |
| 3259 | #define DxF0x08_RevID_WIDTH 8 |
| 3260 | #define DxF0x08_RevID_MASK 0xff |
| 3261 | #define DxF0x08_ClassCode_OFFSET 8 |
| 3262 | #define DxF0x08_ClassCode_WIDTH 24 |
| 3263 | #define DxF0x08_ClassCode_MASK 0xffffff00 |
| 3264 | |
| 3265 | /// DxF0x08 |
| 3266 | typedef union { |
| 3267 | struct { ///< |
| 3268 | UINT32 RevID:8 ; ///< |
| 3269 | UINT32 ClassCode:24; ///< |
| 3270 | } Field; ///< |
| 3271 | UINT32 Value; ///< |
| 3272 | } DxF0x08_STRUCT; |
| 3273 | |
| 3274 | // **** DxF0x0C Register Definition **** |
| 3275 | // Address |
| 3276 | #define DxF0x0C_ADDRESS 0xc |
| 3277 | |
| 3278 | // Type |
| 3279 | #define DxF0x0C_TYPE TYPE_D4F0 |
| 3280 | // Field Data |
| 3281 | #define DxF0x0C_CacheLineSize_OFFSET 0 |
| 3282 | #define DxF0x0C_CacheLineSize_WIDTH 8 |
| 3283 | #define DxF0x0C_CacheLineSize_MASK 0xff |
| 3284 | #define DxF0x0C_LatencyTimer_OFFSET 8 |
| 3285 | #define DxF0x0C_LatencyTimer_WIDTH 8 |
| 3286 | #define DxF0x0C_LatencyTimer_MASK 0xff00 |
| 3287 | #define DxF0x0C_HeaderTypeReg_OFFSET 16 |
| 3288 | #define DxF0x0C_HeaderTypeReg_WIDTH 8 |
| 3289 | #define DxF0x0C_HeaderTypeReg_MASK 0xff0000 |
| 3290 | #define DxF0x0C_BIST_OFFSET 24 |
| 3291 | #define DxF0x0C_BIST_WIDTH 8 |
| 3292 | #define DxF0x0C_BIST_MASK 0xff000000 |
| 3293 | |
| 3294 | /// DxF0x0C |
| 3295 | typedef union { |
| 3296 | struct { ///< |
| 3297 | UINT32 CacheLineSize:8 ; ///< |
| 3298 | UINT32 LatencyTimer:8 ; ///< |
| 3299 | UINT32 HeaderTypeReg:8 ; ///< |
| 3300 | UINT32 BIST:8 ; ///< |
| 3301 | } Field; ///< |
| 3302 | UINT32 Value; ///< |
| 3303 | } DxF0x0C_STRUCT; |
| 3304 | |
| 3305 | // **** DxF0x18 Register Definition **** |
| 3306 | // Address |
| 3307 | #define DxF0x18_ADDRESS 0x18 |
| 3308 | |
| 3309 | // Type |
| 3310 | #define DxF0x18_TYPE TYPE_D4F0 |
| 3311 | // Field Data |
| 3312 | #define DxF0x18_PrimaryBus_OFFSET 0 |
| 3313 | #define DxF0x18_PrimaryBus_WIDTH 8 |
| 3314 | #define DxF0x18_PrimaryBus_MASK 0xff |
| 3315 | #define DxF0x18_SecondaryBus_OFFSET 8 |
| 3316 | #define DxF0x18_SecondaryBus_WIDTH 8 |
| 3317 | #define DxF0x18_SecondaryBus_MASK 0xff00 |
| 3318 | #define DxF0x18_SubBusNumber_OFFSET 16 |
| 3319 | #define DxF0x18_SubBusNumber_WIDTH 8 |
| 3320 | #define DxF0x18_SubBusNumber_MASK 0xff0000 |
| 3321 | #define DxF0x18_SecondaryLatencyTimer_OFFSET 24 |
| 3322 | #define DxF0x18_SecondaryLatencyTimer_WIDTH 8 |
| 3323 | #define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000 |
| 3324 | |
| 3325 | /// DxF0x18 |
| 3326 | typedef union { |
| 3327 | struct { ///< |
| 3328 | UINT32 PrimaryBus:8 ; ///< |
| 3329 | UINT32 SecondaryBus:8 ; ///< |
| 3330 | UINT32 SubBusNumber:8 ; ///< |
| 3331 | UINT32 SecondaryLatencyTimer:8 ; ///< |
| 3332 | } Field; ///< |
| 3333 | UINT32 Value; ///< |
| 3334 | } DxF0x18_STRUCT; |
| 3335 | |
| 3336 | // **** DxF0x1C Register Definition **** |
| 3337 | // Address |
| 3338 | #define DxF0x1C_ADDRESS 0x1c |
| 3339 | |
| 3340 | // Type |
| 3341 | #define DxF0x1C_TYPE TYPE_D4F0 |
| 3342 | // Field Data |
| 3343 | #define DxF0x1C_Reserved_3_0_OFFSET 0 |
| 3344 | #define DxF0x1C_Reserved_3_0_WIDTH 4 |
| 3345 | #define DxF0x1C_Reserved_3_0_MASK 0xf |
| 3346 | #define DxF0x1C_IOBase_15_12__OFFSET 4 |
| 3347 | #define DxF0x1C_IOBase_15_12__WIDTH 4 |
| 3348 | #define DxF0x1C_IOBase_15_12__MASK 0xf0 |
| 3349 | #define DxF0x1C_Reserved_11_8_OFFSET 8 |
| 3350 | #define DxF0x1C_Reserved_11_8_WIDTH 4 |
| 3351 | #define DxF0x1C_Reserved_11_8_MASK 0xf00 |
| 3352 | #define DxF0x1C_IOLimit_15_12__OFFSET 12 |
| 3353 | #define DxF0x1C_IOLimit_15_12__WIDTH 4 |
| 3354 | #define DxF0x1C_IOLimit_15_12__MASK 0xf000 |
| 3355 | #define DxF0x1C_Reserved_19_16_OFFSET 16 |
| 3356 | #define DxF0x1C_Reserved_19_16_WIDTH 4 |
| 3357 | #define DxF0x1C_Reserved_19_16_MASK 0xf0000 |
| 3358 | #define DxF0x1C_CapList_OFFSET 20 |
| 3359 | #define DxF0x1C_CapList_WIDTH 1 |
| 3360 | #define DxF0x1C_CapList_MASK 0x100000 |
| 3361 | #define DxF0x1C_PCI66En_OFFSET 21 |
| 3362 | #define DxF0x1C_PCI66En_WIDTH 1 |
| 3363 | #define DxF0x1C_PCI66En_MASK 0x200000 |
| 3364 | #define DxF0x1C_UDFEn_OFFSET 22 |
| 3365 | #define DxF0x1C_UDFEn_WIDTH 1 |
| 3366 | #define DxF0x1C_UDFEn_MASK 0x400000 |
| 3367 | #define DxF0x1C_FastBackCapable_OFFSET 23 |
| 3368 | #define DxF0x1C_FastBackCapable_WIDTH 1 |
| 3369 | #define DxF0x1C_FastBackCapable_MASK 0x800000 |
| 3370 | #define DxF0x1C_MasterDataPerr_OFFSET 24 |
| 3371 | #define DxF0x1C_MasterDataPerr_WIDTH 1 |
| 3372 | #define DxF0x1C_MasterDataPerr_MASK 0x1000000 |
| 3373 | #define DxF0x1C_DevselTiming_OFFSET 25 |
| 3374 | #define DxF0x1C_DevselTiming_WIDTH 2 |
| 3375 | #define DxF0x1C_DevselTiming_MASK 0x6000000 |
| 3376 | #define DxF0x1C_SignalTargetAbort_OFFSET 27 |
| 3377 | #define DxF0x1C_SignalTargetAbort_WIDTH 1 |
| 3378 | #define DxF0x1C_SignalTargetAbort_MASK 0x8000000 |
| 3379 | #define DxF0x1C_ReceivedTargetAbort_OFFSET 28 |
| 3380 | #define DxF0x1C_ReceivedTargetAbort_WIDTH 1 |
| 3381 | #define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000 |
| 3382 | #define DxF0x1C_ReceivedMasterAbort_OFFSET 29 |
| 3383 | #define DxF0x1C_ReceivedMasterAbort_WIDTH 1 |
| 3384 | #define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000 |
| 3385 | #define DxF0x1C_ReceivedSystemError_OFFSET 30 |
| 3386 | #define DxF0x1C_ReceivedSystemError_WIDTH 1 |
| 3387 | #define DxF0x1C_ReceivedSystemError_MASK 0x40000000 |
| 3388 | #define DxF0x1C_ParityErrorDetected_OFFSET 31 |
| 3389 | #define DxF0x1C_ParityErrorDetected_WIDTH 1 |
| 3390 | #define DxF0x1C_ParityErrorDetected_MASK 0x80000000 |
| 3391 | |
| 3392 | /// DxF0x1C |
| 3393 | typedef union { |
| 3394 | struct { ///< |
| 3395 | UINT32 Reserved_3_0:4 ; ///< |
| 3396 | UINT32 IOBase_15_12_:4 ; ///< |
| 3397 | UINT32 Reserved_11_8:4 ; ///< |
| 3398 | UINT32 IOLimit_15_12_:4 ; ///< |
| 3399 | UINT32 Reserved_19_16:4 ; ///< |
| 3400 | UINT32 CapList:1 ; ///< |
| 3401 | UINT32 PCI66En:1 ; ///< |
| 3402 | UINT32 UDFEn:1 ; ///< |
| 3403 | UINT32 FastBackCapable:1 ; ///< |
| 3404 | UINT32 MasterDataPerr:1 ; ///< |
| 3405 | UINT32 DevselTiming:2 ; ///< |
| 3406 | UINT32 SignalTargetAbort:1 ; ///< |
| 3407 | UINT32 ReceivedTargetAbort:1 ; ///< |
| 3408 | UINT32 ReceivedMasterAbort:1 ; ///< |
| 3409 | UINT32 ReceivedSystemError:1 ; ///< |
| 3410 | UINT32 ParityErrorDetected:1 ; ///< |
| 3411 | } Field; ///< |
| 3412 | UINT32 Value; ///< |
| 3413 | } DxF0x1C_STRUCT; |
| 3414 | |
| 3415 | // **** DxF0x20 Register Definition **** |
| 3416 | // Address |
| 3417 | #define DxF0x20_ADDRESS 0x20 |
| 3418 | |
| 3419 | // Type |
| 3420 | #define DxF0x20_TYPE TYPE_D4F0 |
| 3421 | // Field Data |
| 3422 | #define DxF0x20_Reserved_3_0_OFFSET 0 |
| 3423 | #define DxF0x20_Reserved_3_0_WIDTH 4 |
| 3424 | #define DxF0x20_Reserved_3_0_MASK 0xf |
| 3425 | #define DxF0x20_MemBase_OFFSET 4 |
| 3426 | #define DxF0x20_MemBase_WIDTH 12 |
| 3427 | #define DxF0x20_MemBase_MASK 0xfff0 |
| 3428 | #define DxF0x20_Reserved_19_16_OFFSET 16 |
| 3429 | #define DxF0x20_Reserved_19_16_WIDTH 4 |
| 3430 | #define DxF0x20_Reserved_19_16_MASK 0xf0000 |
| 3431 | #define DxF0x20_MemLimit_OFFSET 20 |
| 3432 | #define DxF0x20_MemLimit_WIDTH 12 |
| 3433 | #define DxF0x20_MemLimit_MASK 0xfff00000 |
| 3434 | |
| 3435 | /// DxF0x20 |
| 3436 | typedef union { |
| 3437 | struct { ///< |
| 3438 | UINT32 Reserved_3_0:4 ; ///< |
| 3439 | UINT32 MemBase:12; ///< |
| 3440 | UINT32 Reserved_19_16:4 ; ///< |
| 3441 | UINT32 MemLimit:12; ///< |
| 3442 | } Field; ///< |
| 3443 | UINT32 Value; ///< |
| 3444 | } DxF0x20_STRUCT; |
| 3445 | |
| 3446 | // **** DxF0x24 Register Definition **** |
| 3447 | // Address |
| 3448 | #define DxF0x24_ADDRESS 0x24 |
| 3449 | |
| 3450 | // Type |
| 3451 | #define DxF0x24_TYPE TYPE_D4F0 |
| 3452 | // Field Data |
| 3453 | #define DxF0x24_PrefMemBaseR_OFFSET 0 |
| 3454 | #define DxF0x24_PrefMemBaseR_WIDTH 4 |
| 3455 | #define DxF0x24_PrefMemBaseR_MASK 0xf |
| 3456 | #define DxF0x24_PrefMemBase_31_20__OFFSET 4 |
| 3457 | #define DxF0x24_PrefMemBase_31_20__WIDTH 12 |
| 3458 | #define DxF0x24_PrefMemBase_31_20__MASK 0xfff0 |
| 3459 | #define DxF0x24_PrefMemLimitR_OFFSET 16 |
| 3460 | #define DxF0x24_PrefMemLimitR_WIDTH 4 |
| 3461 | #define DxF0x24_PrefMemLimitR_MASK 0xf0000 |
| 3462 | #define DxF0x24_PrefMemLimit_OFFSET 20 |
| 3463 | #define DxF0x24_PrefMemLimit_WIDTH 12 |
| 3464 | #define DxF0x24_PrefMemLimit_MASK 0xfff00000 |
| 3465 | |
| 3466 | /// DxF0x24 |
| 3467 | typedef union { |
| 3468 | struct { ///< |
| 3469 | UINT32 PrefMemBaseR:4 ; ///< |
| 3470 | UINT32 PrefMemBase_31_20_:12; ///< |
| 3471 | UINT32 PrefMemLimitR:4 ; ///< |
| 3472 | UINT32 PrefMemLimit:12; ///< |
| 3473 | } Field; ///< |
| 3474 | UINT32 Value; ///< |
| 3475 | } DxF0x24_STRUCT; |
| 3476 | |
| 3477 | // **** DxF0x28 Register Definition **** |
| 3478 | // Address |
| 3479 | #define DxF0x28_ADDRESS 0x28 |
| 3480 | |
| 3481 | // Type |
| 3482 | #define DxF0x28_TYPE TYPE_D4F0 |
| 3483 | // Field Data |
| 3484 | #define DxF0x28_PrefMemBase_63_32__OFFSET 0 |
| 3485 | #define DxF0x28_PrefMemBase_63_32__WIDTH 32 |
| 3486 | #define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff |
| 3487 | |
| 3488 | /// DxF0x28 |
| 3489 | typedef union { |
| 3490 | struct { ///< |
| 3491 | UINT32 PrefMemBase_63_32_:32; ///< |
| 3492 | } Field; ///< |
| 3493 | UINT32 Value; ///< |
| 3494 | } DxF0x28_STRUCT; |
| 3495 | |
| 3496 | // **** DxF0x2C Register Definition **** |
| 3497 | // Address |
| 3498 | #define DxF0x2C_ADDRESS 0x2c |
| 3499 | |
| 3500 | // Type |
| 3501 | #define DxF0x2C_TYPE TYPE_D4F0 |
| 3502 | // Field Data |
| 3503 | #define DxF0x2C_PrefMemLimit_63_32__OFFSET 0 |
| 3504 | #define DxF0x2C_PrefMemLimit_63_32__WIDTH 32 |
| 3505 | #define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff |
| 3506 | |
| 3507 | /// DxF0x2C |
| 3508 | typedef union { |
| 3509 | struct { ///< |
| 3510 | UINT32 PrefMemLimit_63_32_:32; ///< |
| 3511 | } Field; ///< |
| 3512 | UINT32 Value; ///< |
| 3513 | } DxF0x2C_STRUCT; |
| 3514 | |
| 3515 | // **** DxF0x30 Register Definition **** |
| 3516 | // Address |
| 3517 | #define DxF0x30_ADDRESS 0x30 |
| 3518 | |
| 3519 | // Type |
| 3520 | #define DxF0x30_TYPE TYPE_D4F0 |
| 3521 | // Field Data |
| 3522 | #define DxF0x30_IOBase_31_16__OFFSET 0 |
| 3523 | #define DxF0x30_IOBase_31_16__WIDTH 16 |
| 3524 | #define DxF0x30_IOBase_31_16__MASK 0xffff |
| 3525 | #define DxF0x30_IOLimit_31_16__OFFSET 16 |
| 3526 | #define DxF0x30_IOLimit_31_16__WIDTH 16 |
| 3527 | #define DxF0x30_IOLimit_31_16__MASK 0xffff0000 |
| 3528 | |
| 3529 | /// DxF0x30 |
| 3530 | typedef union { |
| 3531 | struct { ///< |
| 3532 | UINT32 IOBase_31_16_:16; ///< |
| 3533 | UINT32 IOLimit_31_16_:16; ///< |
| 3534 | } Field; ///< |
| 3535 | UINT32 Value; ///< |
| 3536 | } DxF0x30_STRUCT; |
| 3537 | |
| 3538 | // **** DxF0x34 Register Definition **** |
| 3539 | // Address |
| 3540 | #define DxF0x34_ADDRESS 0x34 |
| 3541 | |
| 3542 | // Type |
| 3543 | #define DxF0x34_TYPE TYPE_D4F0 |
| 3544 | // Field Data |
| 3545 | #define DxF0x34_CapPtr_OFFSET 0 |
| 3546 | #define DxF0x34_CapPtr_WIDTH 8 |
| 3547 | #define DxF0x34_CapPtr_MASK 0xff |
| 3548 | #define DxF0x34_Reserved_31_8_OFFSET 8 |
| 3549 | #define DxF0x34_Reserved_31_8_WIDTH 24 |
| 3550 | #define DxF0x34_Reserved_31_8_MASK 0xffffff00 |
| 3551 | |
| 3552 | /// DxF0x34 |
| 3553 | typedef union { |
| 3554 | struct { ///< |
| 3555 | UINT32 CapPtr:8 ; ///< |
| 3556 | UINT32 Reserved_31_8:24; ///< |
| 3557 | } Field; ///< |
| 3558 | UINT32 Value; ///< |
| 3559 | } DxF0x34_STRUCT; |
| 3560 | |
| 3561 | // **** DxF0x3C Register Definition **** |
| 3562 | // Address |
| 3563 | #define DxF0x3C_ADDRESS 0x3c |
| 3564 | |
| 3565 | // Type |
| 3566 | #define DxF0x3C_TYPE TYPE_D4F0 |
| 3567 | // Field Data |
| 3568 | #define DxF0x3C_IntLine_OFFSET 0 |
| 3569 | #define DxF0x3C_IntLine_WIDTH 8 |
| 3570 | #define DxF0x3C_IntLine_MASK 0xff |
| 3571 | #define DxF0x3C_IntPin_OFFSET 8 |
| 3572 | #define DxF0x3C_IntPin_WIDTH 3 |
| 3573 | #define DxF0x3C_IntPin_MASK 0x700 |
| 3574 | #define DxF0x3C_Reserved_15_11_OFFSET 11 |
| 3575 | #define DxF0x3C_Reserved_15_11_WIDTH 5 |
| 3576 | #define DxF0x3C_Reserved_15_11_MASK 0xf800 |
| 3577 | #define DxF0x3C_ParityResponseEn_OFFSET 16 |
| 3578 | #define DxF0x3C_ParityResponseEn_WIDTH 1 |
| 3579 | #define DxF0x3C_ParityResponseEn_MASK 0x10000 |
| 3580 | #define DxF0x3C_SerrEn_OFFSET 17 |
| 3581 | #define DxF0x3C_SerrEn_WIDTH 1 |
| 3582 | #define DxF0x3C_SerrEn_MASK 0x20000 |
| 3583 | #define DxF0x3C_IsaEn_OFFSET 18 |
| 3584 | #define DxF0x3C_IsaEn_WIDTH 1 |
| 3585 | #define DxF0x3C_IsaEn_MASK 0x40000 |
| 3586 | #define DxF0x3C_VgaEn_OFFSET 19 |
| 3587 | #define DxF0x3C_VgaEn_WIDTH 1 |
| 3588 | #define DxF0x3C_VgaEn_MASK 0x80000 |
| 3589 | #define DxF0x3C_Vga16En_OFFSET 20 |
| 3590 | #define DxF0x3C_Vga16En_WIDTH 1 |
| 3591 | #define DxF0x3C_Vga16En_MASK 0x100000 |
| 3592 | #define DxF0x3C_MasterAbortMode_OFFSET 21 |
| 3593 | #define DxF0x3C_MasterAbortMode_WIDTH 1 |
| 3594 | #define DxF0x3C_MasterAbortMode_MASK 0x200000 |
| 3595 | #define DxF0x3C_SecondaryBusReset_OFFSET 22 |
| 3596 | #define DxF0x3C_SecondaryBusReset_WIDTH 1 |
| 3597 | #define DxF0x3C_SecondaryBusReset_MASK 0x400000 |
| 3598 | #define DxF0x3C_FastB2BCap_OFFSET 23 |
| 3599 | #define DxF0x3C_FastB2BCap_WIDTH 1 |
| 3600 | #define DxF0x3C_FastB2BCap_MASK 0x800000 |
| 3601 | #define DxF0x3C_Reserved_31_24_OFFSET 24 |
| 3602 | #define DxF0x3C_Reserved_31_24_WIDTH 8 |
| 3603 | #define DxF0x3C_Reserved_31_24_MASK 0xff000000 |
| 3604 | |
| 3605 | /// DxF0x3C |
| 3606 | typedef union { |
| 3607 | struct { ///< |
| 3608 | UINT32 IntLine:8 ; ///< |
| 3609 | UINT32 IntPin:3 ; ///< |
| 3610 | UINT32 Reserved_15_11:5 ; ///< |
| 3611 | UINT32 ParityResponseEn:1 ; ///< |
| 3612 | UINT32 SerrEn:1 ; ///< |
| 3613 | UINT32 IsaEn:1 ; ///< |
| 3614 | UINT32 VgaEn:1 ; ///< |
| 3615 | UINT32 Vga16En:1 ; ///< |
| 3616 | UINT32 MasterAbortMode:1 ; ///< |
| 3617 | UINT32 SecondaryBusReset:1 ; ///< |
| 3618 | UINT32 FastB2BCap:1 ; ///< |
| 3619 | UINT32 Reserved_31_24:8 ; ///< |
| 3620 | } Field; ///< |
| 3621 | UINT32 Value; ///< |
| 3622 | } DxF0x3C_STRUCT; |
| 3623 | |
| 3624 | // **** DxF0x50 Register Definition **** |
| 3625 | // Address |
| 3626 | #define DxF0x50_ADDRESS 0x50 |
| 3627 | |
| 3628 | // Type |
| 3629 | #define DxF0x50_TYPE TYPE_D4F0 |
| 3630 | // Field Data |
| 3631 | #define DxF0x50_CapID_OFFSET 0 |
| 3632 | #define DxF0x50_CapID_WIDTH 8 |
| 3633 | #define DxF0x50_CapID_MASK 0xff |
| 3634 | #define DxF0x50_NextPtr_OFFSET 8 |
| 3635 | #define DxF0x50_NextPtr_WIDTH 8 |
| 3636 | #define DxF0x50_NextPtr_MASK 0xff00 |
| 3637 | #define DxF0x50_Version_OFFSET 16 |
| 3638 | #define DxF0x50_Version_WIDTH 3 |
| 3639 | #define DxF0x50_Version_MASK 0x70000 |
| 3640 | #define DxF0x50_PmeClock_OFFSET 19 |
| 3641 | #define DxF0x50_PmeClock_WIDTH 1 |
| 3642 | #define DxF0x50_PmeClock_MASK 0x80000 |
| 3643 | #define DxF0x50_Reserved_20_20_OFFSET 20 |
| 3644 | #define DxF0x50_Reserved_20_20_WIDTH 1 |
| 3645 | #define DxF0x50_Reserved_20_20_MASK 0x100000 |
| 3646 | #define DxF0x50_DevSpecificInit_OFFSET 21 |
| 3647 | #define DxF0x50_DevSpecificInit_WIDTH 1 |
| 3648 | #define DxF0x50_DevSpecificInit_MASK 0x200000 |
| 3649 | #define DxF0x50_AuxCurrent_OFFSET 22 |
| 3650 | #define DxF0x50_AuxCurrent_WIDTH 3 |
| 3651 | #define DxF0x50_AuxCurrent_MASK 0x1c00000 |
| 3652 | #define DxF0x50_D1Support_OFFSET 25 |
| 3653 | #define DxF0x50_D1Support_WIDTH 1 |
| 3654 | #define DxF0x50_D1Support_MASK 0x2000000 |
| 3655 | #define DxF0x50_D2Support_OFFSET 26 |
| 3656 | #define DxF0x50_D2Support_WIDTH 1 |
| 3657 | #define DxF0x50_D2Support_MASK 0x4000000 |
| 3658 | #define DxF0x50_PmeSupport_OFFSET 27 |
| 3659 | #define DxF0x50_PmeSupport_WIDTH 5 |
| 3660 | #define DxF0x50_PmeSupport_MASK 0xf8000000 |
| 3661 | |
| 3662 | /// DxF0x50 |
| 3663 | typedef union { |
| 3664 | struct { ///< |
| 3665 | UINT32 CapID:8 ; ///< |
| 3666 | UINT32 NextPtr:8 ; ///< |
| 3667 | UINT32 Version:3 ; ///< |
| 3668 | UINT32 PmeClock:1 ; ///< |
| 3669 | UINT32 Reserved_20_20:1 ; ///< |
| 3670 | UINT32 DevSpecificInit:1 ; ///< |
| 3671 | UINT32 AuxCurrent:3 ; ///< |
| 3672 | UINT32 D1Support:1 ; ///< |
| 3673 | UINT32 D2Support:1 ; ///< |
| 3674 | UINT32 PmeSupport:5 ; ///< |
| 3675 | } Field; ///< |
| 3676 | UINT32 Value; ///< |
| 3677 | } DxF0x50_STRUCT; |
| 3678 | |
| 3679 | // **** DxF0x54 Register Definition **** |
| 3680 | // Address |
| 3681 | #define DxF0x54_ADDRESS 0x54 |
| 3682 | |
| 3683 | // Type |
| 3684 | #define DxF0x54_TYPE TYPE_D4F0 |
| 3685 | // Field Data |
| 3686 | #define DxF0x54_PowerState_OFFSET 0 |
| 3687 | #define DxF0x54_PowerState_WIDTH 2 |
| 3688 | #define DxF0x54_PowerState_MASK 0x3 |
| 3689 | #define DxF0x54_Reserved_2_2_OFFSET 2 |
| 3690 | #define DxF0x54_Reserved_2_2_WIDTH 1 |
| 3691 | #define DxF0x54_Reserved_2_2_MASK 0x4 |
| 3692 | #define DxF0x54_NoSoftReset_OFFSET 3 |
| 3693 | #define DxF0x54_NoSoftReset_WIDTH 1 |
| 3694 | #define DxF0x54_NoSoftReset_MASK 0x8 |
| 3695 | #define DxF0x54_Reserved_7_4_OFFSET 4 |
| 3696 | #define DxF0x54_Reserved_7_4_WIDTH 4 |
| 3697 | #define DxF0x54_Reserved_7_4_MASK 0xf0 |
| 3698 | #define DxF0x54_PmeEn_OFFSET 8 |
| 3699 | #define DxF0x54_PmeEn_WIDTH 1 |
| 3700 | #define DxF0x54_PmeEn_MASK 0x100 |
| 3701 | #define DxF0x54_DataSelect_OFFSET 9 |
| 3702 | #define DxF0x54_DataSelect_WIDTH 4 |
| 3703 | #define DxF0x54_DataSelect_MASK 0x1e00 |
| 3704 | #define DxF0x54_DataScale_OFFSET 13 |
| 3705 | #define DxF0x54_DataScale_WIDTH 2 |
| 3706 | #define DxF0x54_DataScale_MASK 0x6000 |
| 3707 | #define DxF0x54_PmeStatus_OFFSET 15 |
| 3708 | #define DxF0x54_PmeStatus_WIDTH 1 |
| 3709 | #define DxF0x54_PmeStatus_MASK 0x8000 |
| 3710 | #define DxF0x54_Reserved_21_16_OFFSET 16 |
| 3711 | #define DxF0x54_Reserved_21_16_WIDTH 6 |
| 3712 | #define DxF0x54_Reserved_21_16_MASK 0x3f0000 |
| 3713 | #define DxF0x54_B2B3Support_OFFSET 22 |
| 3714 | #define DxF0x54_B2B3Support_WIDTH 1 |
| 3715 | #define DxF0x54_B2B3Support_MASK 0x400000 |
| 3716 | #define DxF0x54_BusPwrEn_OFFSET 23 |
| 3717 | #define DxF0x54_BusPwrEn_WIDTH 1 |
| 3718 | #define DxF0x54_BusPwrEn_MASK 0x800000 |
| 3719 | #define DxF0x54_PmeData_OFFSET 24 |
| 3720 | #define DxF0x54_PmeData_WIDTH 8 |
| 3721 | #define DxF0x54_PmeData_MASK 0xff000000 |
| 3722 | |
| 3723 | /// DxF0x54 |
| 3724 | typedef union { |
| 3725 | struct { ///< |
| 3726 | UINT32 PowerState:2 ; ///< |
| 3727 | UINT32 Reserved_2_2:1 ; ///< |
| 3728 | UINT32 NoSoftReset:1 ; ///< |
| 3729 | UINT32 Reserved_7_4:4 ; ///< |
| 3730 | UINT32 PmeEn:1 ; ///< |
| 3731 | UINT32 DataSelect:4 ; ///< |
| 3732 | UINT32 DataScale:2 ; ///< |
| 3733 | UINT32 PmeStatus:1 ; ///< |
| 3734 | UINT32 Reserved_21_16:6 ; ///< |
| 3735 | UINT32 B2B3Support:1 ; ///< |
| 3736 | UINT32 BusPwrEn:1 ; ///< |
| 3737 | UINT32 PmeData:8 ; ///< |
| 3738 | } Field; ///< |
| 3739 | UINT32 Value; ///< |
| 3740 | } DxF0x54_STRUCT; |
| 3741 | |
| 3742 | // **** DxF0x58 Register Definition **** |
| 3743 | // Address |
| 3744 | #define DxF0x58_ADDRESS 0x58 |
| 3745 | |
| 3746 | // Type |
| 3747 | #define DxF0x58_TYPE TYPE_D4F0 |
| 3748 | // Field Data |
| 3749 | #define DxF0x58_CapID_OFFSET 0 |
| 3750 | #define DxF0x58_CapID_WIDTH 8 |
| 3751 | #define DxF0x58_CapID_MASK 0xff |
| 3752 | #define DxF0x58_NextPtr_OFFSET 8 |
| 3753 | #define DxF0x58_NextPtr_WIDTH 8 |
| 3754 | #define DxF0x58_NextPtr_MASK 0xff00 |
| 3755 | #define DxF0x58_Version_OFFSET 16 |
| 3756 | #define DxF0x58_Version_WIDTH 4 |
| 3757 | #define DxF0x58_Version_MASK 0xf0000 |
| 3758 | #define DxF0x58_DeviceType_OFFSET 20 |
| 3759 | #define DxF0x58_DeviceType_WIDTH 4 |
| 3760 | #define DxF0x58_DeviceType_MASK 0xf00000 |
| 3761 | #define DxF0x58_SlotImplemented_OFFSET 24 |
| 3762 | #define DxF0x58_SlotImplemented_WIDTH 1 |
| 3763 | #define DxF0x58_SlotImplemented_MASK 0x1000000 |
| 3764 | #define DxF0x58_IntMessageNum_OFFSET 25 |
| 3765 | #define DxF0x58_IntMessageNum_WIDTH 5 |
| 3766 | #define DxF0x58_IntMessageNum_MASK 0x3e000000 |
| 3767 | #define DxF0x58_Reserved_31_30_OFFSET 30 |
| 3768 | #define DxF0x58_Reserved_31_30_WIDTH 2 |
| 3769 | #define DxF0x58_Reserved_31_30_MASK 0xc0000000 |
| 3770 | |
| 3771 | /// DxF0x58 |
| 3772 | typedef union { |
| 3773 | struct { ///< |
| 3774 | UINT32 CapID:8 ; ///< |
| 3775 | UINT32 NextPtr:8 ; ///< |
| 3776 | UINT32 Version:4 ; ///< |
| 3777 | UINT32 DeviceType:4 ; ///< |
| 3778 | UINT32 SlotImplemented:1 ; ///< |
| 3779 | UINT32 IntMessageNum:5 ; ///< |
| 3780 | UINT32 Reserved_31_30:2 ; ///< |
| 3781 | } Field; ///< |
| 3782 | UINT32 Value; ///< |
| 3783 | } DxF0x58_STRUCT; |
| 3784 | |
| 3785 | // **** DxF0x5C Register Definition **** |
| 3786 | // Address |
| 3787 | #define DxF0x5C_ADDRESS 0x5c |
| 3788 | |
| 3789 | // Type |
| 3790 | #define DxF0x5C_TYPE TYPE_D4F0 |
| 3791 | // Field Data |
| 3792 | #define DxF0x5C_MaxPayloadSupport_OFFSET 0 |
| 3793 | #define DxF0x5C_MaxPayloadSupport_WIDTH 3 |
| 3794 | #define DxF0x5C_MaxPayloadSupport_MASK 0x7 |
| 3795 | #define DxF0x5C_PhantomFunc_OFFSET 3 |
| 3796 | #define DxF0x5C_PhantomFunc_WIDTH 2 |
| 3797 | #define DxF0x5C_PhantomFunc_MASK 0x18 |
| 3798 | #define DxF0x5C_ExtendedTag_OFFSET 5 |
| 3799 | #define DxF0x5C_ExtendedTag_WIDTH 1 |
| 3800 | #define DxF0x5C_ExtendedTag_MASK 0x20 |
| 3801 | #define DxF0x5C_L0SAcceptableLatency_OFFSET 6 |
| 3802 | #define DxF0x5C_L0SAcceptableLatency_WIDTH 3 |
| 3803 | #define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0 |
| 3804 | #define DxF0x5C_L1AcceptableLatency_OFFSET 9 |
| 3805 | #define DxF0x5C_L1AcceptableLatency_WIDTH 3 |
| 3806 | #define DxF0x5C_L1AcceptableLatency_MASK 0xe00 |
| 3807 | #define DxF0x5C_Reserved_14_12_OFFSET 12 |
| 3808 | #define DxF0x5C_Reserved_14_12_WIDTH 3 |
| 3809 | #define DxF0x5C_Reserved_14_12_MASK 0x7000 |
| 3810 | #define DxF0x5C_RoleBasedErrReporting_OFFSET 15 |
| 3811 | #define DxF0x5C_RoleBasedErrReporting_WIDTH 1 |
| 3812 | #define DxF0x5C_RoleBasedErrReporting_MASK 0x8000 |
| 3813 | #define DxF0x5C_Reserved_17_16_OFFSET 16 |
| 3814 | #define DxF0x5C_Reserved_17_16_WIDTH 2 |
| 3815 | #define DxF0x5C_Reserved_17_16_MASK 0x30000 |
| 3816 | #define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18 |
| 3817 | #define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8 |
| 3818 | #define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000 |
| 3819 | #define DxF0x5C_CapturedSlotPowerScale_OFFSET 26 |
| 3820 | #define DxF0x5C_CapturedSlotPowerScale_WIDTH 2 |
| 3821 | #define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000 |
| 3822 | #define DxF0x5C_FlrCapable_OFFSET 28 |
| 3823 | #define DxF0x5C_FlrCapable_WIDTH 1 |
| 3824 | #define DxF0x5C_FlrCapable_MASK 0x10000000 |
| 3825 | #define DxF0x5C_Reserved_31_29_OFFSET 29 |
| 3826 | #define DxF0x5C_Reserved_31_29_WIDTH 3 |
| 3827 | #define DxF0x5C_Reserved_31_29_MASK 0xe0000000 |
| 3828 | |
| 3829 | /// DxF0x5C |
| 3830 | typedef union { |
| 3831 | struct { ///< |
| 3832 | UINT32 MaxPayloadSupport:3 ; ///< |
| 3833 | UINT32 PhantomFunc:2 ; ///< |
| 3834 | UINT32 ExtendedTag:1 ; ///< |
| 3835 | UINT32 L0SAcceptableLatency:3 ; ///< |
| 3836 | UINT32 L1AcceptableLatency:3 ; ///< |
| 3837 | UINT32 Reserved_14_12:3 ; ///< |
| 3838 | UINT32 RoleBasedErrReporting:1 ; ///< |
| 3839 | UINT32 Reserved_17_16:2 ; ///< |
| 3840 | UINT32 CapturedSlotPowerLimit:8 ; ///< |
| 3841 | UINT32 CapturedSlotPowerScale:2 ; ///< |
| 3842 | UINT32 FlrCapable:1 ; ///< |
| 3843 | UINT32 Reserved_31_29:3 ; ///< |
| 3844 | } Field; ///< |
| 3845 | UINT32 Value; ///< |
| 3846 | } DxF0x5C_STRUCT; |
| 3847 | |
| 3848 | // **** DxF0x60 Register Definition **** |
| 3849 | // Address |
| 3850 | #define DxF0x60_ADDRESS 0x60 |
| 3851 | |
| 3852 | // Type |
| 3853 | #define DxF0x60_TYPE TYPE_D4F0 |
| 3854 | // Field Data |
| 3855 | #define DxF0x60_CorrErrEn_OFFSET 0 |
| 3856 | #define DxF0x60_CorrErrEn_WIDTH 1 |
| 3857 | #define DxF0x60_CorrErrEn_MASK 0x1 |
| 3858 | #define DxF0x60_NonFatalErrEn_OFFSET 1 |
| 3859 | #define DxF0x60_NonFatalErrEn_WIDTH 1 |
| 3860 | #define DxF0x60_NonFatalErrEn_MASK 0x2 |
| 3861 | #define DxF0x60_FatalErrEn_OFFSET 2 |
| 3862 | #define DxF0x60_FatalErrEn_WIDTH 1 |
| 3863 | #define DxF0x60_FatalErrEn_MASK 0x4 |
| 3864 | #define DxF0x60_UsrReportEn_OFFSET 3 |
| 3865 | #define DxF0x60_UsrReportEn_WIDTH 1 |
| 3866 | #define DxF0x60_UsrReportEn_MASK 0x8 |
| 3867 | #define DxF0x60_RelaxedOrdEn_OFFSET 4 |
| 3868 | #define DxF0x60_RelaxedOrdEn_WIDTH 1 |
| 3869 | #define DxF0x60_RelaxedOrdEn_MASK 0x10 |
| 3870 | #define DxF0x60_MaxPayloadSize_OFFSET 5 |
| 3871 | #define DxF0x60_MaxPayloadSize_WIDTH 3 |
| 3872 | #define DxF0x60_MaxPayloadSize_MASK 0xe0 |
| 3873 | #define DxF0x60_ExtendedTagEn_OFFSET 8 |
| 3874 | #define DxF0x60_ExtendedTagEn_WIDTH 1 |
| 3875 | #define DxF0x60_ExtendedTagEn_MASK 0x100 |
| 3876 | #define DxF0x60_PhantomFuncEn_OFFSET 9 |
| 3877 | #define DxF0x60_PhantomFuncEn_WIDTH 1 |
| 3878 | #define DxF0x60_PhantomFuncEn_MASK 0x200 |
| 3879 | #define DxF0x60_AuxPowerPmEn_OFFSET 10 |
| 3880 | #define DxF0x60_AuxPowerPmEn_WIDTH 1 |
| 3881 | #define DxF0x60_AuxPowerPmEn_MASK 0x400 |
| 3882 | #define DxF0x60_NoSnoopEnable_OFFSET 11 |
| 3883 | #define DxF0x60_NoSnoopEnable_WIDTH 1 |
| 3884 | #define DxF0x60_NoSnoopEnable_MASK 0x800 |
| 3885 | #define DxF0x60_MaxRequestSize_OFFSET 12 |
| 3886 | #define DxF0x60_MaxRequestSize_WIDTH 3 |
| 3887 | #define DxF0x60_MaxRequestSize_MASK 0x7000 |
| 3888 | #define DxF0x60_BridgeCfgRetryEn_OFFSET 15 |
| 3889 | #define DxF0x60_BridgeCfgRetryEn_WIDTH 1 |
| 3890 | #define DxF0x60_BridgeCfgRetryEn_MASK 0x8000 |
| 3891 | #define DxF0x60_CorrErr_OFFSET 16 |
| 3892 | #define DxF0x60_CorrErr_WIDTH 1 |
| 3893 | #define DxF0x60_CorrErr_MASK 0x10000 |
| 3894 | #define DxF0x60_NonFatalErr_OFFSET 17 |
| 3895 | #define DxF0x60_NonFatalErr_WIDTH 1 |
| 3896 | #define DxF0x60_NonFatalErr_MASK 0x20000 |
| 3897 | #define DxF0x60_FatalErr_OFFSET 18 |
| 3898 | #define DxF0x60_FatalErr_WIDTH 1 |
| 3899 | #define DxF0x60_FatalErr_MASK 0x40000 |
| 3900 | #define DxF0x60_UsrDetected_OFFSET 19 |
| 3901 | #define DxF0x60_UsrDetected_WIDTH 1 |
| 3902 | #define DxF0x60_UsrDetected_MASK 0x80000 |
| 3903 | #define DxF0x60_AuxPwr_OFFSET 20 |
| 3904 | #define DxF0x60_AuxPwr_WIDTH 1 |
| 3905 | #define DxF0x60_AuxPwr_MASK 0x100000 |
| 3906 | #define DxF0x60_TransactionsPending_OFFSET 21 |
| 3907 | #define DxF0x60_TransactionsPending_WIDTH 1 |
| 3908 | #define DxF0x60_TransactionsPending_MASK 0x200000 |
| 3909 | #define DxF0x60_Reserved_31_22_OFFSET 22 |
| 3910 | #define DxF0x60_Reserved_31_22_WIDTH 10 |
| 3911 | #define DxF0x60_Reserved_31_22_MASK 0xffc00000 |
| 3912 | |
| 3913 | /// DxF0x60 |
| 3914 | typedef union { |
| 3915 | struct { ///< |
| 3916 | UINT32 CorrErrEn:1 ; ///< |
| 3917 | UINT32 NonFatalErrEn:1 ; ///< |
| 3918 | UINT32 FatalErrEn:1 ; ///< |
| 3919 | UINT32 UsrReportEn:1 ; ///< |
| 3920 | UINT32 RelaxedOrdEn:1 ; ///< |
| 3921 | UINT32 MaxPayloadSize:3 ; ///< |
| 3922 | UINT32 ExtendedTagEn:1 ; ///< |
| 3923 | UINT32 PhantomFuncEn:1 ; ///< |
| 3924 | UINT32 AuxPowerPmEn:1 ; ///< |
| 3925 | UINT32 NoSnoopEnable:1 ; ///< |
| 3926 | UINT32 MaxRequestSize:3 ; ///< |
| 3927 | UINT32 BridgeCfgRetryEn:1 ; ///< |
| 3928 | UINT32 CorrErr:1 ; ///< |
| 3929 | UINT32 NonFatalErr:1 ; ///< |
| 3930 | UINT32 FatalErr:1 ; ///< |
| 3931 | UINT32 UsrDetected:1 ; ///< |
| 3932 | UINT32 AuxPwr:1 ; ///< |
| 3933 | UINT32 TransactionsPending:1 ; ///< |
| 3934 | UINT32 Reserved_31_22:10; ///< |
| 3935 | } Field; ///< |
| 3936 | UINT32 Value; ///< |
| 3937 | } DxF0x60_STRUCT; |
| 3938 | |
| 3939 | // **** DxF0x64 Register Definition **** |
| 3940 | // Address |
| 3941 | #define DxF0x64_ADDRESS 0x64 |
| 3942 | |
| 3943 | // Type |
| 3944 | #define DxF0x64_TYPE TYPE_D4F0 |
| 3945 | // Field Data |
| 3946 | #define DxF0x64_LinkSpeed_OFFSET 0 |
| 3947 | #define DxF0x64_LinkSpeed_WIDTH 4 |
| 3948 | #define DxF0x64_LinkSpeed_MASK 0xf |
| 3949 | #define DxF0x64_LinkWidth_OFFSET 4 |
| 3950 | #define DxF0x64_LinkWidth_WIDTH 6 |
| 3951 | #define DxF0x64_LinkWidth_MASK 0x3f0 |
| 3952 | #define DxF0x64_PMSupport_OFFSET 10 |
| 3953 | #define DxF0x64_PMSupport_WIDTH 2 |
| 3954 | #define DxF0x64_PMSupport_MASK 0xc00 |
| 3955 | #define DxF0x64_L0sExitLatency_OFFSET 12 |
| 3956 | #define DxF0x64_L0sExitLatency_WIDTH 3 |
| 3957 | #define DxF0x64_L0sExitLatency_MASK 0x7000 |
| 3958 | #define DxF0x64_L1ExitLatency_OFFSET 15 |
| 3959 | #define DxF0x64_L1ExitLatency_WIDTH 3 |
| 3960 | #define DxF0x64_L1ExitLatency_MASK 0x38000 |
| 3961 | #define DxF0x64_ClockPowerManagement_OFFSET 18 |
| 3962 | #define DxF0x64_ClockPowerManagement_WIDTH 1 |
| 3963 | #define DxF0x64_ClockPowerManagement_MASK 0x40000 |
| 3964 | #define DxF0x64_Reserved_19_19_OFFSET 19 |
| 3965 | #define DxF0x64_Reserved_19_19_WIDTH 1 |
| 3966 | #define DxF0x64_Reserved_19_19_MASK 0x80000 |
| 3967 | #define DxF0x64_DlActiveReportingCapable_OFFSET 20 |
| 3968 | #define DxF0x64_DlActiveReportingCapable_WIDTH 1 |
| 3969 | #define DxF0x64_DlActiveReportingCapable_MASK 0x100000 |
| 3970 | #define DxF0x64_LinkBWNotificationCap_OFFSET 21 |
| 3971 | #define DxF0x64_LinkBWNotificationCap_WIDTH 1 |
| 3972 | #define DxF0x64_LinkBWNotificationCap_MASK 0x200000 |
| 3973 | #define DxF0x64_Reserved_23_22_OFFSET 22 |
| 3974 | #define DxF0x64_Reserved_23_22_WIDTH 2 |
| 3975 | #define DxF0x64_Reserved_23_22_MASK 0xc00000 |
| 3976 | #define DxF0x64_PortNumber_OFFSET 24 |
| 3977 | #define DxF0x64_PortNumber_WIDTH 8 |
| 3978 | #define DxF0x64_PortNumber_MASK 0xff000000 |
| 3979 | |
| 3980 | /// DxF0x64 |
| 3981 | typedef union { |
| 3982 | struct { ///< |
| 3983 | UINT32 LinkSpeed:4 ; ///< |
| 3984 | UINT32 LinkWidth:6 ; ///< |
| 3985 | UINT32 PMSupport:2 ; ///< |
| 3986 | UINT32 L0sExitLatency:3 ; ///< |
| 3987 | UINT32 L1ExitLatency:3 ; ///< |
| 3988 | UINT32 ClockPowerManagement:1 ; ///< |
| 3989 | UINT32 Reserved_19_19:1 ; ///< |
| 3990 | UINT32 DlActiveReportingCapable:1 ; ///< |
| 3991 | UINT32 LinkBWNotificationCap:1 ; ///< |
| 3992 | UINT32 Reserved_23_22:2 ; ///< |
| 3993 | UINT32 PortNumber:8 ; ///< |
| 3994 | } Field; ///< |
| 3995 | UINT32 Value; ///< |
| 3996 | } DxF0x64_STRUCT; |
| 3997 | |
| 3998 | // **** DxF0x68 Register Definition **** |
| 3999 | // Address |
| 4000 | #define DxF0x68_ADDRESS 0x68 |
| 4001 | |
| 4002 | // Type |
| 4003 | #define DxF0x68_TYPE TYPE_D4F0 |
| 4004 | // Field Data |
| 4005 | #define DxF0x68_PmControl_OFFSET 0 |
| 4006 | #define DxF0x68_PmControl_WIDTH 2 |
| 4007 | #define DxF0x68_PmControl_MASK 0x3 |
| 4008 | #define DxF0x68_Reserved_2_2_OFFSET 2 |
| 4009 | #define DxF0x68_Reserved_2_2_WIDTH 1 |
| 4010 | #define DxF0x68_Reserved_2_2_MASK 0x4 |
| 4011 | #define DxF0x68_ReadCplBoundary_OFFSET 3 |
| 4012 | #define DxF0x68_ReadCplBoundary_WIDTH 1 |
| 4013 | #define DxF0x68_ReadCplBoundary_MASK 0x8 |
| 4014 | #define DxF0x68_LinkDis_OFFSET 4 |
| 4015 | #define DxF0x68_LinkDis_WIDTH 1 |
| 4016 | #define DxF0x68_LinkDis_MASK 0x10 |
| 4017 | #define DxF0x68_RetrainLink_OFFSET 5 |
| 4018 | #define DxF0x68_RetrainLink_WIDTH 1 |
| 4019 | #define DxF0x68_RetrainLink_MASK 0x20 |
| 4020 | #define DxF0x68_CommonClockCfg_OFFSET 6 |
| 4021 | #define DxF0x68_CommonClockCfg_WIDTH 1 |
| 4022 | #define DxF0x68_CommonClockCfg_MASK 0x40 |
| 4023 | #define DxF0x68_ExtendedSync_OFFSET 7 |
| 4024 | #define DxF0x68_ExtendedSync_WIDTH 1 |
| 4025 | #define DxF0x68_ExtendedSync_MASK 0x80 |
| 4026 | #define DxF0x68_ClockPowerManagementEn_OFFSET 8 |
| 4027 | #define DxF0x68_ClockPowerManagementEn_WIDTH 1 |
| 4028 | #define DxF0x68_ClockPowerManagementEn_MASK 0x100 |
| 4029 | #define DxF0x68_HWAutonomousWidthDisable_OFFSET 9 |
| 4030 | #define DxF0x68_HWAutonomousWidthDisable_WIDTH 1 |
| 4031 | #define DxF0x68_HWAutonomousWidthDisable_MASK 0x200 |
| 4032 | #define DxF0x68_LinkBWManagementEn_OFFSET 10 |
| 4033 | #define DxF0x68_LinkBWManagementEn_WIDTH 1 |
| 4034 | #define DxF0x68_LinkBWManagementEn_MASK 0x400 |
| 4035 | #define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11 |
| 4036 | #define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1 |
| 4037 | #define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800 |
| 4038 | #define DxF0x68_Reserved_15_12_OFFSET 12 |
| 4039 | #define DxF0x68_Reserved_15_12_WIDTH 4 |
| 4040 | #define DxF0x68_Reserved_15_12_MASK 0xf000 |
| 4041 | #define DxF0x68_LinkSpeed_OFFSET 16 |
| 4042 | #define DxF0x68_LinkSpeed_WIDTH 4 |
| 4043 | #define DxF0x68_LinkSpeed_MASK 0xf0000 |
| 4044 | #define DxF0x68_NegotiatedLinkWidth_OFFSET 20 |
| 4045 | #define DxF0x68_NegotiatedLinkWidth_WIDTH 6 |
| 4046 | #define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000 |
| 4047 | #define DxF0x68_Reserved_26_26_OFFSET 26 |
| 4048 | #define DxF0x68_Reserved_26_26_WIDTH 1 |
| 4049 | #define DxF0x68_Reserved_26_26_MASK 0x4000000 |
| 4050 | #define DxF0x68_LinkTraining_OFFSET 27 |
| 4051 | #define DxF0x68_LinkTraining_WIDTH 1 |
| 4052 | #define DxF0x68_LinkTraining_MASK 0x8000000 |
| 4053 | #define DxF0x68_SlotClockCfg_OFFSET 28 |
| 4054 | #define DxF0x68_SlotClockCfg_WIDTH 1 |
| 4055 | #define DxF0x68_SlotClockCfg_MASK 0x10000000 |
| 4056 | #define DxF0x68_DlActive_OFFSET 29 |
| 4057 | #define DxF0x68_DlActive_WIDTH 1 |
| 4058 | #define DxF0x68_DlActive_MASK 0x20000000 |
| 4059 | #define DxF0x68_LinkBWManagementStatus_OFFSET 30 |
| 4060 | #define DxF0x68_LinkBWManagementStatus_WIDTH 1 |
| 4061 | #define DxF0x68_LinkBWManagementStatus_MASK 0x40000000 |
| 4062 | #define DxF0x68_LinkAutonomousBWStatus_OFFSET 31 |
| 4063 | #define DxF0x68_LinkAutonomousBWStatus_WIDTH 1 |
| 4064 | #define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000 |
| 4065 | |
| 4066 | /// DxF0x68 |
| 4067 | typedef union { |
| 4068 | struct { ///< |
| 4069 | UINT32 PmControl:2 ; ///< |
| 4070 | UINT32 Reserved_2_2:1 ; ///< |
| 4071 | UINT32 ReadCplBoundary:1 ; ///< |
| 4072 | UINT32 LinkDis:1 ; ///< |
| 4073 | UINT32 RetrainLink:1 ; ///< |
| 4074 | UINT32 CommonClockCfg:1 ; ///< |
| 4075 | UINT32 ExtendedSync:1 ; ///< |
| 4076 | UINT32 ClockPowerManagementEn:1 ; ///< |
| 4077 | UINT32 HWAutonomousWidthDisable:1 ; ///< |
| 4078 | UINT32 LinkBWManagementEn:1 ; ///< |
| 4079 | UINT32 LinkAutonomousBWIntEn:1 ; ///< |
| 4080 | UINT32 Reserved_15_12:4 ; ///< |
| 4081 | UINT32 LinkSpeed:4 ; ///< |
| 4082 | UINT32 NegotiatedLinkWidth:6 ; ///< |
| 4083 | UINT32 Reserved_26_26:1 ; ///< |
| 4084 | UINT32 LinkTraining:1 ; ///< |
| 4085 | UINT32 SlotClockCfg:1 ; ///< |
| 4086 | UINT32 DlActive:1 ; ///< |
| 4087 | UINT32 LinkBWManagementStatus:1 ; ///< |
| 4088 | UINT32 LinkAutonomousBWStatus:1 ; ///< |
| 4089 | } Field; ///< |
| 4090 | UINT32 Value; ///< |
| 4091 | } DxF0x68_STRUCT; |
| 4092 | |
| 4093 | // **** DxF0x6C Register Definition **** |
| 4094 | // Address |
| 4095 | #define DxF0x6C_ADDRESS 0x6c |
| 4096 | |
| 4097 | // Type |
| 4098 | #define DxF0x6C_TYPE TYPE_D4F0 |
| 4099 | // Field Data |
| 4100 | #define DxF0x6C_AttnButtonPresent_OFFSET 0 |
| 4101 | #define DxF0x6C_AttnButtonPresent_WIDTH 1 |
| 4102 | #define DxF0x6C_AttnButtonPresent_MASK 0x1 |
| 4103 | #define DxF0x6C_PwrControllerPresent_OFFSET 1 |
| 4104 | #define DxF0x6C_PwrControllerPresent_WIDTH 1 |
| 4105 | #define DxF0x6C_PwrControllerPresent_MASK 0x2 |
| 4106 | #define DxF0x6C_MrlSensorPresent_OFFSET 2 |
| 4107 | #define DxF0x6C_MrlSensorPresent_WIDTH 1 |
| 4108 | #define DxF0x6C_MrlSensorPresent_MASK 0x4 |
| 4109 | #define DxF0x6C_AttnIndicatorPresent_OFFSET 3 |
| 4110 | #define DxF0x6C_AttnIndicatorPresent_WIDTH 1 |
| 4111 | #define DxF0x6C_AttnIndicatorPresent_MASK 0x8 |
| 4112 | #define DxF0x6C_PwrIndicatorPresent_OFFSET 4 |
| 4113 | #define DxF0x6C_PwrIndicatorPresent_WIDTH 1 |
| 4114 | #define DxF0x6C_PwrIndicatorPresent_MASK 0x10 |
| 4115 | #define DxF0x6C_HotplugSurprise_OFFSET 5 |
| 4116 | #define DxF0x6C_HotplugSurprise_WIDTH 1 |
| 4117 | #define DxF0x6C_HotplugSurprise_MASK 0x20 |
| 4118 | #define DxF0x6C_HotplugCapable_OFFSET 6 |
| 4119 | #define DxF0x6C_HotplugCapable_WIDTH 1 |
| 4120 | #define DxF0x6C_HotplugCapable_MASK 0x40 |
| 4121 | #define DxF0x6C_SlotPwrLimitValue_OFFSET 7 |
| 4122 | #define DxF0x6C_SlotPwrLimitValue_WIDTH 8 |
| 4123 | #define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80 |
| 4124 | #define DxF0x6C_SlotPwrLimitScale_OFFSET 15 |
| 4125 | #define DxF0x6C_SlotPwrLimitScale_WIDTH 2 |
| 4126 | #define DxF0x6C_SlotPwrLimitScale_MASK 0x18000 |
| 4127 | #define DxF0x6C_ElecMechIlPresent_OFFSET 17 |
| 4128 | #define DxF0x6C_ElecMechIlPresent_WIDTH 1 |
| 4129 | #define DxF0x6C_ElecMechIlPresent_MASK 0x20000 |
| 4130 | #define DxF0x6C_NoCmdCplSupport_OFFSET 18 |
| 4131 | #define DxF0x6C_NoCmdCplSupport_WIDTH 1 |
| 4132 | #define DxF0x6C_NoCmdCplSupport_MASK 0x40000 |
| 4133 | #define DxF0x6C_PhysicalSlotNumber_OFFSET 19 |
| 4134 | #define DxF0x6C_PhysicalSlotNumber_WIDTH 13 |
| 4135 | #define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000 |
| 4136 | |
| 4137 | /// DxF0x6C |
| 4138 | typedef union { |
| 4139 | struct { ///< |
| 4140 | UINT32 AttnButtonPresent:1 ; ///< |
| 4141 | UINT32 PwrControllerPresent:1 ; ///< |
| 4142 | UINT32 MrlSensorPresent:1 ; ///< |
| 4143 | UINT32 AttnIndicatorPresent:1 ; ///< |
| 4144 | UINT32 PwrIndicatorPresent:1 ; ///< |
| 4145 | UINT32 HotplugSurprise:1 ; ///< |
| 4146 | UINT32 HotplugCapable:1 ; ///< |
| 4147 | UINT32 SlotPwrLimitValue:8 ; ///< |
| 4148 | UINT32 SlotPwrLimitScale:2 ; ///< |
| 4149 | UINT32 ElecMechIlPresent:1 ; ///< |
| 4150 | UINT32 NoCmdCplSupport:1 ; ///< |
| 4151 | UINT32 PhysicalSlotNumber:13; ///< |
| 4152 | } Field; ///< |
| 4153 | UINT32 Value; ///< |
| 4154 | } DxF0x6C_STRUCT; |
| 4155 | |
| 4156 | // **** DxF0x70 Register Definition **** |
| 4157 | // Address |
| 4158 | #define DxF0x70_ADDRESS 0x70 |
| 4159 | |
| 4160 | // Type |
| 4161 | #define DxF0x70_TYPE TYPE_D4F0 |
| 4162 | // Field Data |
| 4163 | #define DxF0x70_AttnButtonPressedEn_OFFSET 0 |
| 4164 | #define DxF0x70_AttnButtonPressedEn_WIDTH 1 |
| 4165 | #define DxF0x70_AttnButtonPressedEn_MASK 0x1 |
| 4166 | #define DxF0x70_PwrFaultDetectedEn_OFFSET 1 |
| 4167 | #define DxF0x70_PwrFaultDetectedEn_WIDTH 1 |
| 4168 | #define DxF0x70_PwrFaultDetectedEn_MASK 0x2 |
| 4169 | #define DxF0x70_MrlSensorChangedEn_OFFSET 2 |
| 4170 | #define DxF0x70_MrlSensorChangedEn_WIDTH 1 |
| 4171 | #define DxF0x70_MrlSensorChangedEn_MASK 0x4 |
| 4172 | #define DxF0x70_PresenceDetectChangedEn_OFFSET 3 |
| 4173 | #define DxF0x70_PresenceDetectChangedEn_WIDTH 1 |
| 4174 | #define DxF0x70_PresenceDetectChangedEn_MASK 0x8 |
| 4175 | #define DxF0x70_CmdCplIntrEn_OFFSET 4 |
| 4176 | #define DxF0x70_CmdCplIntrEn_WIDTH 1 |
| 4177 | #define DxF0x70_CmdCplIntrEn_MASK 0x10 |
| 4178 | #define DxF0x70_HotplugIntrEn_OFFSET 5 |
| 4179 | #define DxF0x70_HotplugIntrEn_WIDTH 1 |
| 4180 | #define DxF0x70_HotplugIntrEn_MASK 0x20 |
| 4181 | #define DxF0x70_AttnIndicatorControl_OFFSET 6 |
| 4182 | #define DxF0x70_AttnIndicatorControl_WIDTH 2 |
| 4183 | #define DxF0x70_AttnIndicatorControl_MASK 0xc0 |
| 4184 | #define DxF0x70_PwrIndicatorCntl_OFFSET 8 |
| 4185 | #define DxF0x70_PwrIndicatorCntl_WIDTH 2 |
| 4186 | #define DxF0x70_PwrIndicatorCntl_MASK 0x300 |
| 4187 | #define DxF0x70_PwrControllerCntl_OFFSET 10 |
| 4188 | #define DxF0x70_PwrControllerCntl_WIDTH 1 |
| 4189 | #define DxF0x70_PwrControllerCntl_MASK 0x400 |
| 4190 | #define DxF0x70_ElecMechIlCntl_OFFSET 11 |
| 4191 | #define DxF0x70_ElecMechIlCntl_WIDTH 1 |
| 4192 | #define DxF0x70_ElecMechIlCntl_MASK 0x800 |
| 4193 | #define DxF0x70_DlStateChangedEn_OFFSET 12 |
| 4194 | #define DxF0x70_DlStateChangedEn_WIDTH 1 |
| 4195 | #define DxF0x70_DlStateChangedEn_MASK 0x1000 |
| 4196 | #define DxF0x70_Reserved_15_13_OFFSET 13 |
| 4197 | #define DxF0x70_Reserved_15_13_WIDTH 3 |
| 4198 | #define DxF0x70_Reserved_15_13_MASK 0xe000 |
| 4199 | #define DxF0x70_AttnButtonPressed_OFFSET 16 |
| 4200 | #define DxF0x70_AttnButtonPressed_WIDTH 1 |
| 4201 | #define DxF0x70_AttnButtonPressed_MASK 0x10000 |
| 4202 | #define DxF0x70_PwrFaultDetected_OFFSET 17 |
| 4203 | #define DxF0x70_PwrFaultDetected_WIDTH 1 |
| 4204 | #define DxF0x70_PwrFaultDetected_MASK 0x20000 |
| 4205 | #define DxF0x70_MrlSensorChanged_OFFSET 18 |
| 4206 | #define DxF0x70_MrlSensorChanged_WIDTH 1 |
| 4207 | #define DxF0x70_MrlSensorChanged_MASK 0x40000 |
| 4208 | #define DxF0x70_PresenceDetectChanged_OFFSET 19 |
| 4209 | #define DxF0x70_PresenceDetectChanged_WIDTH 1 |
| 4210 | #define DxF0x70_PresenceDetectChanged_MASK 0x80000 |
| 4211 | #define DxF0x70_CmdCpl_OFFSET 20 |
| 4212 | #define DxF0x70_CmdCpl_WIDTH 1 |
| 4213 | #define DxF0x70_CmdCpl_MASK 0x100000 |
| 4214 | #define DxF0x70_MrlSensorState_OFFSET 21 |
| 4215 | #define DxF0x70_MrlSensorState_WIDTH 1 |
| 4216 | #define DxF0x70_MrlSensorState_MASK 0x200000 |
| 4217 | #define DxF0x70_PresenceDetectState_OFFSET 22 |
| 4218 | #define DxF0x70_PresenceDetectState_WIDTH 1 |
| 4219 | #define DxF0x70_PresenceDetectState_MASK 0x400000 |
| 4220 | #define DxF0x70_ElecMechIlSts_OFFSET 23 |
| 4221 | #define DxF0x70_ElecMechIlSts_WIDTH 1 |
| 4222 | #define DxF0x70_ElecMechIlSts_MASK 0x800000 |
| 4223 | #define DxF0x70_DlStateChanged_OFFSET 24 |
| 4224 | #define DxF0x70_DlStateChanged_WIDTH 1 |
| 4225 | #define DxF0x70_DlStateChanged_MASK 0x1000000 |
| 4226 | #define DxF0x70_Reserved_31_25_OFFSET 25 |
| 4227 | #define DxF0x70_Reserved_31_25_WIDTH 7 |
| 4228 | #define DxF0x70_Reserved_31_25_MASK 0xfe000000 |
| 4229 | |
| 4230 | /// DxF0x70 |
| 4231 | typedef union { |
| 4232 | struct { ///< |
| 4233 | UINT32 AttnButtonPressedEn:1 ; ///< |
| 4234 | UINT32 PwrFaultDetectedEn:1 ; ///< |
| 4235 | UINT32 MrlSensorChangedEn:1 ; ///< |
| 4236 | UINT32 PresenceDetectChangedEn:1 ; ///< |
| 4237 | UINT32 CmdCplIntrEn:1 ; ///< |
| 4238 | UINT32 HotplugIntrEn:1 ; ///< |
| 4239 | UINT32 AttnIndicatorControl:2 ; ///< |
| 4240 | UINT32 PwrIndicatorCntl:2 ; ///< |
| 4241 | UINT32 PwrControllerCntl:1 ; ///< |
| 4242 | UINT32 ElecMechIlCntl:1 ; ///< |
| 4243 | UINT32 DlStateChangedEn:1 ; ///< |
| 4244 | UINT32 Reserved_15_13:3 ; ///< |
| 4245 | UINT32 AttnButtonPressed:1 ; ///< |
| 4246 | UINT32 PwrFaultDetected:1 ; ///< |
| 4247 | UINT32 MrlSensorChanged:1 ; ///< |
| 4248 | UINT32 PresenceDetectChanged:1 ; ///< |
| 4249 | UINT32 CmdCpl:1 ; ///< |
| 4250 | UINT32 MrlSensorState:1 ; ///< |
| 4251 | UINT32 PresenceDetectState:1 ; ///< |
| 4252 | UINT32 ElecMechIlSts:1 ; ///< |
| 4253 | UINT32 DlStateChanged:1 ; ///< |
| 4254 | UINT32 Reserved_31_25:7 ; ///< |
| 4255 | } Field; ///< |
| 4256 | UINT32 Value; ///< |
| 4257 | } DxF0x70_STRUCT; |
| 4258 | |
| 4259 | // **** DxF0x74 Register Definition **** |
| 4260 | // Address |
| 4261 | #define DxF0x74_ADDRESS 0x74 |
| 4262 | |
| 4263 | // Type |
| 4264 | #define DxF0x74_TYPE TYPE_D4F0 |
| 4265 | // Field Data |
| 4266 | #define DxF0x74_SerrOnCorrErrEn_OFFSET 0 |
| 4267 | #define DxF0x74_SerrOnCorrErrEn_WIDTH 1 |
| 4268 | #define DxF0x74_SerrOnCorrErrEn_MASK 0x1 |
| 4269 | #define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1 |
| 4270 | #define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1 |
| 4271 | #define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2 |
| 4272 | #define DxF0x74_SerrOnFatalErrEn_OFFSET 2 |
| 4273 | #define DxF0x74_SerrOnFatalErrEn_WIDTH 1 |
| 4274 | #define DxF0x74_SerrOnFatalErrEn_MASK 0x4 |
| 4275 | #define DxF0x74_PmIntEn_OFFSET 3 |
| 4276 | #define DxF0x74_PmIntEn_WIDTH 1 |
| 4277 | #define DxF0x74_PmIntEn_MASK 0x8 |
| 4278 | #define DxF0x74_CrsSoftVisibilityEn_OFFSET 4 |
| 4279 | #define DxF0x74_CrsSoftVisibilityEn_WIDTH 1 |
| 4280 | #define DxF0x74_CrsSoftVisibilityEn_MASK 0x10 |
| 4281 | #define DxF0x74_Reserved_15_5_OFFSET 5 |
| 4282 | #define DxF0x74_Reserved_15_5_WIDTH 11 |
| 4283 | #define DxF0x74_Reserved_15_5_MASK 0xffe0 |
| 4284 | #define DxF0x74_CrsSoftVisibility_OFFSET 16 |
| 4285 | #define DxF0x74_CrsSoftVisibility_WIDTH 1 |
| 4286 | #define DxF0x74_CrsSoftVisibility_MASK 0x10000 |
| 4287 | #define DxF0x74_Reserved_31_17_OFFSET 17 |
| 4288 | #define DxF0x74_Reserved_31_17_WIDTH 15 |
| 4289 | #define DxF0x74_Reserved_31_17_MASK 0xfffe0000 |
| 4290 | |
| 4291 | /// DxF0x74 |
| 4292 | typedef union { |
| 4293 | struct { ///< |
| 4294 | UINT32 SerrOnCorrErrEn:1 ; ///< |
| 4295 | UINT32 SerrOnNonFatalErrEn:1 ; ///< |
| 4296 | UINT32 SerrOnFatalErrEn:1 ; ///< |
| 4297 | UINT32 PmIntEn:1 ; ///< |
| 4298 | UINT32 CrsSoftVisibilityEn:1 ; ///< |
| 4299 | UINT32 Reserved_15_5:11; ///< |
| 4300 | UINT32 CrsSoftVisibility:1 ; ///< |
| 4301 | UINT32 Reserved_31_17:15; ///< |
| 4302 | } Field; ///< |
| 4303 | UINT32 Value; ///< |
| 4304 | } DxF0x74_STRUCT; |
| 4305 | |
| 4306 | // **** DxF0x78 Register Definition **** |
| 4307 | // Address |
| 4308 | #define DxF0x78_ADDRESS 0x78 |
| 4309 | |
| 4310 | // Type |
| 4311 | #define DxF0x78_TYPE TYPE_D4F0 |
| 4312 | // Field Data |
| 4313 | #define DxF0x78_PmeRequestorId_OFFSET 0 |
| 4314 | #define DxF0x78_PmeRequestorId_WIDTH 16 |
| 4315 | #define DxF0x78_PmeRequestorId_MASK 0xffff |
| 4316 | #define DxF0x78_PmeStatus_OFFSET 16 |
| 4317 | #define DxF0x78_PmeStatus_WIDTH 1 |
| 4318 | #define DxF0x78_PmeStatus_MASK 0x10000 |
| 4319 | #define DxF0x78_PmePending_OFFSET 17 |
| 4320 | #define DxF0x78_PmePending_WIDTH 1 |
| 4321 | #define DxF0x78_PmePending_MASK 0x20000 |
| 4322 | #define DxF0x78_Reserved_31_18_OFFSET 18 |
| 4323 | #define DxF0x78_Reserved_31_18_WIDTH 14 |
| 4324 | #define DxF0x78_Reserved_31_18_MASK 0xfffc0000 |
| 4325 | |
| 4326 | /// DxF0x78 |
| 4327 | typedef union { |
| 4328 | struct { ///< |
| 4329 | UINT32 PmeRequestorId:16; ///< |
| 4330 | UINT32 PmeStatus:1 ; ///< |
| 4331 | UINT32 PmePending:1 ; ///< |
| 4332 | UINT32 Reserved_31_18:14; ///< |
| 4333 | } Field; ///< |
| 4334 | UINT32 Value; ///< |
| 4335 | } DxF0x78_STRUCT; |
| 4336 | |
| 4337 | // **** DxF0x7C Register Definition **** |
| 4338 | // Address |
| 4339 | #define DxF0x7C_ADDRESS 0x7c |
| 4340 | |
| 4341 | // Type |
| 4342 | #define DxF0x7C_TYPE TYPE_D4F0 |
| 4343 | // Field Data |
| 4344 | #define DxF0x7C_CplTimeoutRangeSup_OFFSET 0 |
| 4345 | #define DxF0x7C_CplTimeoutRangeSup_WIDTH 4 |
| 4346 | #define DxF0x7C_CplTimeoutRangeSup_MASK 0xf |
| 4347 | #define DxF0x7C_CplTimeoutDisSup_OFFSET 4 |
| 4348 | #define DxF0x7C_CplTimeoutDisSup_WIDTH 1 |
| 4349 | #define DxF0x7C_CplTimeoutDisSup_MASK 0x10 |
| 4350 | #define DxF0x7C_AriForwardingSupported_OFFSET 5 |
| 4351 | #define DxF0x7C_AriForwardingSupported_WIDTH 1 |
| 4352 | #define DxF0x7C_AriForwardingSupported_MASK 0x20 |
| 4353 | #define DxF0x7C_Reserved_31_6_OFFSET 6 |
| 4354 | #define DxF0x7C_Reserved_31_6_WIDTH 26 |
| 4355 | #define DxF0x7C_Reserved_31_6_MASK 0xffffffc0 |
| 4356 | |
| 4357 | /// DxF0x7C |
| 4358 | typedef union { |
| 4359 | struct { ///< |
| 4360 | UINT32 CplTimeoutRangeSup:4 ; ///< |
| 4361 | UINT32 CplTimeoutDisSup:1 ; ///< |
| 4362 | UINT32 AriForwardingSupported:1 ; ///< |
| 4363 | UINT32 Reserved_31_6:26; ///< |
| 4364 | } Field; ///< |
| 4365 | UINT32 Value; ///< |
| 4366 | } DxF0x7C_STRUCT; |
| 4367 | |
| 4368 | // **** DxF0x80 Register Definition **** |
| 4369 | // Address |
| 4370 | #define DxF0x80_ADDRESS 0x80 |
| 4371 | |
| 4372 | // Type |
| 4373 | #define DxF0x80_TYPE TYPE_D4F0 |
| 4374 | // Field Data |
| 4375 | #define DxF0x80_CplTimeoutValue_OFFSET 0 |
| 4376 | #define DxF0x80_CplTimeoutValue_WIDTH 4 |
| 4377 | #define DxF0x80_CplTimeoutValue_MASK 0xf |
| 4378 | #define DxF0x80_CplTimeoutDis_OFFSET 4 |
| 4379 | #define DxF0x80_CplTimeoutDis_WIDTH 1 |
| 4380 | #define DxF0x80_CplTimeoutDis_MASK 0x10 |
| 4381 | #define DxF0x80_AriForwardingEn_OFFSET 5 |
| 4382 | #define DxF0x80_AriForwardingEn_WIDTH 1 |
| 4383 | #define DxF0x80_AriForwardingEn_MASK 0x20 |
| 4384 | #define DxF0x80_Reserved_31_6_OFFSET 6 |
| 4385 | #define DxF0x80_Reserved_31_6_WIDTH 26 |
| 4386 | #define DxF0x80_Reserved_31_6_MASK 0xffffffc0 |
| 4387 | |
| 4388 | /// DxF0x80 |
| 4389 | typedef union { |
| 4390 | struct { ///< |
| 4391 | UINT32 CplTimeoutValue:4 ; ///< |
| 4392 | UINT32 CplTimeoutDis:1 ; ///< |
| 4393 | UINT32 AriForwardingEn:1 ; ///< |
| 4394 | UINT32 Reserved_31_6:26; ///< |
| 4395 | } Field; ///< |
| 4396 | UINT32 Value; ///< |
| 4397 | } DxF0x80_STRUCT; |
| 4398 | |
| 4399 | // **** DxF0x84 Register Definition **** |
| 4400 | // Address |
| 4401 | #define DxF0x84_ADDRESS 0x84 |
| 4402 | |
| 4403 | // Type |
| 4404 | #define DxF0x84_TYPE TYPE_D4F0 |
| 4405 | // Field Data |
| 4406 | #define DxF0x84_Reserved_31_0_OFFSET 0 |
| 4407 | #define DxF0x84_Reserved_31_0_WIDTH 32 |
| 4408 | #define DxF0x84_Reserved_31_0_MASK 0xffffffff |
| 4409 | |
| 4410 | /// DxF0x84 |
| 4411 | typedef union { |
| 4412 | struct { ///< |
| 4413 | UINT32 Reserved_31_0:32; ///< |
| 4414 | } Field; ///< |
| 4415 | UINT32 Value; ///< |
| 4416 | } DxF0x84_STRUCT; |
| 4417 | |
| 4418 | // **** DxF0x88 Register Definition **** |
| 4419 | // Address |
| 4420 | #define DxF0x88_ADDRESS 0x88 |
| 4421 | |
| 4422 | // Type |
| 4423 | #define DxF0x88_TYPE TYPE_D4F0 |
| 4424 | // Field Data |
| 4425 | #define DxF0x88_TargetLinkSpeed_OFFSET 0 |
| 4426 | #define DxF0x88_TargetLinkSpeed_WIDTH 4 |
| 4427 | #define DxF0x88_TargetLinkSpeed_MASK 0xf |
| 4428 | #define DxF0x88_EnterCompliance_OFFSET 4 |
| 4429 | #define DxF0x88_EnterCompliance_WIDTH 1 |
| 4430 | #define DxF0x88_EnterCompliance_MASK 0x10 |
| 4431 | #define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5 |
| 4432 | #define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1 |
| 4433 | #define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20 |
| 4434 | #define DxF0x88_SelectableDeemphasis_OFFSET 6 |
| 4435 | #define DxF0x88_SelectableDeemphasis_WIDTH 1 |
| 4436 | #define DxF0x88_SelectableDeemphasis_MASK 0x40 |
| 4437 | #define DxF0x88_XmitMargin_OFFSET 7 |
| 4438 | #define DxF0x88_XmitMargin_WIDTH 3 |
| 4439 | #define DxF0x88_XmitMargin_MASK 0x380 |
| 4440 | #define DxF0x88_EnterModCompliance_OFFSET 10 |
| 4441 | #define DxF0x88_EnterModCompliance_WIDTH 1 |
| 4442 | #define DxF0x88_EnterModCompliance_MASK 0x400 |
| 4443 | #define DxF0x88_ComplianceSOS_OFFSET 11 |
| 4444 | #define DxF0x88_ComplianceSOS_WIDTH 1 |
| 4445 | #define DxF0x88_ComplianceSOS_MASK 0x800 |
| 4446 | #define DxF0x88_ComplianceDeemphasis_OFFSET 12 |
| 4447 | #define DxF0x88_ComplianceDeemphasis_WIDTH 1 |
| 4448 | #define DxF0x88_ComplianceDeemphasis_MASK 0x1000 |
| 4449 | #define DxF0x88_Reserved_15_13_OFFSET 13 |
| 4450 | #define DxF0x88_Reserved_15_13_WIDTH 3 |
| 4451 | #define DxF0x88_Reserved_15_13_MASK 0xe000 |
| 4452 | #define DxF0x88_CurDeemphasisLevel_OFFSET 16 |
| 4453 | #define DxF0x88_CurDeemphasisLevel_WIDTH 1 |
| 4454 | #define DxF0x88_CurDeemphasisLevel_MASK 0x10000 |
| 4455 | #define DxF0x88_Reserved_31_17_OFFSET 17 |
| 4456 | #define DxF0x88_Reserved_31_17_WIDTH 15 |
| 4457 | #define DxF0x88_Reserved_31_17_MASK 0xfffe0000 |
| 4458 | |
| 4459 | /// DxF0x88 |
| 4460 | typedef union { |
| 4461 | struct { ///< |
| 4462 | UINT32 TargetLinkSpeed:4 ; ///< |
| 4463 | UINT32 EnterCompliance:1 ; ///< |
| 4464 | UINT32 HwAutonomousSpeedDisable:1 ; ///< |
| 4465 | UINT32 SelectableDeemphasis:1 ; ///< |
| 4466 | UINT32 XmitMargin:3 ; ///< |
| 4467 | UINT32 EnterModCompliance:1 ; ///< |
| 4468 | UINT32 ComplianceSOS:1 ; ///< |
| 4469 | UINT32 ComplianceDeemphasis:1 ; ///< |
| 4470 | UINT32 Reserved_15_13:3 ; ///< |
| 4471 | UINT32 CurDeemphasisLevel:1 ; ///< |
| 4472 | UINT32 Reserved_31_17:15; ///< |
| 4473 | } Field; ///< |
| 4474 | UINT32 Value; ///< |
| 4475 | } DxF0x88_STRUCT; |
| 4476 | |
| 4477 | // **** DxF0x8C Register Definition **** |
| 4478 | // Address |
| 4479 | #define DxF0x8C_ADDRESS 0x8c |
| 4480 | |
| 4481 | // Type |
| 4482 | #define DxF0x8C_TYPE TYPE_D4F0 |
| 4483 | // Field Data |
| 4484 | #define DxF0x8C_Reserved_31_0_OFFSET 0 |
| 4485 | #define DxF0x8C_Reserved_31_0_WIDTH 32 |
| 4486 | #define DxF0x8C_Reserved_31_0_MASK 0xffffffff |
| 4487 | |
| 4488 | /// DxF0x8C |
| 4489 | typedef union { |
| 4490 | struct { ///< |
| 4491 | UINT32 Reserved_31_0:32; ///< |
| 4492 | } Field; ///< |
| 4493 | UINT32 Value; ///< |
| 4494 | } DxF0x8C_STRUCT; |
| 4495 | |
| 4496 | // **** DxF0x90 Register Definition **** |
| 4497 | // Address |
| 4498 | #define DxF0x90_ADDRESS 0x90 |
| 4499 | |
| 4500 | // Type |
| 4501 | #define DxF0x90_TYPE TYPE_D4F0 |
| 4502 | // Field Data |
| 4503 | #define DxF0x90_Reserved_31_0_OFFSET 0 |
| 4504 | #define DxF0x90_Reserved_31_0_WIDTH 32 |
| 4505 | #define DxF0x90_Reserved_31_0_MASK 0xffffffff |
| 4506 | |
| 4507 | /// DxF0x90 |
| 4508 | typedef union { |
| 4509 | struct { ///< |
| 4510 | UINT32 Reserved_31_0:32; ///< |
| 4511 | } Field; ///< |
| 4512 | UINT32 Value; ///< |
| 4513 | } DxF0x90_STRUCT; |
| 4514 | |
| 4515 | // **** DxF0x128 Register Definition **** |
| 4516 | // Address |
| 4517 | #define DxF0x128_ADDRESS 0x128 |
| 4518 | |
| 4519 | // Type |
| 4520 | #define DxF0x128_TYPE TYPE_D4F0 |
| 4521 | // Field Data |
| 4522 | #define DxF0x128_Reserved_15_0_OFFSET 0 |
| 4523 | #define DxF0x128_Reserved_15_0_WIDTH 16 |
| 4524 | #define DxF0x128_Reserved_15_0_MASK 0xffff |
| 4525 | #define DxF0x128_PortArbTableStatus_OFFSET 16 |
| 4526 | #define DxF0x128_PortArbTableStatus_WIDTH 1 |
| 4527 | #define DxF0x128_PortArbTableStatus_MASK 0x10000 |
| 4528 | #define DxF0x128_VcNegotiationPending_OFFSET 17 |
| 4529 | #define DxF0x128_VcNegotiationPending_WIDTH 1 |
| 4530 | #define DxF0x128_VcNegotiationPending_MASK 0x20000 |
| 4531 | #define DxF0x128_Reserved_31_18_OFFSET 18 |
| 4532 | #define DxF0x128_Reserved_31_18_WIDTH 14 |
| 4533 | #define DxF0x128_Reserved_31_18_MASK 0xfffc0000 |
| 4534 | |
| 4535 | /// DxF0x128 |
| 4536 | typedef union { |
| 4537 | struct { ///< |
| 4538 | UINT32 Reserved_15_0:16; ///< |
| 4539 | UINT32 PortArbTableStatus:1 ; ///< |
| 4540 | UINT32 VcNegotiationPending:1 ; ///< |
| 4541 | UINT32 Reserved_31_18:14; ///< |
| 4542 | } Field; ///< |
| 4543 | UINT32 Value; ///< |
| 4544 | } DxF0x128_STRUCT; |
| 4545 | |
| 4546 | // **** FCRxFE00_6000 Register Definition **** |
| 4547 | // Address |
| 4548 | #define FCRxFE00_6000_ADDRESS 0xfe006000 |
| 4549 | |
| 4550 | // Type |
| 4551 | #define FCRxFE00_6000_TYPE TYPE_FCR |
| 4552 | // Field Data |
| 4553 | #define FCRxFE00_6000_Reserved_6_0_OFFSET 0 |
| 4554 | #define FCRxFE00_6000_Reserved_6_0_WIDTH 7 |
| 4555 | #define FCRxFE00_6000_Reserved_6_0_MASK 0x7f |
| 4556 | #define FCRxFE00_6000_NbPs0Vid_OFFSET 7 |
| 4557 | #define FCRxFE00_6000_NbPs0Vid_WIDTH 7 |
| 4558 | #define FCRxFE00_6000_NbPs0Vid_MASK 0x3f80 |
| 4559 | #define FCRxFE00_6000_NbPs1Vid_OFFSET 14 |
| 4560 | #define FCRxFE00_6000_NbPs1Vid_WIDTH 7 |
| 4561 | #define FCRxFE00_6000_NbPs1Vid_MASK 0x1fc000 |
| 4562 | #define FCRxFE00_6000_Reserved_31_21_OFFSET 21 |
| 4563 | #define FCRxFE00_6000_Reserved_31_21_WIDTH 11 |
| 4564 | #define FCRxFE00_6000_Reserved_31_21_MASK 0xffe00000 |
| 4565 | |
| 4566 | /// FCRxFE00_6000 |
| 4567 | typedef union { |
| 4568 | struct { ///< |
| 4569 | UINT32 Reserved_6_0:7 ; ///< |
| 4570 | UINT32 NbPs0Vid:7 ; ///< |
| 4571 | UINT32 NbPs1Vid:7 ; ///< |
| 4572 | UINT32 Reserved_31_21:11; ///< |
| 4573 | } Field; ///< |
| 4574 | UINT32 Value; ///< |
| 4575 | } FCRxFE00_6000_STRUCT; |
| 4576 | |
| 4577 | // **** FCRxFE00_6002 Register Definition **** |
| 4578 | // Address |
| 4579 | #define FCRxFE00_6002_ADDRESS 0xfe006002 |
| 4580 | |
| 4581 | // Type |
| 4582 | #define FCRxFE00_6002_TYPE TYPE_FCR |
| 4583 | // Field Data |
| 4584 | #define FCRxFE00_6002_Reserved_4_0_OFFSET 0 |
| 4585 | #define FCRxFE00_6002_Reserved_4_0_WIDTH 5 |
| 4586 | #define FCRxFE00_6002_Reserved_4_0_MASK 0x1f |
| 4587 | #define FCRxFE00_6002_NbPs1VidAddl_OFFSET 5 |
| 4588 | #define FCRxFE00_6002_NbPs1VidAddl_WIDTH 7 |
| 4589 | #define FCRxFE00_6002_NbPs1VidAddl_MASK 0xfe0 |
| 4590 | #define FCRxFE00_6002_NbPs1VidHigh_OFFSET 12 |
| 4591 | #define FCRxFE00_6002_NbPs1VidHigh_WIDTH 7 |
| 4592 | #define FCRxFE00_6002_NbPs1VidHigh_MASK 0x7f000 |
| 4593 | #define FCRxFE00_6002_Reserved_31_19_OFFSET 19 |
| 4594 | #define FCRxFE00_6002_Reserved_31_19_WIDTH 13 |
| 4595 | #define FCRxFE00_6002_Reserved_31_19_MASK 0xfff80000 |
| 4596 | |
| 4597 | /// FCRxFE00_6002 |
| 4598 | typedef union { |
| 4599 | struct { ///< |
| 4600 | UINT32 Reserved_4_0:5 ; ///< |
| 4601 | UINT32 NbPs1VidAddl:7 ; ///< |
| 4602 | UINT32 NbPs1VidHigh:7 ; ///< |
| 4603 | UINT32 Reserved_31_19:13; ///< |
| 4604 | } Field; ///< |
| 4605 | UINT32 Value; ///< |
| 4606 | } FCRxFE00_6002_STRUCT; |
| 4607 | |
| 4608 | // **** FCRxFE00_7006 Register Definition **** |
| 4609 | // Address |
| 4610 | #define FCRxFE00_7006_ADDRESS 0xfe007006 |
| 4611 | |
| 4612 | // Type |
| 4613 | #define FCRxFE00_7006_TYPE TYPE_FCR |
| 4614 | // Field Data |
| 4615 | #define FCRxFE00_7006_Reserved_13_0_OFFSET 0 |
| 4616 | #define FCRxFE00_7006_Reserved_13_0_WIDTH 14 |
| 4617 | #define FCRxFE00_7006_Reserved_13_0_MASK 0x3fff |
| 4618 | #define FCRxFE00_7006_NbPs1NclkDiv_OFFSET 14 |
| 4619 | #define FCRxFE00_7006_NbPs1NclkDiv_WIDTH 7 |
| 4620 | #define FCRxFE00_7006_NbPs1NclkDiv_MASK 0x1fc000 |
| 4621 | #define FCRxFE00_7006_MaxNbFreqAtMinVid_OFFSET 21 |
| 4622 | #define FCRxFE00_7006_MaxNbFreqAtMinVid_WIDTH 5 |
| 4623 | #define FCRxFE00_7006_MaxNbFreqAtMinVid_MASK 0x3e00000 |
| 4624 | #define FCRxFE00_7006_Reserved_31_26_OFFSET 26 |
| 4625 | #define FCRxFE00_7006_Reserved_31_26_WIDTH 6 |
| 4626 | #define FCRxFE00_7006_Reserved_31_26_MASK 0xfc000000 |
| 4627 | |
| 4628 | /// FCRxFE00_7006 |
| 4629 | typedef union { |
| 4630 | struct { ///< |
| 4631 | UINT32 Reserved_13_0:14; ///< |
| 4632 | UINT32 NbPs1NclkDiv:7 ; ///< |
| 4633 | UINT32 MaxNbFreqAtMinVid:5 ; ///< |
| 4634 | UINT32 Reserved_31_26:6 ; ///< |
| 4635 | } Field; ///< |
| 4636 | UINT32 Value; ///< |
| 4637 | } FCRxFE00_7006_STRUCT; |
| 4638 | |
| 4639 | // **** FCRxFE00_7009 Register Definition **** |
| 4640 | // Address |
| 4641 | #define FCRxFE00_7009_ADDRESS 0xfe007009 |
| 4642 | |
| 4643 | // Type |
| 4644 | #define FCRxFE00_7009_TYPE TYPE_FCR |
| 4645 | // Field Data |
| 4646 | #define FCRxFE00_7009_Reserved_1_0_OFFSET 0 |
| 4647 | #define FCRxFE00_7009_Reserved_1_0_WIDTH 2 |
| 4648 | #define FCRxFE00_7009_Reserved_1_0_MASK 0x3 |
| 4649 | #define FCRxFE00_7009_NbPs0NclkDiv_OFFSET 2 |
| 4650 | #define FCRxFE00_7009_NbPs0NclkDiv_WIDTH 7 |
| 4651 | #define FCRxFE00_7009_NbPs0NclkDiv_MASK 0x1fc |
| 4652 | #define FCRxFE00_7009_Reserved_31_9_OFFSET 9 |
| 4653 | #define FCRxFE00_7009_Reserved_31_9_WIDTH 23 |
| 4654 | #define FCRxFE00_7009_Reserved_31_9_MASK 0xfffffe00 |
| 4655 | |
| 4656 | /// FCRxFE00_7009 |
| 4657 | typedef union { |
| 4658 | struct { ///< |
| 4659 | UINT32 Reserved_1_0:2 ; ///< |
| 4660 | UINT32 NbPs0NclkDiv:7 ; ///< |
| 4661 | UINT32 Reserved_31_9:23; ///< |
| 4662 | } Field; ///< |
| 4663 | UINT32 Value; ///< |
| 4664 | } FCRxFE00_7009_STRUCT; |
| 4665 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 4666 | // **** FCRxFE00_7079 Register Definition **** |
| 4667 | // Address |
| 4668 | #define FCRxFE00_7079_ADDRESS 0xfe007079 |
| 4669 | |
| 4670 | // Type |
| 4671 | #define FCRxFE00_7079_TYPE TYPE_FCR |
| 4672 | // Field Data |
| 4673 | #define FCRxFE00_7079_Reserved_4_0_OFFSET 0 |
| 4674 | #define FCRxFE00_7079_Reserved_4_0_WIDTH 5 |
| 4675 | #define FCRxFE00_7079_Reserved_4_0_MASK 0x1f |
| 4676 | #define FCRxFE00_7079_CoreDis_OFFSET 5 |
| 4677 | #define FCRxFE00_7079_CoreDis_WIDTH 2 |
| 4678 | #define FCRxFE00_7079_CoreDis_MASK 0x60 |
| 4679 | #define FCRxFE00_7079_Reserved_31_7_OFFSET 7 |
| 4680 | #define FCRxFE00_7079_Reserved_31_7_WIDTH 25 |
| 4681 | #define FCRxFE00_7079_Reserved_31_7_MASK 0xffffff80 |
| 4682 | |
| 4683 | /// FCRxFE00_7079 |
| 4684 | typedef union { |
| 4685 | struct { ///< |
| 4686 | UINT32 Reserved_4_0:5 ; ///< |
| 4687 | UINT32 CoreDis:2 ; ///< |
| 4688 | UINT32 Reserved_31_7:25; ///< |
| 4689 | } Field; ///< |
| 4690 | UINT32 Value; ///< |
| 4691 | } FCRxFE00_7079_STRUCT; |
| 4692 | |
| 4693 | |
| 4694 | // **** FCRxFF30_0AE6 Register Definition **** |
| 4695 | // Address |
| 4696 | #define FCRxFF30_0AE6_ADDRESS 0xff300ae6 |
| 4697 | |
| 4698 | // Type |
| 4699 | #define FCRxFF30_0AE6_TYPE TYPE_FCR |
| 4700 | // Field Data |
| 4701 | #define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 |
| 4702 | #define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 |
| 4703 | #define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_MASK 0x3ff |
| 4704 | #define FCRxFF30_0AE6_Reserved_10_10_OFFSET 10 |
| 4705 | #define FCRxFF30_0AE6_Reserved_10_10_WIDTH 1 |
| 4706 | #define FCRxFF30_0AE6_Reserved_10_10_MASK 0x400 |
| 4707 | #define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 |
| 4708 | #define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 |
| 4709 | #define FCRxFF30_0AE6_RengExecuteOnRegUpdate_MASK 0x800 |
| 4710 | #define FCRxFF30_0AE6_Reserved_15_12_OFFSET 12 |
| 4711 | #define FCRxFF30_0AE6_Reserved_15_12_WIDTH 4 |
| 4712 | #define FCRxFF30_0AE6_Reserved_15_12_MASK 0xf000 |
| 4713 | #define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 |
| 4714 | #define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 |
| 4715 | #define FCRxFF30_0AE6_StctrlStutterEn_MASK 0x10000 |
| 4716 | #define FCRxFF30_0AE6_Reserved_23_17_OFFSET 17 |
| 4717 | #define FCRxFF30_0AE6_Reserved_23_17_WIDTH 7 |
| 4718 | #define FCRxFF30_0AE6_Reserved_23_17_MASK 0xfe0000 |
| 4719 | #define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 |
| 4720 | #define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 |
| 4721 | #define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_MASK 0x1000000 |
| 4722 | #define FCRxFF30_0AE6_Reserved_26_25_OFFSET 25 |
| 4723 | #define FCRxFF30_0AE6_Reserved_26_25_WIDTH 2 |
| 4724 | #define FCRxFF30_0AE6_Reserved_26_25_MASK 0x6000000 |
| 4725 | #define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 |
| 4726 | #define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 |
| 4727 | #define FCRxFF30_0AE6_CriticalRegsLock_MASK 0x8000000 |
| 4728 | #define FCRxFF30_0AE6_Reserved_31_28_OFFSET 28 |
| 4729 | #define FCRxFF30_0AE6_Reserved_31_28_WIDTH 4 |
| 4730 | #define FCRxFF30_0AE6_Reserved_31_28_MASK 0xf0000000 |
| 4731 | |
| 4732 | /// FCRxFF30_0AE6 |
| 4733 | typedef union { |
| 4734 | struct { ///< |
| 4735 | UINT32 RengExecuteNonsecureStartPtr:10; ///< |
| 4736 | UINT32 Reserved_10_10:1 ; ///< |
| 4737 | UINT32 RengExecuteOnRegUpdate:1 ; ///< |
| 4738 | UINT32 Reserved_15_12:4 ; ///< |
| 4739 | UINT32 StctrlStutterEn:1 ; ///< |
| 4740 | UINT32 Reserved_23_17:7 ; ///< |
| 4741 | UINT32 StctrlIgnoreProtectionFault:1 ; ///< |
| 4742 | UINT32 Reserved_26_25:2 ; ///< |
| 4743 | UINT32 CriticalRegsLock:1 ; ///< |
| 4744 | UINT32 Reserved_31_28:4 ; ///< |
| 4745 | } Field; ///< |
| 4746 | UINT32 Value; ///< |
| 4747 | } FCRxFF30_0AE6_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 4748 | |
| 4749 | // **** D0F0x64_x00 Register Definition **** |
| 4750 | // Address |
| 4751 | #define D0F0x64_x00_ADDRESS 0x0 |
| 4752 | |
| 4753 | // Type |
| 4754 | #define D0F0x64_x00_TYPE TYPE_D0F0x64 |
| 4755 | // Field Data |
| 4756 | #define D0F0x64_x00_Reserved_5_0_OFFSET 0 |
| 4757 | #define D0F0x64_x00_Reserved_5_0_WIDTH 6 |
| 4758 | #define D0F0x64_x00_Reserved_5_0_MASK 0x3f |
| 4759 | #define D0F0x64_x00_NbFchCfgEn_OFFSET 6 |
| 4760 | #define D0F0x64_x00_NbFchCfgEn_WIDTH 1 |
| 4761 | #define D0F0x64_x00_NbFchCfgEn_MASK 0x40 |
| 4762 | #define D0F0x64_x00_HwInitWrLock_OFFSET 7 |
| 4763 | #define D0F0x64_x00_HwInitWrLock_WIDTH 1 |
| 4764 | #define D0F0x64_x00_HwInitWrLock_MASK 0x80 |
| 4765 | #define D0F0x64_x00_Reserved_31_8_OFFSET 8 |
| 4766 | #define D0F0x64_x00_Reserved_31_8_WIDTH 24 |
| 4767 | #define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00 |
| 4768 | |
| 4769 | /// D0F0x64_x00 |
| 4770 | typedef union { |
| 4771 | struct { ///< |
| 4772 | UINT32 Reserved_5_0:6 ; ///< |
| 4773 | UINT32 NbFchCfgEn:1 ; ///< |
| 4774 | UINT32 HwInitWrLock:1 ; ///< |
| 4775 | UINT32 Reserved_31_8:24; ///< |
| 4776 | } Field; ///< |
| 4777 | UINT32 Value; ///< |
| 4778 | } D0F0x64_x00_STRUCT; |
| 4779 | |
| 4780 | // **** D0F0x64_x0B Register Definition **** |
| 4781 | // Address |
| 4782 | #define D0F0x64_x0B_ADDRESS 0xb |
| 4783 | |
| 4784 | // Type |
| 4785 | #define D0F0x64_x0B_TYPE TYPE_D0F0x64 |
| 4786 | // Field Data |
| 4787 | #define D0F0x64_x0B_Reserved_19_0_OFFSET 0 |
| 4788 | #define D0F0x64_x0B_Reserved_19_0_WIDTH 20 |
| 4789 | #define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff |
| 4790 | #define D0F0x64_x0B_SetPowEn_OFFSET 20 |
| 4791 | #define D0F0x64_x0B_SetPowEn_WIDTH 1 |
| 4792 | #define D0F0x64_x0B_SetPowEn_MASK 0x100000 |
| 4793 | #define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21 |
| 4794 | #define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1 |
| 4795 | #define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000 |
| 4796 | #define D0F0x64_x0B_Reserved_22_22_OFFSET 22 |
| 4797 | #define D0F0x64_x0B_Reserved_22_22_WIDTH 1 |
| 4798 | #define D0F0x64_x0B_Reserved_22_22_MASK 0x400000 |
| 4799 | #define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23 |
| 4800 | #define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1 |
| 4801 | #define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000 |
| 4802 | #define D0F0x64_x0B_Reserved_31_24_OFFSET 24 |
| 4803 | #define D0F0x64_x0B_Reserved_31_24_WIDTH 8 |
| 4804 | #define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000 |
| 4805 | |
| 4806 | /// D0F0x64_x0B |
| 4807 | typedef union { |
| 4808 | struct { ///< |
| 4809 | UINT32 Reserved_19_0:20; ///< |
| 4810 | UINT32 SetPowEn:1 ; ///< |
| 4811 | UINT32 IocFchSetPowEn:1 ; ///< |
| 4812 | UINT32 Reserved_22_22:1 ; ///< |
| 4813 | UINT32 IocFchSetPmeTurnOffEn:1 ; ///< |
| 4814 | UINT32 Reserved_31_24:8 ; ///< |
| 4815 | } Field; ///< |
| 4816 | UINT32 Value; ///< |
| 4817 | } D0F0x64_x0B_STRUCT; |
| 4818 | |
| 4819 | // **** D0F0x64_x0C Register Definition **** |
| 4820 | // Address |
| 4821 | #define D0F0x64_x0C_ADDRESS 0xc |
| 4822 | |
| 4823 | // Type |
| 4824 | #define D0F0x64_x0C_TYPE TYPE_D0F0x64 |
| 4825 | // Field Data |
| 4826 | #define D0F0x64_x0C_Reserved_3_0_OFFSET 0 |
| 4827 | #define D0F0x64_x0C_Reserved_3_0_WIDTH 4 |
| 4828 | #define D0F0x64_x0C_Reserved_3_0_MASK 0xf |
| 4829 | #define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4 |
| 4830 | #define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1 |
| 4831 | #define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10 |
| 4832 | #define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5 |
| 4833 | #define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1 |
| 4834 | #define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20 |
| 4835 | #define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6 |
| 4836 | #define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1 |
| 4837 | #define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40 |
| 4838 | #define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7 |
| 4839 | #define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1 |
| 4840 | #define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80 |
| 4841 | #define D0F0x64_x0C_Reserved_31_8_OFFSET 8 |
| 4842 | #define D0F0x64_x0C_Reserved_31_8_WIDTH 24 |
| 4843 | #define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00 |
| 4844 | |
| 4845 | /// D0F0x64_x0C |
| 4846 | typedef union { |
| 4847 | struct { ///< |
| 4848 | UINT32 Reserved_3_0:4 ; ///< |
| 4849 | UINT32 Dev4BridgeDis:1 ; ///< |
| 4850 | UINT32 Dev5BridgeDis:1 ; ///< |
| 4851 | UINT32 Dev6BridgeDis:1 ; ///< |
| 4852 | UINT32 Dev7BridgeDis:1 ; ///< |
| 4853 | UINT32 Reserved_31_8:24; ///< |
| 4854 | } Field; ///< |
| 4855 | UINT32 Value; ///< |
| 4856 | } D0F0x64_x0C_STRUCT; |
| 4857 | |
| 4858 | // **** D0F0x64_x16 Register Definition **** |
| 4859 | // Address |
| 4860 | #define D0F0x64_x16_ADDRESS 0x16 |
| 4861 | |
| 4862 | // Type |
| 4863 | #define D0F0x64_x16_TYPE TYPE_D0F0x64 |
| 4864 | // Field Data |
| 4865 | #define D0F0x64_x16_AerUrMsgEn_OFFSET 0 |
| 4866 | #define D0F0x64_x16_AerUrMsgEn_WIDTH 1 |
| 4867 | #define D0F0x64_x16_AerUrMsgEn_MASK 0x1 |
| 4868 | #define D0F0x64_x16_Reserved_31_1_OFFSET 1 |
| 4869 | #define D0F0x64_x16_Reserved_31_1_WIDTH 31 |
| 4870 | #define D0F0x64_x16_Reserved_31_1_MASK 0xfffffffe |
| 4871 | |
| 4872 | /// D0F0x64_x16 |
| 4873 | typedef union { |
| 4874 | struct { ///< |
| 4875 | UINT32 AerUrMsgEn:1 ; ///< |
| 4876 | UINT32 Reserved_31_1:31; ///< |
| 4877 | } Field; ///< |
| 4878 | UINT32 Value; ///< |
| 4879 | } D0F0x64_x16_STRUCT; |
| 4880 | |
| 4881 | // **** D0F0x64_x19 Register Definition **** |
| 4882 | // Address |
| 4883 | #define D0F0x64_x19_ADDRESS 0x19 |
| 4884 | |
| 4885 | // Type |
| 4886 | #define D0F0x64_x19_TYPE TYPE_D0F0x64 |
| 4887 | // Field Data |
| 4888 | #define D0F0x64_x19_TomEn_OFFSET 0 |
| 4889 | #define D0F0x64_x19_TomEn_WIDTH 1 |
| 4890 | #define D0F0x64_x19_TomEn_MASK 0x1 |
| 4891 | #define D0F0x64_x19_Reserved_22_1_OFFSET 1 |
| 4892 | #define D0F0x64_x19_Reserved_22_1_WIDTH 22 |
| 4893 | #define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe |
| 4894 | #define D0F0x64_x19_Tom2_31_23__OFFSET 23 |
| 4895 | #define D0F0x64_x19_Tom2_31_23__WIDTH 9 |
| 4896 | #define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 |
| 4897 | |
| 4898 | /// D0F0x64_x19 |
| 4899 | typedef union { |
| 4900 | struct { ///< |
| 4901 | UINT32 TomEn:1 ; ///< |
| 4902 | UINT32 Reserved_22_1:22; ///< |
| 4903 | UINT32 Tom2_31_23_:9 ; ///< |
| 4904 | } Field; ///< |
| 4905 | UINT32 Value; ///< |
| 4906 | } D0F0x64_x19_STRUCT; |
| 4907 | |
| 4908 | // **** D0F0x64_x1A Register Definition **** |
| 4909 | // Address |
| 4910 | #define D0F0x64_x1A_ADDRESS 0x1a |
| 4911 | |
| 4912 | // Type |
| 4913 | #define D0F0x64_x1A_TYPE TYPE_D0F0x64 |
| 4914 | // Field Data |
| 4915 | #define D0F0x64_x1A_Tom2_35_32__OFFSET 0 |
| 4916 | #define D0F0x64_x1A_Tom2_35_32__WIDTH 4 |
| 4917 | #define D0F0x64_x1A_Tom2_35_32__MASK 0xf |
| 4918 | #define D0F0x64_x1A_Reserved_31_4_OFFSET 4 |
| 4919 | #define D0F0x64_x1A_Reserved_31_4_WIDTH 28 |
| 4920 | #define D0F0x64_x1A_Reserved_31_4_MASK 0xfffffff0 |
| 4921 | |
| 4922 | /// D0F0x64_x1A |
| 4923 | typedef union { |
| 4924 | struct { ///< |
| 4925 | UINT32 Tom2_35_32_:4 ; ///< |
| 4926 | UINT32 Reserved_31_4:28; ///< |
| 4927 | } Field; ///< |
| 4928 | UINT32 Value; ///< |
| 4929 | } D0F0x64_x1A_STRUCT; |
| 4930 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 4931 | // **** D0F0x64_x1C Register Definition **** |
| 4932 | // Address |
| 4933 | #define D0F0x64_x1C_ADDRESS 0x1c |
| 4934 | |
| 4935 | // Type |
| 4936 | #define D0F0x64_x1C_TYPE TYPE_D0F0x64 |
| 4937 | // Field Data |
| 4938 | #define D0F0x64_x1C_WriteDis_OFFSET 0 |
| 4939 | #define D0F0x64_x1C_WriteDis_WIDTH 1 |
| 4940 | #define D0F0x64_x1C_WriteDis_MASK 0x1 |
| 4941 | #define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 |
| 4942 | #define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 |
| 4943 | #define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 |
| 4944 | #define D0F0x64_x1C_F064BarEn_OFFSET 2 |
| 4945 | #define D0F0x64_x1C_F064BarEn_WIDTH 1 |
| 4946 | #define D0F0x64_x1C_F064BarEn_MASK 0x4 |
| 4947 | #define D0F0x64_x1C_MemApSize_OFFSET 3 |
| 4948 | #define D0F0x64_x1C_MemApSize_WIDTH 3 |
| 4949 | #define D0F0x64_x1C_MemApSize_MASK 0x38 |
| 4950 | #define D0F0x64_x1C_RegApSize_OFFSET 6 |
| 4951 | #define D0F0x64_x1C_RegApSize_WIDTH 1 |
| 4952 | #define D0F0x64_x1C_RegApSize_MASK 0x40 |
| 4953 | #define D0F0x64_x1C_Reserved_7_7_OFFSET 7 |
| 4954 | #define D0F0x64_x1C_Reserved_7_7_WIDTH 1 |
| 4955 | #define D0F0x64_x1C_Reserved_7_7_MASK 0x80 |
| 4956 | #define D0F0x64_x1C_AudioEn_OFFSET 8 |
| 4957 | #define D0F0x64_x1C_AudioEn_WIDTH 1 |
| 4958 | #define D0F0x64_x1C_AudioEn_MASK 0x100 |
| 4959 | #define D0F0x64_x1C_MsiDis_OFFSET 9 |
| 4960 | #define D0F0x64_x1C_MsiDis_WIDTH 1 |
| 4961 | #define D0F0x64_x1C_MsiDis_MASK 0x200 |
| 4962 | #define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 |
| 4963 | #define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 |
| 4964 | #define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 |
| 4965 | #define D0F0x64_x1C_Audio64BarEn_OFFSET 11 |
| 4966 | #define D0F0x64_x1C_Audio64BarEn_WIDTH 1 |
| 4967 | #define D0F0x64_x1C_Audio64BarEn_MASK 0x800 |
| 4968 | #define D0F0x64_x1C_Reserved_15_12_OFFSET 12 |
| 4969 | #define D0F0x64_x1C_Reserved_15_12_WIDTH 4 |
| 4970 | #define D0F0x64_x1C_Reserved_15_12_MASK 0xf000 |
| 4971 | #define D0F0x64_x1C_IoBarDis_OFFSET 16 |
| 4972 | #define D0F0x64_x1C_IoBarDis_WIDTH 1 |
| 4973 | #define D0F0x64_x1C_IoBarDis_MASK 0x10000 |
| 4974 | #define D0F0x64_x1C_F0En_OFFSET 17 |
| 4975 | #define D0F0x64_x1C_F0En_WIDTH 1 |
| 4976 | #define D0F0x64_x1C_F0En_MASK 0x20000 |
| 4977 | #define D0F0x64_x1C_Reserved_22_18_OFFSET 18 |
| 4978 | #define D0F0x64_x1C_Reserved_22_18_WIDTH 5 |
| 4979 | #define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000 |
| 4980 | #define D0F0x64_x1C_RcieEn_OFFSET 23 |
| 4981 | #define D0F0x64_x1C_RcieEn_WIDTH 1 |
| 4982 | #define D0F0x64_x1C_RcieEn_MASK 0x800000 |
| 4983 | #define D0F0x64_x1C_Reserved_31_24_OFFSET 24 |
| 4984 | #define D0F0x64_x1C_Reserved_31_24_WIDTH 8 |
| 4985 | #define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000 |
| 4986 | |
| 4987 | /// D0F0x64_x1C |
| 4988 | typedef union { |
| 4989 | struct { ///< |
| 4990 | UINT32 WriteDis:1 ; ///< |
| 4991 | UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< |
| 4992 | UINT32 F064BarEn:1 ; ///< |
| 4993 | UINT32 MemApSize:3 ; ///< |
| 4994 | UINT32 RegApSize:1 ; ///< |
| 4995 | UINT32 Reserved_7_7:1 ; ///< |
| 4996 | UINT32 AudioEn:1 ; ///< |
| 4997 | UINT32 MsiDis:1 ; ///< |
| 4998 | UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< |
| 4999 | UINT32 Audio64BarEn:1 ; ///< |
| 5000 | UINT32 Reserved_15_12:4 ; ///< |
| 5001 | UINT32 IoBarDis:1 ; ///< |
| 5002 | UINT32 F0En:1 ; ///< |
| 5003 | UINT32 Reserved_22_18:5 ; ///< |
| 5004 | UINT32 RcieEn:1 ; ///< |
| 5005 | UINT32 Reserved_31_24:8 ; ///< |
| 5006 | } Field; ///< |
| 5007 | UINT32 Value; ///< |
| 5008 | } D0F0x64_x1C_STRUCT; |
| 5009 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 5010 | // **** D0F0x64_x1D Register Definition **** |
| 5011 | // Address |
| 5012 | #define D0F0x64_x1D_ADDRESS 0x1d |
| 5013 | |
| 5014 | // Type |
| 5015 | #define D0F0x64_x1D_TYPE TYPE_D0F0x64 |
| 5016 | // Field Data |
| 5017 | #define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0 |
| 5018 | #define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1 |
| 5019 | #define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1 |
| 5020 | #define D0F0x64_x1D_VgaEn_OFFSET 1 |
| 5021 | #define D0F0x64_x1D_VgaEn_WIDTH 1 |
| 5022 | #define D0F0x64_x1D_VgaEn_MASK 0x2 |
| 5023 | #define D0F0x64_x1D_Reserved_2_2_OFFSET 2 |
| 5024 | #define D0F0x64_x1D_Reserved_2_2_WIDTH 1 |
| 5025 | #define D0F0x64_x1D_Reserved_2_2_MASK 0x4 |
| 5026 | #define D0F0x64_x1D_Vga16En_OFFSET 3 |
| 5027 | #define D0F0x64_x1D_Vga16En_WIDTH 1 |
| 5028 | #define D0F0x64_x1D_Vga16En_MASK 0x8 |
| 5029 | #define D0F0x64_x1D_Reserved_31_4_OFFSET 4 |
| 5030 | #define D0F0x64_x1D_Reserved_31_4_WIDTH 28 |
| 5031 | #define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 |
| 5032 | |
| 5033 | /// D0F0x64_x1D |
| 5034 | typedef union { |
| 5035 | struct { ///< |
| 5036 | UINT32 IntGfxAsPcieEn:1 ; ///< |
| 5037 | UINT32 VgaEn:1 ; ///< |
| 5038 | UINT32 Reserved_2_2:1 ; ///< |
| 5039 | UINT32 Vga16En:1 ; ///< |
| 5040 | UINT32 Reserved_31_4:28; ///< |
| 5041 | } Field; ///< |
| 5042 | UINT32 Value; ///< |
| 5043 | } D0F0x64_x1D_STRUCT; |
| 5044 | |
| 5045 | // **** D0F0x64_x20 Register Definition **** |
| 5046 | // Address |
| 5047 | #define D0F0x64_x20_ADDRESS 0x20 |
| 5048 | |
| 5049 | // Type |
| 5050 | #define D0F0x64_x20_TYPE TYPE_D0F0x64 |
| 5051 | // Field Data |
| 5052 | #define D0F0x64_x20_Reserved_0_0_OFFSET 0 |
| 5053 | #define D0F0x64_x20_Reserved_0_0_WIDTH 1 |
| 5054 | #define D0F0x64_x20_Reserved_0_0_MASK 0x1 |
| 5055 | #define D0F0x64_x20_PcieDevRemapDis_OFFSET 1 |
| 5056 | #define D0F0x64_x20_PcieDevRemapDis_WIDTH 1 |
| 5057 | #define D0F0x64_x20_PcieDevRemapDis_MASK 0x2 |
| 5058 | #define D0F0x64_x20_Reserved_31_2_OFFSET 2 |
| 5059 | #define D0F0x64_x20_Reserved_31_2_WIDTH 30 |
| 5060 | #define D0F0x64_x20_Reserved_31_2_MASK 0xfffffffc |
| 5061 | |
| 5062 | /// D0F0x64_x20 |
| 5063 | typedef union { |
| 5064 | struct { ///< |
| 5065 | UINT32 Reserved_0_0:1 ; ///< |
| 5066 | UINT32 PcieDevRemapDis:1 ; ///< |
| 5067 | UINT32 Reserved_31_2:30; ///< |
| 5068 | } Field; ///< |
| 5069 | UINT32 Value; ///< |
| 5070 | } D0F0x64_x20_STRUCT; |
| 5071 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 5072 | // **** D0F0x64_x22 Register Definition **** |
| 5073 | // Address |
| 5074 | #define D0F0x64_x22_ADDRESS 0x22 |
| 5075 | |
| 5076 | // Type |
| 5077 | #define D0F0x64_x22_TYPE TYPE_D0F0x64 |
| 5078 | // Field Data |
| 5079 | #define D0F0x64_x22_Reserved_3_0_OFFSET 0 |
| 5080 | #define D0F0x64_x22_Reserved_3_0_WIDTH 4 |
| 5081 | #define D0F0x64_x22_Reserved_3_0_MASK 0xf |
| 5082 | #define D0F0x64_x22_OffHysteresis_OFFSET 4 |
| 5083 | #define D0F0x64_x22_OffHysteresis_WIDTH 8 |
| 5084 | #define D0F0x64_x22_OffHysteresis_MASK 0xff0 |
| 5085 | #define D0F0x64_x22_Reserved_25_12_OFFSET 12 |
| 5086 | #define D0F0x64_x22_Reserved_25_12_WIDTH 14 |
| 5087 | #define D0F0x64_x22_Reserved_25_12_MASK 0x3fff000 |
| 5088 | #define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 |
| 5089 | #define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 |
| 5090 | #define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 |
| 5091 | #define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 |
| 5092 | #define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 |
| 5093 | #define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 |
| 5094 | #define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 |
| 5095 | #define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 |
| 5096 | #define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 |
| 5097 | #define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 |
| 5098 | #define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 |
| 5099 | #define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 |
| 5100 | #define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 |
| 5101 | #define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 |
| 5102 | #define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 |
| 5103 | #define D0F0x64_x22_Reserved_31_31_OFFSET 31 |
| 5104 | #define D0F0x64_x22_Reserved_31_31_WIDTH 1 |
| 5105 | #define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 |
| 5106 | |
| 5107 | /// D0F0x64_x22 |
| 5108 | typedef union { |
| 5109 | struct { ///< |
| 5110 | UINT32 Reserved_3_0:4 ; ///< |
| 5111 | UINT32 OffHysteresis:8 ; ///< |
| 5112 | UINT32 Reserved_25_12:14; ///< |
| 5113 | UINT32 SoftOverrideClk4:1 ; ///< |
| 5114 | UINT32 SoftOverrideClk3:1 ; ///< |
| 5115 | UINT32 SoftOverrideClk2:1 ; ///< |
| 5116 | UINT32 SoftOverrideClk1:1 ; ///< |
| 5117 | UINT32 SoftOverrideClk0:1 ; ///< |
| 5118 | UINT32 Reserved_31_31:1 ; ///< |
| 5119 | } Field; ///< |
| 5120 | UINT32 Value; ///< |
| 5121 | } D0F0x64_x22_STRUCT; |
| 5122 | |
| 5123 | // **** D0F0x64_x23 Register Definition **** |
| 5124 | // Address |
| 5125 | #define D0F0x64_x23_ADDRESS 0x23 |
| 5126 | |
| 5127 | // Type |
| 5128 | #define D0F0x64_x23_TYPE TYPE_D0F0x64 |
| 5129 | // Field Data |
| 5130 | #define D0F0x64_x23_Reserved_3_0_OFFSET 0 |
| 5131 | #define D0F0x64_x23_Reserved_3_0_WIDTH 4 |
| 5132 | #define D0F0x64_x23_Reserved_3_0_MASK 0xf |
| 5133 | #define D0F0x64_x23_OffHysteresis_OFFSET 4 |
| 5134 | #define D0F0x64_x23_OffHysteresis_WIDTH 8 |
| 5135 | #define D0F0x64_x23_OffHysteresis_MASK 0xff0 |
| 5136 | #define D0F0x64_x23_Reserved_25_12_OFFSET 12 |
| 5137 | #define D0F0x64_x23_Reserved_25_12_WIDTH 14 |
| 5138 | #define D0F0x64_x23_Reserved_25_12_MASK 0x3fff000 |
| 5139 | #define D0F0x64_x23_SoftOverrideClk4_OFFSET 26 |
| 5140 | #define D0F0x64_x23_SoftOverrideClk4_WIDTH 1 |
| 5141 | #define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000 |
| 5142 | #define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 |
| 5143 | #define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 |
| 5144 | #define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 |
| 5145 | #define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 |
| 5146 | #define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 |
| 5147 | #define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 |
| 5148 | #define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 |
| 5149 | #define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 |
| 5150 | #define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 |
| 5151 | #define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 |
| 5152 | #define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 |
| 5153 | #define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 |
| 5154 | #define D0F0x64_x23_Reserved_31_31_OFFSET 31 |
| 5155 | #define D0F0x64_x23_Reserved_31_31_WIDTH 1 |
| 5156 | #define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 |
| 5157 | |
| 5158 | /// D0F0x64_x23 |
| 5159 | typedef union { |
| 5160 | struct { ///< |
| 5161 | UINT32 Reserved_3_0:4 ; ///< |
| 5162 | UINT32 OffHysteresis:8 ; ///< |
| 5163 | UINT32 Reserved_25_12:14; ///< |
| 5164 | UINT32 SoftOverrideClk4:1 ; ///< |
| 5165 | UINT32 SoftOverrideClk3:1 ; ///< |
| 5166 | UINT32 SoftOverrideClk2:1 ; ///< |
| 5167 | UINT32 SoftOverrideClk1:1 ; ///< |
| 5168 | UINT32 SoftOverrideClk0:1 ; ///< |
| 5169 | UINT32 Reserved_31_31:1 ; ///< |
| 5170 | } Field; ///< |
| 5171 | UINT32 Value; ///< |
| 5172 | } D0F0x64_x23_STRUCT; |
| 5173 | |
| 5174 | // **** D0F0x64_x24 Register Definition **** |
| 5175 | // Address |
| 5176 | #define D0F0x64_x24_ADDRESS 0x24 |
| 5177 | |
| 5178 | // Type |
| 5179 | #define D0F0x64_x24_TYPE TYPE_D0F0x64 |
| 5180 | // Field Data |
| 5181 | #define D0F0x64_x24_Reserved_3_0_OFFSET 0 |
| 5182 | #define D0F0x64_x24_Reserved_3_0_WIDTH 4 |
| 5183 | #define D0F0x64_x24_Reserved_3_0_MASK 0xf |
| 5184 | #define D0F0x64_x24_OffHysteresis_OFFSET 4 |
| 5185 | #define D0F0x64_x24_OffHysteresis_WIDTH 8 |
| 5186 | #define D0F0x64_x24_OffHysteresis_MASK 0xff0 |
| 5187 | #define D0F0x64_x24_Reserved_28_12_OFFSET 12 |
| 5188 | #define D0F0x64_x24_Reserved_28_12_WIDTH 17 |
| 5189 | #define D0F0x64_x24_Reserved_28_12_MASK 0x1ffff000 |
| 5190 | #define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 |
| 5191 | #define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 |
| 5192 | #define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 |
| 5193 | #define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 |
| 5194 | #define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 |
| 5195 | #define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 |
| 5196 | #define D0F0x64_x24_Reserved_31_31_OFFSET 31 |
| 5197 | #define D0F0x64_x24_Reserved_31_31_WIDTH 1 |
| 5198 | #define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 |
| 5199 | |
| 5200 | /// D0F0x64_x24 |
| 5201 | typedef union { |
| 5202 | struct { ///< |
| 5203 | UINT32 Reserved_3_0:4 ; ///< |
| 5204 | UINT32 OffHysteresis:8 ; ///< |
| 5205 | UINT32 Reserved_28_12:17; ///< |
| 5206 | UINT32 SoftOverrideClk1:1 ; ///< |
| 5207 | UINT32 SoftOverrideClk0:1 ; ///< |
| 5208 | UINT32 Reserved_31_31:1 ; ///< |
| 5209 | } Field; ///< |
| 5210 | UINT32 Value; ///< |
| 5211 | } D0F0x64_x24_STRUCT; |
| 5212 | |
| 5213 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 5214 | // **** D0F0x64_x46 Register Definition **** |
| 5215 | // Address |
| 5216 | #define D0F0x64_x46_ADDRESS 0x46 |
| 5217 | |
| 5218 | // Type |
| 5219 | #define D0F0x64_x46_TYPE TYPE_D0F0x64 |
| 5220 | // Field Data |
| 5221 | #define D0F0x64_x46_Reserved_0_0_OFFSET 0 |
| 5222 | #define D0F0x64_x46_Reserved_0_0_WIDTH 1 |
| 5223 | #define D0F0x64_x46_Reserved_0_0_MASK 0x1 |
| 5224 | #define D0F0x64_x46_P2PMode_OFFSET 1 |
| 5225 | #define D0F0x64_x46_P2PMode_WIDTH 2 |
| 5226 | #define D0F0x64_x46_P2PMode_MASK 0x6 |
| 5227 | #define D0F0x64_x46_Reserved_15_3_OFFSET 3 |
| 5228 | #define D0F0x64_x46_Reserved_15_3_WIDTH 13 |
| 5229 | #define D0F0x64_x46_Reserved_15_3_MASK 0xfff8 |
| 5230 | #define D0F0x64_x46_Msi64bitEn_OFFSET 16 |
| 5231 | #define D0F0x64_x46_Msi64bitEn_WIDTH 1 |
| 5232 | #define D0F0x64_x46_Msi64bitEn_MASK 0x10000 |
| 5233 | #define D0F0x64_x46_Reserved_31_17_OFFSET 17 |
| 5234 | #define D0F0x64_x46_Reserved_31_17_WIDTH 15 |
| 5235 | #define D0F0x64_x46_Reserved_31_17_MASK 0xfffe0000 |
| 5236 | |
| 5237 | /// D0F0x64_x46 |
| 5238 | typedef union { |
| 5239 | struct { ///< |
| 5240 | UINT32 Reserved_0_0:1 ; ///< |
| 5241 | UINT32 P2PMode:2 ; ///< |
| 5242 | UINT32 Reserved_15_3:13; ///< |
| 5243 | UINT32 Msi64bitEn:1 ; ///< |
| 5244 | UINT32 Reserved_31_17:15; ///< |
| 5245 | } Field; ///< |
| 5246 | UINT32 Value; ///< |
| 5247 | } D0F0x64_x46_STRUCT; |
| 5248 | |
| 5249 | // **** D0F0x64_x4D Register Definition **** |
| 5250 | // Address |
| 5251 | #define D0F0x64_x4D_ADDRESS 0x4d |
| 5252 | |
| 5253 | // Type |
| 5254 | #define D0F0x64_x4D_TYPE TYPE_D0F0x64 |
| 5255 | // Field Data |
| 5256 | #define D0F0x64_x4D_WriteData_OFFSET 0 |
| 5257 | #define D0F0x64_x4D_WriteData_WIDTH 16 |
| 5258 | #define D0F0x64_x4D_WriteData_MASK 0xffff |
| 5259 | #define D0F0x64_x4D_SmuAddr_OFFSET 16 |
| 5260 | #define D0F0x64_x4D_SmuAddr_WIDTH 8 |
| 5261 | #define D0F0x64_x4D_SmuAddr_MASK 0xff0000 |
| 5262 | #define D0F0x64_x4D_ReqToggle_OFFSET 24 |
| 5263 | #define D0F0x64_x4D_ReqToggle_WIDTH 1 |
| 5264 | #define D0F0x64_x4D_ReqToggle_MASK 0x1000000 |
| 5265 | #define D0F0x64_x4D_ReqType_OFFSET 25 |
| 5266 | #define D0F0x64_x4D_ReqType_WIDTH 1 |
| 5267 | #define D0F0x64_x4D_ReqType_MASK 0x2000000 |
| 5268 | #define D0F0x64_x4D_Reserved_31_26_OFFSET 26 |
| 5269 | #define D0F0x64_x4D_Reserved_31_26_WIDTH 6 |
| 5270 | #define D0F0x64_x4D_Reserved_31_26_MASK 0xfc000000 |
| 5271 | |
| 5272 | /// D0F0x64_x4D |
| 5273 | typedef union { |
| 5274 | struct { ///< |
| 5275 | UINT32 WriteData:16; ///< |
| 5276 | UINT32 SmuAddr:8 ; ///< |
| 5277 | UINT32 ReqToggle:1 ; ///< |
| 5278 | UINT32 ReqType:1 ; ///< |
| 5279 | UINT32 Reserved_31_26:6 ; ///< |
| 5280 | } Field; ///< |
| 5281 | UINT32 Value; ///< |
| 5282 | } D0F0x64_x4D_STRUCT; |
| 5283 | |
| 5284 | // **** D0F0x64_x4E Register Definition **** |
| 5285 | // Address |
| 5286 | #define D0F0x64_x4E_ADDRESS 0x4e |
| 5287 | |
| 5288 | // Type |
| 5289 | #define D0F0x64_x4E_TYPE TYPE_D0F0x64 |
| 5290 | // Field Data |
| 5291 | #define D0F0x64_x4E_SmuReadData_OFFSET 0 |
| 5292 | #define D0F0x64_x4E_SmuReadData_WIDTH 32 |
| 5293 | #define D0F0x64_x4E_SmuReadData_MASK 0xffffffff |
| 5294 | |
| 5295 | /// D0F0x64_x4E |
| 5296 | typedef union { |
| 5297 | struct { ///< |
| 5298 | UINT32 SmuReadData:32; ///< |
| 5299 | } Field; ///< |
| 5300 | UINT32 Value; ///< |
| 5301 | } D0F0x64_x4E_STRUCT; |
| 5302 | |
| 5303 | // **** D0F0x64_x55 Register Definition **** |
| 5304 | // Address |
| 5305 | #define D0F0x64_x55_ADDRESS 0x55 |
| 5306 | |
| 5307 | // Type |
| 5308 | #define D0F0x64_x55_TYPE TYPE_D0F0x64 |
| 5309 | // Field Data |
| 5310 | #define D0F0x64_x55_Reserved_19_0_OFFSET 0 |
| 5311 | #define D0F0x64_x55_Reserved_19_0_WIDTH 20 |
| 5312 | #define D0F0x64_x55_Reserved_19_0_MASK 0xfffff |
| 5313 | #define D0F0x64_x55_SetPowEn_OFFSET 20 |
| 5314 | #define D0F0x64_x55_SetPowEn_WIDTH 1 |
| 5315 | #define D0F0x64_x55_SetPowEn_MASK 0x100000 |
| 5316 | #define D0F0x64_x55_Reserved_31_21_OFFSET 21 |
| 5317 | #define D0F0x64_x55_Reserved_31_21_WIDTH 11 |
| 5318 | #define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000 |
| 5319 | |
| 5320 | /// D0F0x64_x55 |
| 5321 | typedef union { |
| 5322 | struct { ///< |
| 5323 | UINT32 Reserved_19_0:20; ///< |
| 5324 | UINT32 SetPowEn:1 ; ///< |
| 5325 | UINT32 Reserved_31_21:11; ///< |
| 5326 | } Field; ///< |
| 5327 | UINT32 Value; ///< |
| 5328 | } D0F0x64_x55_STRUCT; |
| 5329 | |
| 5330 | // **** D0F0x64_x57 Register Definition **** |
| 5331 | // Address |
| 5332 | #define D0F0x64_x57_ADDRESS 0x57 |
| 5333 | |
| 5334 | // Type |
| 5335 | #define D0F0x64_x57_TYPE TYPE_D0F0x64 |
| 5336 | // Field Data |
| 5337 | #define D0F0x64_x57_Reserved_19_0_OFFSET 0 |
| 5338 | #define D0F0x64_x57_Reserved_19_0_WIDTH 20 |
| 5339 | #define D0F0x64_x57_Reserved_19_0_MASK 0xfffff |
| 5340 | #define D0F0x64_x57_SetPowEn_OFFSET 20 |
| 5341 | #define D0F0x64_x57_SetPowEn_WIDTH 1 |
| 5342 | #define D0F0x64_x57_SetPowEn_MASK 0x100000 |
| 5343 | #define D0F0x64_x57_Reserved_31_21_OFFSET 21 |
| 5344 | #define D0F0x64_x57_Reserved_31_21_WIDTH 11 |
| 5345 | #define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000 |
| 5346 | |
| 5347 | /// D0F0x64_x57 |
| 5348 | typedef union { |
| 5349 | struct { ///< |
| 5350 | UINT32 Reserved_19_0:20; ///< |
| 5351 | UINT32 SetPowEn:1 ; ///< |
| 5352 | UINT32 Reserved_31_21:11; ///< |
| 5353 | } Field; ///< |
| 5354 | UINT32 Value; ///< |
| 5355 | } D0F0x64_x57_STRUCT; |
| 5356 | |
| 5357 | // **** D0F0x64_x59 Register Definition **** |
| 5358 | // Address |
| 5359 | #define D0F0x64_x59_ADDRESS 0x59 |
| 5360 | |
| 5361 | // Type |
| 5362 | #define D0F0x64_x59_TYPE TYPE_D0F0x64 |
| 5363 | // Field Data |
| 5364 | #define D0F0x64_x59_Reserved_19_0_OFFSET 0 |
| 5365 | #define D0F0x64_x59_Reserved_19_0_WIDTH 20 |
| 5366 | #define D0F0x64_x59_Reserved_19_0_MASK 0xfffff |
| 5367 | #define D0F0x64_x59_SetPowEn_OFFSET 20 |
| 5368 | #define D0F0x64_x59_SetPowEn_WIDTH 1 |
| 5369 | #define D0F0x64_x59_SetPowEn_MASK 0x100000 |
| 5370 | #define D0F0x64_x59_Reserved_31_21_OFFSET 21 |
| 5371 | #define D0F0x64_x59_Reserved_31_21_WIDTH 11 |
| 5372 | #define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000 |
| 5373 | |
| 5374 | /// D0F0x64_x59 |
| 5375 | typedef union { |
| 5376 | struct { ///< |
| 5377 | UINT32 Reserved_19_0:20; ///< |
| 5378 | UINT32 SetPowEn:1 ; ///< |
| 5379 | UINT32 Reserved_31_21:11; ///< |
| 5380 | } Field; ///< |
| 5381 | UINT32 Value; ///< |
| 5382 | } D0F0x64_x59_STRUCT; |
| 5383 | |
| 5384 | // **** D0F0x64_x5B Register Definition **** |
| 5385 | // Address |
| 5386 | #define D0F0x64_x5B_ADDRESS 0x5b |
| 5387 | |
| 5388 | // Type |
| 5389 | #define D0F0x64_x5B_TYPE TYPE_D0F0x64 |
| 5390 | // Field Data |
| 5391 | #define D0F0x64_x5B_Reserved_19_0_OFFSET 0 |
| 5392 | #define D0F0x64_x5B_Reserved_19_0_WIDTH 20 |
| 5393 | #define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff |
| 5394 | #define D0F0x64_x5B_SetPowEn_OFFSET 20 |
| 5395 | #define D0F0x64_x5B_SetPowEn_WIDTH 1 |
| 5396 | #define D0F0x64_x5B_SetPowEn_MASK 0x100000 |
| 5397 | #define D0F0x64_x5B_Reserved_31_21_OFFSET 21 |
| 5398 | #define D0F0x64_x5B_Reserved_31_21_WIDTH 11 |
| 5399 | #define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000 |
| 5400 | |
| 5401 | /// D0F0x64_x5B |
| 5402 | typedef union { |
| 5403 | struct { ///< |
| 5404 | UINT32 Reserved_19_0:20; ///< |
| 5405 | UINT32 SetPowEn:1 ; ///< |
| 5406 | UINT32 Reserved_31_21:11; ///< |
| 5407 | } Field; ///< |
| 5408 | UINT32 Value; ///< |
| 5409 | } D0F0x64_x5B_STRUCT; |
| 5410 | |
| 5411 | // **** D0F0x64_x6A Register Definition **** |
| 5412 | // Address |
| 5413 | #define D0F0x64_x6A_ADDRESS 0x6a |
| 5414 | |
| 5415 | // Type |
| 5416 | #define D0F0x64_x6A_TYPE TYPE_D0F0x64 |
| 5417 | // Field Data |
| 5418 | #define D0F0x64_x6A_VoltageForceEn_OFFSET 0 |
| 5419 | #define D0F0x64_x6A_VoltageForceEn_WIDTH 1 |
| 5420 | #define D0F0x64_x6A_VoltageForceEn_MASK 0x1 |
| 5421 | #define D0F0x64_x6A_VoltageChangeEn_OFFSET 1 |
| 5422 | #define D0F0x64_x6A_VoltageChangeEn_WIDTH 1 |
| 5423 | #define D0F0x64_x6A_VoltageChangeEn_MASK 0x2 |
| 5424 | #define D0F0x64_x6A_VoltageChangeReq_OFFSET 2 |
| 5425 | #define D0F0x64_x6A_VoltageChangeReq_WIDTH 1 |
| 5426 | #define D0F0x64_x6A_VoltageChangeReq_MASK 0x4 |
| 5427 | #define D0F0x64_x6A_VoltageLevel_OFFSET 3 |
| 5428 | #define D0F0x64_x6A_VoltageLevel_WIDTH 2 |
| 5429 | #define D0F0x64_x6A_VoltageLevel_MASK 0x18 |
| 5430 | #define D0F0x64_x6A_Reserved_31_5_OFFSET 5 |
| 5431 | #define D0F0x64_x6A_Reserved_31_5_WIDTH 27 |
| 5432 | #define D0F0x64_x6A_Reserved_31_5_MASK 0xffffffe0 |
| 5433 | |
| 5434 | /// D0F0x64_x6A |
| 5435 | typedef union { |
| 5436 | struct { ///< |
| 5437 | UINT32 VoltageForceEn:1 ; ///< |
| 5438 | UINT32 VoltageChangeEn:1 ; ///< |
| 5439 | UINT32 VoltageChangeReq:1 ; ///< |
| 5440 | UINT32 VoltageLevel:2 ; ///< |
| 5441 | UINT32 Reserved_31_5:27; ///< |
| 5442 | } Field; ///< |
| 5443 | UINT32 Value; ///< |
| 5444 | } D0F0x64_x6A_STRUCT; |
| 5445 | |
| 5446 | // **** D0F0x64_x6B Register Definition **** |
| 5447 | // Address |
| 5448 | #define D0F0x64_x6B_ADDRESS 0x6b |
| 5449 | |
| 5450 | // Type |
| 5451 | #define D0F0x64_x6B_TYPE TYPE_D0F0x64 |
| 5452 | // Field Data |
| 5453 | #define D0F0x64_x6B_VoltageChangeAck_OFFSET 0 |
| 5454 | #define D0F0x64_x6B_VoltageChangeAck_WIDTH 1 |
| 5455 | #define D0F0x64_x6B_VoltageChangeAck_MASK 0x1 |
| 5456 | #define D0F0x64_x6B_CurrentVoltageLevel_OFFSET 1 |
| 5457 | #define D0F0x64_x6B_CurrentVoltageLevel_WIDTH 2 |
| 5458 | #define D0F0x64_x6B_CurrentVoltageLevel_MASK 0x6 |
| 5459 | #define D0F0x64_x6B_Reserved_31_3_OFFSET 3 |
| 5460 | #define D0F0x64_x6B_Reserved_31_3_WIDTH 29 |
| 5461 | #define D0F0x64_x6B_Reserved_31_3_MASK 0xfffffff8 |
| 5462 | |
| 5463 | /// D0F0x64_x6B |
| 5464 | typedef union { |
| 5465 | struct { ///< |
| 5466 | UINT32 VoltageChangeAck:1 ; ///< |
| 5467 | UINT32 CurrentVoltageLevel:2 ; ///< |
| 5468 | UINT32 Reserved_31_3:29; ///< |
| 5469 | } Field; ///< |
| 5470 | UINT32 Value; ///< |
| 5471 | } D0F0x64_x6B_STRUCT; |
| 5472 | |
| 5473 | // **** D0F0x98_x06 Register Definition **** |
| 5474 | // Address |
| 5475 | #define D0F0x98_x06_ADDRESS 0x6 |
| 5476 | |
| 5477 | // Type |
| 5478 | #define D0F0x98_x06_TYPE TYPE_D0F0x98 |
| 5479 | // Field Data |
| 5480 | #define D0F0x98_x06_Reserved_25_0_OFFSET 0 |
| 5481 | #define D0F0x98_x06_Reserved_25_0_WIDTH 26 |
| 5482 | #define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff |
| 5483 | #define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 |
| 5484 | #define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 |
| 5485 | #define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 |
| 5486 | #define D0F0x98_x06_Reserved_31_27_OFFSET 27 |
| 5487 | #define D0F0x98_x06_Reserved_31_27_WIDTH 5 |
| 5488 | #define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 |
| 5489 | |
| 5490 | /// D0F0x98_x06 |
| 5491 | typedef union { |
| 5492 | struct { ///< |
| 5493 | UINT32 Reserved_25_0:26; ///< |
| 5494 | UINT32 UmiNpMemWrEn:1 ; ///< |
| 5495 | UINT32 Reserved_31_27:5 ; ///< |
| 5496 | } Field; ///< |
| 5497 | UINT32 Value; ///< |
| 5498 | } D0F0x98_x06_STRUCT; |
| 5499 | |
| 5500 | // **** D0F0x98_x07 Register Definition **** |
| 5501 | // Address |
| 5502 | #define D0F0x98_x07_ADDRESS 0x7 |
| 5503 | |
| 5504 | // Type |
| 5505 | #define D0F0x98_x07_TYPE TYPE_D0F0x98 |
| 5506 | // Field Data |
| 5507 | #define D0F0x98_x07_IocBwOptEn_OFFSET 0 |
| 5508 | #define D0F0x98_x07_IocBwOptEn_WIDTH 1 |
| 5509 | #define D0F0x98_x07_IocBwOptEn_MASK 0x1 |
| 5510 | #define D0F0x98_x07_Reserved_13_1_OFFSET 1 |
| 5511 | #define D0F0x98_x07_Reserved_13_1_WIDTH 13 |
| 5512 | #define D0F0x98_x07_Reserved_13_1_MASK 0x3ffe |
| 5513 | #define D0F0x98_x07_MSIHTIntConversionEn_OFFSET 14 |
| 5514 | #define D0F0x98_x07_MSIHTIntConversionEn_WIDTH 1 |
| 5515 | #define D0F0x98_x07_MSIHTIntConversionEn_MASK 0x4000 |
| 5516 | #define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15 |
| 5517 | #define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1 |
| 5518 | #define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000 |
| 5519 | #define D0F0x98_x07_Reserved_31_16_OFFSET 16 |
| 5520 | #define D0F0x98_x07_Reserved_31_16_WIDTH 16 |
| 5521 | #define D0F0x98_x07_Reserved_31_16_MASK 0xffff0000 |
| 5522 | |
| 5523 | /// D0F0x98_x07 |
| 5524 | typedef union { |
| 5525 | struct { ///< |
| 5526 | UINT32 IocBwOptEn:1 ; ///< |
| 5527 | UINT32 Reserved_13_1:13; ///< |
| 5528 | UINT32 MSIHTIntConversionEn:1 ; ///< |
| 5529 | UINT32 DropZeroMaskWrEn:1 ; ///< |
| 5530 | UINT32 Reserved_31_16:16; ///< |
| 5531 | } Field; ///< |
| 5532 | UINT32 Value; ///< |
| 5533 | } D0F0x98_x07_STRUCT; |
| 5534 | |
| 5535 | // **** D0F0x98_x08 Register Definition **** |
| 5536 | // Address |
| 5537 | #define D0F0x98_x08_ADDRESS 0x8 |
| 5538 | |
| 5539 | // Type |
| 5540 | #define D0F0x98_x08_TYPE TYPE_D0F0x98 |
| 5541 | // Field Data |
| 5542 | #define D0F0x98_x08_NpWrrLenA_OFFSET 0 |
| 5543 | #define D0F0x98_x08_NpWrrLenA_WIDTH 8 |
| 5544 | #define D0F0x98_x08_NpWrrLenA_MASK 0xff |
| 5545 | #define D0F0x98_x08_Reserved_15_8_OFFSET 8 |
| 5546 | #define D0F0x98_x08_Reserved_15_8_WIDTH 8 |
| 5547 | #define D0F0x98_x08_Reserved_15_8_MASK 0xff00 |
| 5548 | #define D0F0x98_x08_NpWrrLenC_OFFSET 16 |
| 5549 | #define D0F0x98_x08_NpWrrLenC_WIDTH 8 |
| 5550 | #define D0F0x98_x08_NpWrrLenC_MASK 0xff0000 |
| 5551 | #define D0F0x98_x08_Reserved_31_24_OFFSET 24 |
| 5552 | #define D0F0x98_x08_Reserved_31_24_WIDTH 8 |
| 5553 | #define D0F0x98_x08_Reserved_31_24_MASK 0xff000000 |
| 5554 | |
| 5555 | /// D0F0x98_x08 |
| 5556 | typedef union { |
| 5557 | struct { ///< |
| 5558 | UINT32 NpWrrLenA:8 ; ///< |
| 5559 | UINT32 Reserved_15_8:8 ; ///< |
| 5560 | UINT32 NpWrrLenC:8 ; ///< |
| 5561 | UINT32 Reserved_31_24:8 ; ///< |
| 5562 | } Field; ///< |
| 5563 | UINT32 Value; ///< |
| 5564 | } D0F0x98_x08_STRUCT; |
| 5565 | |
| 5566 | // **** D0F0x98_x09 Register Definition **** |
| 5567 | // Address |
| 5568 | #define D0F0x98_x09_ADDRESS 0x9 |
| 5569 | |
| 5570 | // Type |
| 5571 | #define D0F0x98_x09_TYPE TYPE_D0F0x98 |
| 5572 | // Field Data |
| 5573 | #define D0F0x98_x09_PWrrLenA_OFFSET 0 |
| 5574 | #define D0F0x98_x09_PWrrLenA_WIDTH 8 |
| 5575 | #define D0F0x98_x09_PWrrLenA_MASK 0xff |
| 5576 | #define D0F0x98_x09_Reserved_23_8_OFFSET 8 |
| 5577 | #define D0F0x98_x09_Reserved_23_8_WIDTH 16 |
| 5578 | #define D0F0x98_x09_Reserved_23_8_MASK 0xffff00 |
| 5579 | #define D0F0x98_x09_PWrrLenD_OFFSET 24 |
| 5580 | #define D0F0x98_x09_PWrrLenD_WIDTH 8 |
| 5581 | #define D0F0x98_x09_PWrrLenD_MASK 0xff000000 |
| 5582 | |
| 5583 | /// D0F0x98_x09 |
| 5584 | typedef union { |
| 5585 | struct { ///< |
| 5586 | UINT32 PWrrLenA:8 ; ///< |
| 5587 | UINT32 Reserved_23_8:16; ///< |
| 5588 | UINT32 PWrrLenD:8 ; ///< |
| 5589 | } Field; ///< |
| 5590 | UINT32 Value; ///< |
| 5591 | } D0F0x98_x09_STRUCT; |
| 5592 | |
| 5593 | // **** D0F0x98_x0C Register Definition **** |
| 5594 | // Address |
| 5595 | #define D0F0x98_x0C_ADDRESS 0xc |
| 5596 | |
| 5597 | // Type |
| 5598 | #define D0F0x98_x0C_TYPE TYPE_D0F0x98 |
| 5599 | // Field Data |
| 5600 | #define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 |
| 5601 | #define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 |
| 5602 | #define D0F0x98_x0C_GcmWrrLenA_MASK 0xff |
| 5603 | #define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 |
| 5604 | #define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 |
| 5605 | #define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00 |
| 5606 | #define D0F0x98_x0C_Reserved_29_16_OFFSET 16 |
| 5607 | #define D0F0x98_x0C_Reserved_29_16_WIDTH 14 |
| 5608 | #define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000 |
| 5609 | #define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30 |
| 5610 | #define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1 |
| 5611 | #define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000 |
| 5612 | #define D0F0x98_x0C_Reserved_31_31_OFFSET 31 |
| 5613 | #define D0F0x98_x0C_Reserved_31_31_WIDTH 1 |
| 5614 | #define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000 |
| 5615 | |
| 5616 | /// D0F0x98_x0C |
| 5617 | typedef union { |
| 5618 | struct { ///< |
| 5619 | UINT32 GcmWrrLenA:8 ; ///< |
| 5620 | UINT32 GcmWrrLenB:8 ; ///< |
| 5621 | UINT32 Reserved_29_16:14; ///< |
| 5622 | UINT32 StrictSelWinnerEn:1 ; ///< |
| 5623 | UINT32 Reserved_31_31:1 ; ///< |
| 5624 | } Field; ///< |
| 5625 | UINT32 Value; ///< |
| 5626 | } D0F0x98_x0C_STRUCT; |
| 5627 | |
| 5628 | // **** D0F0x98_x0E Register Definition **** |
| 5629 | // Address |
| 5630 | #define D0F0x98_x0E_ADDRESS 0xe |
| 5631 | |
| 5632 | // Type |
| 5633 | #define D0F0x98_x0E_TYPE TYPE_D0F0x98 |
| 5634 | // Field Data |
| 5635 | #define D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET 0 |
| 5636 | #define D0F0x98_x0E_MsiHtRsvIntRemapEn_WIDTH 1 |
| 5637 | #define D0F0x98_x0E_MsiHtRsvIntRemapEn_MASK 0x1 |
| 5638 | #define D0F0x98_x0E_Reserved_1_1_OFFSET 1 |
| 5639 | #define D0F0x98_x0E_Reserved_1_1_WIDTH 1 |
| 5640 | #define D0F0x98_x0E_Reserved_1_1_MASK 0x2 |
| 5641 | #define D0F0x98_x0E_MsiHtRsvIntMt_OFFSET 2 |
| 5642 | #define D0F0x98_x0E_MsiHtRsvIntMt_WIDTH 3 |
| 5643 | #define D0F0x98_x0E_MsiHtRsvIntMt_MASK 0x1c |
| 5644 | #define D0F0x98_x0E_MsiHtRsvIntRqEoi_OFFSET 5 |
| 5645 | #define D0F0x98_x0E_MsiHtRsvIntRqEoi_WIDTH 1 |
| 5646 | #define D0F0x98_x0E_MsiHtRsvIntRqEoi_MASK 0x20 |
| 5647 | #define D0F0x98_x0E_MsiHtRsvIntDM_OFFSET 6 |
| 5648 | #define D0F0x98_x0E_MsiHtRsvIntDM_WIDTH 1 |
| 5649 | #define D0F0x98_x0E_MsiHtRsvIntDM_MASK 0x40 |
| 5650 | #define D0F0x98_x0E_Reserved_7_7_OFFSET 7 |
| 5651 | #define D0F0x98_x0E_Reserved_7_7_WIDTH 1 |
| 5652 | #define D0F0x98_x0E_Reserved_7_7_MASK 0x80 |
| 5653 | #define D0F0x98_x0E_MsiHtRsvIntDestination_OFFSET 8 |
| 5654 | #define D0F0x98_x0E_MsiHtRsvIntDestination_WIDTH 8 |
| 5655 | #define D0F0x98_x0E_MsiHtRsvIntDestination_MASK 0xff00 |
| 5656 | #define D0F0x98_x0E_MsiHtRsvIntVector_OFFSET 16 |
| 5657 | #define D0F0x98_x0E_MsiHtRsvIntVector_WIDTH 8 |
| 5658 | #define D0F0x98_x0E_MsiHtRsvIntVector_MASK 0xff0000 |
| 5659 | #define D0F0x98_x0E_Reserved_31_24_OFFSET 24 |
| 5660 | #define D0F0x98_x0E_Reserved_31_24_WIDTH 8 |
| 5661 | #define D0F0x98_x0E_Reserved_31_24_MASK 0xff000000 |
| 5662 | |
| 5663 | /// D0F0x98_x0E |
| 5664 | typedef union { |
| 5665 | struct { ///< |
| 5666 | UINT32 MsiHtRsvIntRemapEn:1 ; ///< |
| 5667 | UINT32 Reserved_1_1:1 ; ///< |
| 5668 | UINT32 MsiHtRsvIntMt:3 ; ///< |
| 5669 | UINT32 MsiHtRsvIntRqEoi:1 ; ///< |
| 5670 | UINT32 MsiHtRsvIntDM:1 ; ///< |
| 5671 | UINT32 Reserved_7_7:1 ; ///< |
| 5672 | UINT32 MsiHtRsvIntDestination:8 ; ///< |
| 5673 | UINT32 MsiHtRsvIntVector:8 ; ///< |
| 5674 | UINT32 Reserved_31_24:8 ; ///< |
| 5675 | } Field; ///< |
| 5676 | UINT32 Value; ///< |
| 5677 | } D0F0x98_x0E_STRUCT; |
| 5678 | |
| 5679 | // **** D0F0x98_x1E Register Definition **** |
| 5680 | // Address |
| 5681 | #define D0F0x98_x1E_ADDRESS 0x1e |
| 5682 | |
| 5683 | // Type |
| 5684 | #define D0F0x98_x1E_TYPE TYPE_D0F0x98 |
| 5685 | // Field Data |
| 5686 | #define D0F0x98_x1E_Reserved_0_0_OFFSET 0 |
| 5687 | #define D0F0x98_x1E_Reserved_0_0_WIDTH 1 |
| 5688 | #define D0F0x98_x1E_Reserved_0_0_MASK 0x1 |
| 5689 | #define D0F0x98_x1E_HiPriEn_OFFSET 1 |
| 5690 | #define D0F0x98_x1E_HiPriEn_WIDTH 1 |
| 5691 | #define D0F0x98_x1E_HiPriEn_MASK 0x2 |
| 5692 | #define D0F0x98_x1E_Reserved_31_2_OFFSET 2 |
| 5693 | #define D0F0x98_x1E_Reserved_31_2_WIDTH 30 |
| 5694 | #define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc |
| 5695 | |
| 5696 | /// D0F0x98_x1E |
| 5697 | typedef union { |
| 5698 | struct { ///< |
| 5699 | UINT32 Reserved_0_0:1 ; ///< |
| 5700 | UINT32 HiPriEn:1 ; ///< |
| 5701 | UINT32 Reserved_31_2:30; ///< |
| 5702 | } Field; ///< |
| 5703 | UINT32 Value; ///< |
| 5704 | } D0F0x98_x1E_STRUCT; |
| 5705 | |
| 5706 | // **** D0F0x98_x28 Register Definition **** |
| 5707 | // Address |
| 5708 | #define D0F0x98_x28_ADDRESS 0x28 |
| 5709 | |
| 5710 | // Type |
| 5711 | #define D0F0x98_x28_TYPE TYPE_D0F0x98 |
| 5712 | // Field Data |
| 5713 | #define D0F0x98_x28_SmuPmInterfaceEn_OFFSET 0 |
| 5714 | #define D0F0x98_x28_SmuPmInterfaceEn_WIDTH 1 |
| 5715 | #define D0F0x98_x28_SmuPmInterfaceEn_MASK 0x1 |
| 5716 | #define D0F0x98_x28_ForceCoherentIntr_OFFSET 1 |
| 5717 | #define D0F0x98_x28_ForceCoherentIntr_WIDTH 1 |
| 5718 | #define D0F0x98_x28_ForceCoherentIntr_MASK 0x2 |
| 5719 | #define D0F0x98_x28_Reserved_31_2_OFFSET 2 |
| 5720 | #define D0F0x98_x28_Reserved_31_2_WIDTH 30 |
| 5721 | #define D0F0x98_x28_Reserved_31_2_MASK 0xfffffffc |
| 5722 | |
| 5723 | /// D0F0x98_x28 |
| 5724 | typedef union { |
| 5725 | struct { ///< |
| 5726 | UINT32 SmuPmInterfaceEn:1 ; ///< |
| 5727 | UINT32 ForceCoherentIntr:1 ; ///< |
| 5728 | UINT32 Reserved_31_2:30; ///< |
| 5729 | } Field; ///< |
| 5730 | UINT32 Value; ///< |
| 5731 | } D0F0x98_x28_STRUCT; |
| 5732 | |
| 5733 | // **** D0F0x98_x2C Register Definition **** |
| 5734 | // Address |
| 5735 | #define D0F0x98_x2C_ADDRESS 0x2c |
| 5736 | |
| 5737 | // Type |
| 5738 | #define D0F0x98_x2C_TYPE TYPE_D0F0x98 |
| 5739 | // Field Data |
| 5740 | #define D0F0x98_x2C_Reserved_0_0_OFFSET 0 |
| 5741 | #define D0F0x98_x2C_Reserved_0_0_WIDTH 1 |
| 5742 | #define D0F0x98_x2C_Reserved_0_0_MASK 0x1 |
| 5743 | #define D0F0x98_x2C_DynWakeEn_OFFSET 1 |
| 5744 | #define D0F0x98_x2C_DynWakeEn_WIDTH 1 |
| 5745 | #define D0F0x98_x2C_DynWakeEn_MASK 0x2 |
| 5746 | #define D0F0x98_x2C_Reserved_15_2_OFFSET 2 |
| 5747 | #define D0F0x98_x2C_Reserved_15_2_WIDTH 14 |
| 5748 | #define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc |
| 5749 | #define D0F0x98_x2C_WakeHysteresis_OFFSET 16 |
| 5750 | #define D0F0x98_x2C_WakeHysteresis_WIDTH 16 |
| 5751 | #define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000 |
| 5752 | |
| 5753 | /// D0F0x98_x2C |
| 5754 | typedef union { |
| 5755 | struct { ///< |
| 5756 | UINT32 Reserved_0_0:1 ; ///< |
| 5757 | UINT32 DynWakeEn:1 ; ///< |
| 5758 | UINT32 Reserved_15_2:14; ///< |
| 5759 | UINT32 WakeHysteresis:16; ///< |
| 5760 | } Field; ///< |
| 5761 | UINT32 Value; ///< |
| 5762 | } D0F0x98_x2C_STRUCT; |
| 5763 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 5764 | // **** D0F0x98_x49 Register Definition **** |
| 5765 | // Address |
| 5766 | #define D0F0x98_x49_ADDRESS 0x49 |
| 5767 | |
| 5768 | // Type |
| 5769 | #define D0F0x98_x49_TYPE TYPE_D0F0x98 |
| 5770 | // Field Data |
| 5771 | #define D0F0x98_x49_Reserved_3_0_OFFSET 0 |
| 5772 | #define D0F0x98_x49_Reserved_3_0_WIDTH 4 |
| 5773 | #define D0F0x98_x49_Reserved_3_0_MASK 0xf |
| 5774 | #define D0F0x98_x49_OffHysteresis_OFFSET 4 |
| 5775 | #define D0F0x98_x49_OffHysteresis_WIDTH 8 |
| 5776 | #define D0F0x98_x49_OffHysteresis_MASK 0xff0 |
| 5777 | #define D0F0x98_x49_Reserved_23_12_OFFSET 12 |
| 5778 | #define D0F0x98_x49_Reserved_23_12_WIDTH 12 |
| 5779 | #define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 |
| 5780 | #define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 |
| 5781 | #define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 |
| 5782 | #define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 |
| 5783 | #define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 |
| 5784 | #define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 |
| 5785 | #define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 |
| 5786 | #define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 |
| 5787 | #define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 |
| 5788 | #define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 |
| 5789 | #define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 |
| 5790 | #define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 |
| 5791 | #define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 |
| 5792 | #define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 |
| 5793 | #define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 |
| 5794 | #define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 |
| 5795 | #define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 |
| 5796 | #define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 |
| 5797 | #define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 |
| 5798 | #define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 |
| 5799 | #define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 |
| 5800 | #define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 |
| 5801 | #define D0F0x98_x49_Reserved_31_31_OFFSET 31 |
| 5802 | #define D0F0x98_x49_Reserved_31_31_WIDTH 1 |
| 5803 | #define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 |
| 5804 | |
| 5805 | /// D0F0x98_x49 |
| 5806 | typedef union { |
| 5807 | struct { ///< |
| 5808 | UINT32 Reserved_3_0:4 ; ///< |
| 5809 | UINT32 OffHysteresis:8 ; ///< |
| 5810 | UINT32 Reserved_23_12:12; ///< |
| 5811 | UINT32 SoftOverrideClk6:1 ; ///< |
| 5812 | UINT32 SoftOverrideClk5:1 ; ///< |
| 5813 | UINT32 SoftOverrideClk4:1 ; ///< |
| 5814 | UINT32 SoftOverrideClk3:1 ; ///< |
| 5815 | UINT32 SoftOverrideClk2:1 ; ///< |
| 5816 | UINT32 SoftOverrideClk1:1 ; ///< |
| 5817 | UINT32 SoftOverrideClk0:1 ; ///< |
| 5818 | UINT32 Reserved_31_31:1 ; ///< |
| 5819 | } Field; ///< |
| 5820 | UINT32 Value; ///< |
| 5821 | } D0F0x98_x49_STRUCT; |
| 5822 | |
| 5823 | // **** D0F0x98_x4A Register Definition **** |
| 5824 | // Address |
| 5825 | #define D0F0x98_x4A_ADDRESS 0x4a |
| 5826 | |
| 5827 | // Type |
| 5828 | #define D0F0x98_x4A_TYPE TYPE_D0F0x98 |
| 5829 | // Field Data |
| 5830 | #define D0F0x98_x4A_Reserved_3_0_OFFSET 0 |
| 5831 | #define D0F0x98_x4A_Reserved_3_0_WIDTH 4 |
| 5832 | #define D0F0x98_x4A_Reserved_3_0_MASK 0xf |
| 5833 | #define D0F0x98_x4A_OffHysteresis_OFFSET 4 |
| 5834 | #define D0F0x98_x4A_OffHysteresis_WIDTH 8 |
| 5835 | #define D0F0x98_x4A_OffHysteresis_MASK 0xff0 |
| 5836 | #define D0F0x98_x4A_Reserved_23_12_OFFSET 12 |
| 5837 | #define D0F0x98_x4A_Reserved_23_12_WIDTH 12 |
| 5838 | #define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 |
| 5839 | #define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 |
| 5840 | #define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 |
| 5841 | #define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 |
| 5842 | #define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 |
| 5843 | #define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 |
| 5844 | #define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 |
| 5845 | #define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 |
| 5846 | #define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 |
| 5847 | #define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 |
| 5848 | #define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 |
| 5849 | #define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 |
| 5850 | #define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 |
| 5851 | #define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 |
| 5852 | #define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 |
| 5853 | #define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 |
| 5854 | #define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 |
| 5855 | #define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 |
| 5856 | #define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 |
| 5857 | #define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 |
| 5858 | #define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 |
| 5859 | #define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 |
| 5860 | #define D0F0x98_x4A_Reserved_31_31_OFFSET 31 |
| 5861 | #define D0F0x98_x4A_Reserved_31_31_WIDTH 1 |
| 5862 | #define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 |
| 5863 | |
| 5864 | /// D0F0x98_x4A |
| 5865 | typedef union { |
| 5866 | struct { ///< |
| 5867 | UINT32 Reserved_3_0:4 ; ///< |
| 5868 | UINT32 OffHysteresis:8 ; ///< |
| 5869 | UINT32 Reserved_23_12:12; ///< |
| 5870 | UINT32 SoftOverrideClk6:1 ; ///< |
| 5871 | UINT32 SoftOverrideClk5:1 ; ///< |
| 5872 | UINT32 SoftOverrideClk4:1 ; ///< |
| 5873 | UINT32 SoftOverrideClk3:1 ; ///< |
| 5874 | UINT32 SoftOverrideClk2:1 ; ///< |
| 5875 | UINT32 SoftOverrideClk1:1 ; ///< |
| 5876 | UINT32 SoftOverrideClk0:1 ; ///< |
| 5877 | UINT32 Reserved_31_31:1 ; ///< |
| 5878 | } Field; ///< |
| 5879 | UINT32 Value; ///< |
| 5880 | } D0F0x98_x4A_STRUCT; |
| 5881 | |
| 5882 | // **** D0F0x98_x4B Register Definition **** |
| 5883 | // Address |
| 5884 | #define D0F0x98_x4B_ADDRESS 0x4b |
| 5885 | |
| 5886 | // Type |
| 5887 | #define D0F0x98_x4B_TYPE TYPE_D0F0x98 |
| 5888 | // Field Data |
| 5889 | #define D0F0x98_x4B_Reserved_3_0_OFFSET 0 |
| 5890 | #define D0F0x98_x4B_Reserved_3_0_WIDTH 4 |
| 5891 | #define D0F0x98_x4B_Reserved_3_0_MASK 0xf |
| 5892 | #define D0F0x98_x4B_OffHysteresis_OFFSET 4 |
| 5893 | #define D0F0x98_x4B_OffHysteresis_WIDTH 8 |
| 5894 | #define D0F0x98_x4B_OffHysteresis_MASK 0xff0 |
| 5895 | #define D0F0x98_x4B_Reserved_29_12_OFFSET 12 |
| 5896 | #define D0F0x98_x4B_Reserved_29_12_WIDTH 18 |
| 5897 | #define D0F0x98_x4B_Reserved_29_12_MASK 0x3ffff000 |
| 5898 | #define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 |
| 5899 | #define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 |
| 5900 | #define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 |
| 5901 | #define D0F0x98_x4B_Reserved_31_31_OFFSET 31 |
| 5902 | #define D0F0x98_x4B_Reserved_31_31_WIDTH 1 |
| 5903 | #define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 |
| 5904 | |
| 5905 | /// D0F0x98_x4B |
| 5906 | typedef union { |
| 5907 | struct { ///< |
| 5908 | UINT32 Reserved_3_0:4 ; ///< |
| 5909 | UINT32 OffHysteresis:8 ; ///< |
| 5910 | UINT32 Reserved_29_12:18; ///< |
| 5911 | UINT32 SoftOverrideClk:1 ; ///< |
| 5912 | UINT32 Reserved_31_31:1 ; ///< |
| 5913 | } Field; ///< |
| 5914 | UINT32 Value; ///< |
| 5915 | } D0F0x98_x4B_STRUCT; |
| 5916 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 5917 | // **** D0F0xE4_WRAP_0080 Register Definition **** |
| 5918 | // Address |
| 5919 | #define D0F0xE4_WRAP_0080_ADDRESS 0x80 |
| 5920 | |
| 5921 | // Type |
| 5922 | #define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 |
| 5923 | // Field Data |
| 5924 | #define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 |
| 5925 | #define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 |
| 5926 | #define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf |
| 5927 | #define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 |
| 5928 | #define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 |
| 5929 | #define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 |
| 5930 | |
| 5931 | /// D0F0xE4_WRAP_0080 |
| 5932 | typedef union { |
| 5933 | struct { ///< |
| 5934 | UINT32 StrapBifLinkConfig:4 ; ///< |
| 5935 | UINT32 Reserved_31_4:28; ///< |
| 5936 | } Field; ///< |
| 5937 | UINT32 Value; ///< |
| 5938 | } D0F0xE4_WRAP_0080_STRUCT; |
| 5939 | |
| 5940 | // **** D0F0xE4_WRAP_0800 Register Definition **** |
| 5941 | // Address |
| 5942 | #define D0F0xE4_WRAP_0800_ADDRESS 0x800 |
| 5943 | |
| 5944 | // Type |
| 5945 | #define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 |
| 5946 | // Field Data |
| 5947 | #define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 |
| 5948 | #define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 |
| 5949 | #define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 |
| 5950 | #define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 |
| 5951 | #define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 |
| 5952 | #define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe |
| 5953 | |
| 5954 | /// D0F0xE4_WRAP_0800 |
| 5955 | typedef union { |
| 5956 | struct { ///< |
| 5957 | UINT32 HoldTraining:1 ; ///< |
| 5958 | UINT32 Reserved_31_1:31; ///< |
| 5959 | } Field; ///< |
| 5960 | UINT32 Value; ///< |
| 5961 | } D0F0xE4_WRAP_0800_STRUCT; |
| 5962 | |
| 5963 | // **** D0F0xE4_WRAP_0803 Register Definition **** |
| 5964 | // Address |
| 5965 | #define D0F0xE4_WRAP_0803_ADDRESS 0x803 |
| 5966 | |
| 5967 | // Type |
| 5968 | #define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 |
| 5969 | // Field Data |
| 5970 | #define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 |
| 5971 | #define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 |
| 5972 | #define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f |
| 5973 | #define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 |
| 5974 | #define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 |
| 5975 | #define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 |
| 5976 | #define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 |
| 5977 | #define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 |
| 5978 | #define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 |
| 5979 | |
| 5980 | /// D0F0xE4_WRAP_0803 |
| 5981 | typedef union { |
| 5982 | struct { ///< |
| 5983 | UINT32 Reserved_4_0:5 ; ///< |
| 5984 | UINT32 StrapBifDeemphasisSel:1 ; ///< |
| 5985 | UINT32 Reserved_31_6:26; ///< |
| 5986 | } Field; ///< |
| 5987 | UINT32 Value; ///< |
| 5988 | } D0F0xE4_WRAP_0803_STRUCT; |
| 5989 | |
| 5990 | // **** D0F0xE4_WRAP_0903 Register Definition **** |
| 5991 | // Address |
| 5992 | #define D0F0xE4_WRAP_0903_ADDRESS 0x903 |
| 5993 | |
| 5994 | // Type |
| 5995 | #define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 |
| 5996 | // Field Data |
| 5997 | #define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 |
| 5998 | #define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 |
| 5999 | #define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f |
| 6000 | #define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 |
| 6001 | #define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 |
| 6002 | #define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 |
| 6003 | #define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 |
| 6004 | #define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 |
| 6005 | #define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 |
| 6006 | |
| 6007 | /// D0F0xE4_WRAP_0903 |
| 6008 | typedef union { |
| 6009 | struct { ///< |
| 6010 | UINT32 Reserved_4_0:5 ; ///< |
| 6011 | UINT32 StrapBifDeemphasisSel:1 ; ///< |
| 6012 | UINT32 Reserved_31_6:26; ///< |
| 6013 | } Field; ///< |
| 6014 | UINT32 Value; ///< |
| 6015 | } D0F0xE4_WRAP_0903_STRUCT; |
| 6016 | |
| 6017 | // **** D0F0xE4_WRAP_8002 Register Definition **** |
| 6018 | // Address |
| 6019 | #define D0F0xE4_WRAP_8002_ADDRESS 0x8002 |
| 6020 | |
| 6021 | // Type |
| 6022 | #define D0F0xE4_WRAP_8002_TYPE TYPE_D0F0xE4 |
| 6023 | // Field Data |
| 6024 | #define D0F0xE4_WRAP_8002_SubsystemVendorID_OFFSET 0 |
| 6025 | #define D0F0xE4_WRAP_8002_SubsystemVendorID_WIDTH 16 |
| 6026 | #define D0F0xE4_WRAP_8002_SubsystemVendorID_MASK 0xffff |
| 6027 | #define D0F0xE4_WRAP_8002_SubsystemID_OFFSET 16 |
| 6028 | #define D0F0xE4_WRAP_8002_SubsystemID_WIDTH 16 |
| 6029 | #define D0F0xE4_WRAP_8002_SubsystemID_MASK 0xffff0000 |
| 6030 | |
| 6031 | /// D0F0xE4_WRAP_8002 |
| 6032 | typedef union { |
| 6033 | struct { ///< |
| 6034 | UINT32 SubsystemVendorID:16; ///< |
| 6035 | UINT32 SubsystemID:16; ///< |
| 6036 | } Field; ///< |
| 6037 | UINT32 Value; ///< |
| 6038 | } D0F0xE4_WRAP_8002_STRUCT; |
| 6039 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 6040 | // **** D0F0xE4_WRAP_8011 Register Definition **** |
| 6041 | // Address |
| 6042 | #define D0F0xE4_WRAP_8011_ADDRESS 0x8011 |
| 6043 | |
| 6044 | // Type |
| 6045 | #define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 |
| 6046 | // Field Data |
| 6047 | #define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 |
| 6048 | #define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 |
| 6049 | #define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f |
| 6050 | #define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 |
| 6051 | #define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 |
| 6052 | #define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 |
| 6053 | #define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 |
| 6054 | #define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 |
| 6055 | #define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 |
| 6056 | #define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 |
| 6057 | #define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 |
| 6058 | #define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 |
| 6059 | #define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 |
| 6060 | #define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 |
| 6061 | #define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 |
| 6062 | #define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 |
| 6063 | #define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 |
| 6064 | #define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 |
| 6065 | #define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 |
| 6066 | #define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 |
| 6067 | #define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 |
| 6068 | #define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 |
| 6069 | #define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 |
| 6070 | #define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 |
| 6071 | #define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 |
| 6072 | #define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 |
| 6073 | #define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 |
| 6074 | #define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 |
| 6075 | #define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 |
| 6076 | #define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 |
| 6077 | #define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 |
| 6078 | #define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 |
| 6079 | #define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 |
| 6080 | #define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31 |
| 6081 | #define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1 |
| 6082 | #define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000 |
| 6083 | |
| 6084 | /// D0F0xE4_WRAP_8011 |
| 6085 | typedef union { |
| 6086 | struct { ///< |
| 6087 | UINT32 TxclkDynGateLatency:6 ; ///< |
| 6088 | UINT32 TxclkPermGateEven:1 ; ///< |
| 6089 | UINT32 TxclkDynGateEnable:1 ; ///< |
| 6090 | UINT32 TxclkPermStop:1 ; ///< |
| 6091 | UINT32 TxclkRegsGateEnable:1 ; ///< |
| 6092 | UINT32 TxclkRegsGateLatency:6 ; ///< |
| 6093 | UINT32 RcvrDetClkEnable:1 ; ///< |
| 6094 | UINT32 TxclkPermGateLatency:6 ; ///< |
| 6095 | UINT32 Reserved_23_23:1 ; ///< |
| 6096 | UINT32 TxclkLcntGateEnable:1 ; ///< |
| 6097 | UINT32 Reserved_30_25:6 ; ///< |
| 6098 | UINT32 StrapBifValid:1 ; ///< |
| 6099 | } Field; ///< |
| 6100 | UINT32 Value; ///< |
| 6101 | } D0F0xE4_WRAP_8011_STRUCT; |
| 6102 | |
| 6103 | // **** D0F0xE4_WRAP_8012 Register Definition **** |
| 6104 | // Address |
| 6105 | #define D0F0xE4_WRAP_8012_ADDRESS 0x8012 |
| 6106 | |
| 6107 | // Type |
| 6108 | #define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 |
| 6109 | // Field Data |
| 6110 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 |
| 6111 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 |
| 6112 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f |
| 6113 | #define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 |
| 6114 | #define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 |
| 6115 | #define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 |
| 6116 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 |
| 6117 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 |
| 6118 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 |
| 6119 | #define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 |
| 6120 | #define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 |
| 6121 | #define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 |
| 6122 | #define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 |
| 6123 | #define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 |
| 6124 | #define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 |
| 6125 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 |
| 6126 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 |
| 6127 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 |
| 6128 | #define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 |
| 6129 | #define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 |
| 6130 | #define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 |
| 6131 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 |
| 6132 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 |
| 6133 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 |
| 6134 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 |
| 6135 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 |
| 6136 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 |
| 6137 | #define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 |
| 6138 | #define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 |
| 6139 | #define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 |
| 6140 | |
| 6141 | /// D0F0xE4_WRAP_8012 |
| 6142 | typedef union { |
| 6143 | struct { ///< |
| 6144 | UINT32 Pif1xIdleGateLatency:6 ; ///< |
| 6145 | UINT32 Reserved_6_6:1 ; ///< |
| 6146 | UINT32 Pif1xIdleGateEnable:1 ; ///< |
| 6147 | UINT32 Pif1xIdleResumeLatency:6 ; ///< |
| 6148 | UINT32 Reserved_15_14:2 ; ///< |
| 6149 | UINT32 Pif2p5xIdleGateLatency:6 ; ///< |
| 6150 | UINT32 Reserved_22_22:1 ; ///< |
| 6151 | UINT32 Pif2p5xIdleGateEnable:1 ; ///< |
| 6152 | UINT32 Pif2p5xIdleResumeLatency:6 ; ///< |
| 6153 | UINT32 Reserved_31_30:2 ; ///< |
| 6154 | } Field; ///< |
| 6155 | UINT32 Value; ///< |
| 6156 | } D0F0xE4_WRAP_8012_STRUCT; |
| 6157 | |
| 6158 | |
| 6159 | // **** D0F0xE4_WRAP_8013 Register Definition **** |
| 6160 | // Address |
| 6161 | #define D0F0xE4_WRAP_8013_ADDRESS 0x8013 |
| 6162 | |
| 6163 | // Field Data |
| 6164 | #define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 |
| 6165 | #define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 |
| 6166 | #define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 |
| 6167 | #define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 |
| 6168 | #define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 |
| 6169 | #define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 |
| 6170 | #define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 |
| 6171 | #define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 |
| 6172 | #define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 |
| 6173 | #define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 |
| 6174 | #define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 |
| 6175 | #define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 |
| 6176 | #define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 |
| 6177 | #define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 |
| 6178 | #define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 |
| 6179 | #define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 |
| 6180 | #define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 |
| 6181 | #define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 |
| 6182 | #define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 |
| 6183 | #define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 |
| 6184 | #define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 |
| 6185 | #define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 |
| 6186 | #define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 |
| 6187 | #define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 |
| 6188 | #define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 |
| 6189 | #define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 |
| 6190 | #define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 |
| 6191 | #define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 |
| 6192 | #define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 |
| 6193 | #define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 |
| 6194 | #define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 |
| 6195 | #define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 |
| 6196 | #define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 |
| 6197 | #define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 |
| 6198 | #define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 |
| 6199 | #define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 |
| 6200 | #define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 |
| 6201 | #define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 |
| 6202 | #define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 |
| 6203 | #define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 |
| 6204 | #define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 |
| 6205 | #define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 |
| 6206 | #define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 |
| 6207 | #define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 |
| 6208 | #define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 |
| 6209 | #define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 |
| 6210 | #define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 |
| 6211 | #define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 |
| 6212 | #define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 |
| 6213 | #define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 |
| 6214 | #define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 |
| 6215 | #define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 |
| 6216 | #define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 |
| 6217 | #define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 |
| 6218 | |
| 6219 | /// D0F0xE4_WRAP_8013 |
| 6220 | typedef union { |
| 6221 | struct { ///< |
| 6222 | UINT32 MasterPciePllA:1 ; ///< |
| 6223 | UINT32 MasterPciePllB:1 ; ///< |
| 6224 | UINT32 MasterPciePllC:1 ; ///< |
| 6225 | UINT32 MasterPciePllD:1 ; ///< |
| 6226 | UINT32 ClkDividerResetOverrideA:1 ; ///< |
| 6227 | UINT32 Reserved_5_5:1 ; ///< |
| 6228 | UINT32 Reserved_6_6:1 ; ///< |
| 6229 | UINT32 Reserved_7_7:1 ; ///< |
| 6230 | UINT32 TxclkSelCoreOverride:1 ; ///< |
| 6231 | UINT32 TxclkSelPifAOverride:1 ; ///< |
| 6232 | UINT32 Reserved_10_10:1 ; ///< |
| 6233 | UINT32 Reserved_11_11:1 ; ///< |
| 6234 | UINT32 Reserved_12_12:1 ; ///< |
| 6235 | UINT32 Reserved_15_13:3 ; ///< |
| 6236 | UINT32 Reserved_16_16:1 ; ///< |
| 6237 | UINT32 Reserved_19_17:3 ; ///< |
| 6238 | UINT32 Reserved_20_20:1 ; ///< |
| 6239 | UINT32 Reserved_31_21:11; ///< |
| 6240 | } Field; ///< |
| 6241 | UINT32 Value; ///< |
| 6242 | } D0F0xE4_WRAP_8013_STRUCT; |
| 6243 | |
| 6244 | // **** D0F0xE4_WRAP_8014 Register Definition **** |
| 6245 | // Address |
| 6246 | #define D0F0xE4_WRAP_8014_ADDRESS 0x8014 |
| 6247 | |
| 6248 | // Field Data |
| 6249 | #define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 |
| 6250 | #define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 |
| 6251 | #define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 |
| 6252 | #define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 |
| 6253 | #define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 |
| 6254 | #define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 |
| 6255 | #define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 |
| 6256 | #define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 |
| 6257 | #define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 |
| 6258 | #define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 |
| 6259 | #define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 |
| 6260 | #define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 |
| 6261 | #define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 |
| 6262 | #define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 |
| 6263 | #define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 |
| 6264 | #define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 |
| 6265 | #define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 |
| 6266 | #define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 |
| 6267 | #define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 |
| 6268 | #define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 |
| 6269 | #define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 |
| 6270 | #define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 |
| 6271 | #define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 |
| 6272 | #define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 |
| 6273 | #define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 |
| 6274 | #define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 |
| 6275 | #define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 |
| 6276 | #define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 |
| 6277 | #define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 |
| 6278 | #define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 |
| 6279 | #define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 |
| 6280 | #define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 |
| 6281 | #define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 |
| 6282 | #define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 |
| 6283 | #define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 |
| 6284 | #define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 |
| 6285 | #define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 |
| 6286 | #define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 |
| 6287 | #define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 |
| 6288 | #define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 |
| 6289 | #define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 |
| 6290 | #define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 |
| 6291 | #define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 |
| 6292 | #define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 |
| 6293 | #define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 |
| 6294 | #define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 |
| 6295 | #define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 |
| 6296 | #define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 |
| 6297 | #define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 |
| 6298 | #define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 |
| 6299 | #define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 |
| 6300 | #define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 |
| 6301 | #define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 |
| 6302 | #define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 |
| 6303 | #define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 |
| 6304 | #define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 |
| 6305 | #define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 |
| 6306 | #define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 |
| 6307 | #define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 |
| 6308 | #define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 |
| 6309 | #define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 |
| 6310 | #define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 |
| 6311 | #define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 |
| 6312 | #define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 |
| 6313 | #define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 |
| 6314 | #define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 |
| 6315 | |
| 6316 | /// D0F0xE4_WRAP_8014 |
| 6317 | typedef union { |
| 6318 | struct { |
| 6319 | UINT32 TxclkPermGateEnable:1 ; ///< |
| 6320 | UINT32 TxclkPrbsGateEnable:1 ; ///< |
| 6321 | UINT32 DdiGatePifA1xEnable:1 ; ///< |
| 6322 | UINT32 DdiGatePifB1xEnable:1 ; ///< |
| 6323 | UINT32 DdiGatePifC1xEnable:1 ; ///< |
| 6324 | UINT32 DdiGatePifD1xEnable:1 ; ///< |
| 6325 | UINT32 DdiGateDigAEnable:1 ; ///< |
| 6326 | UINT32 DdiGateDigBEnable:1 ; ///< |
| 6327 | UINT32 DdiGatePifA2p5xEnable:1 ; ///< |
| 6328 | UINT32 DdiGatePifB2p5xEnable:1 ; ///< |
| 6329 | UINT32 DdiGatePifC2p5xEnable:1 ; ///< |
| 6330 | UINT32 DdiGatePifD2p5xEnable:1 ; ///< |
| 6331 | UINT32 PcieGatePifA1xEnable:1 ; ///< |
| 6332 | UINT32 PcieGatePifB1xEnable:1 ; ///< |
| 6333 | UINT32 PcieGatePifC1xEnable:1 ; ///< |
| 6334 | UINT32 PcieGatePifD1xEnable:1 ; ///< |
| 6335 | UINT32 PcieGatePifA2p5xEnable:1 ; ///< |
| 6336 | UINT32 PcieGatePifB2p5xEnable:1 ; ///< |
| 6337 | UINT32 PcieGatePifC2p5xEnable:1 ; ///< |
| 6338 | UINT32 PcieGatePifD2p5xEnable:1 ; ///< |
| 6339 | UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< |
| 6340 | UINT32 Reserved_31_21:11; ///< |
| 6341 | } Field; ///< |
| 6342 | UINT32 Value; ///< |
| 6343 | } D0F0xE4_WRAP_8014_STRUCT; |
| 6344 | |
| 6345 | // **** D0F0xE4_WRAP_8016 Register Definition **** |
| 6346 | // Address |
| 6347 | #define D0F0xE4_WRAP_8016_ADDRESS 0x8016 |
| 6348 | |
| 6349 | // Type |
| 6350 | #define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 |
| 6351 | // Field Data |
| 6352 | #define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 |
| 6353 | #define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 |
| 6354 | #define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f |
| 6355 | #define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6 |
| 6356 | #define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16 |
| 6357 | #define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0 |
| 6358 | #define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 |
| 6359 | #define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 |
| 6360 | #define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 |
| 6361 | #define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 |
| 6362 | #define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 |
| 6363 | #define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 |
| 6364 | #define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 |
| 6365 | #define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 |
| 6366 | #define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 |
| 6367 | |
| 6368 | /// D0F0xE4_WRAP_8016 |
| 6369 | typedef union { |
| 6370 | struct { ///< |
| 6371 | UINT32 CalibAckLatency:6 ; ///< |
| 6372 | UINT32 Reserved_21_6:16; ///< |
| 6373 | UINT32 LclkGateFree:1 ; ///< |
| 6374 | UINT32 LclkDynGateEnable:1 ; ///< |
| 6375 | UINT32 Reserved_31_24:8 ; ///< |
| 6376 | } Field; ///< |
| 6377 | UINT32 Value; ///< |
| 6378 | } D0F0xE4_WRAP_8016_STRUCT; |
| 6379 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 6380 | // **** D0F0xE4_WRAP_8021 Register Definition **** |
| 6381 | // Address |
| 6382 | #define D0F0xE4_WRAP_8021_ADDRESS 0x8021 |
| 6383 | |
| 6384 | // Type |
| 6385 | #define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 |
| 6386 | // Field Data |
| 6387 | #define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0 |
| 6388 | #define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4 |
| 6389 | #define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf |
| 6390 | #define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4 |
| 6391 | #define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4 |
| 6392 | #define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0 |
| 6393 | #define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8 |
| 6394 | #define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4 |
| 6395 | #define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00 |
| 6396 | #define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12 |
| 6397 | #define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4 |
| 6398 | #define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000 |
| 6399 | #define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16 |
| 6400 | #define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4 |
| 6401 | #define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000 |
| 6402 | #define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20 |
| 6403 | #define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4 |
| 6404 | #define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000 |
| 6405 | #define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24 |
| 6406 | #define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4 |
| 6407 | #define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000 |
| 6408 | #define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28 |
| 6409 | #define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4 |
| 6410 | #define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000 |
| 6411 | |
| 6412 | /// D0F0xE4_WRAP_8021 |
| 6413 | typedef union { |
| 6414 | struct { ///< |
| 6415 | UINT32 Lanes10:4 ; ///< |
| 6416 | UINT32 Lanes32:4 ; ///< |
| 6417 | UINT32 Lanes54:4 ; ///< |
| 6418 | UINT32 Lanes76:4 ; ///< |
| 6419 | UINT32 Lanes98:4 ; ///< |
| 6420 | UINT32 Lanes1110:4 ; ///< |
| 6421 | UINT32 Lanes1312:4 ; ///< |
| 6422 | UINT32 Lanes1514:4 ; ///< |
| 6423 | } Field; ///< |
| 6424 | UINT32 Value; ///< |
| 6425 | } D0F0xE4_WRAP_8021_STRUCT; |
| 6426 | |
| 6427 | // **** D0F0xE4_WRAP_8022 Register Definition **** |
| 6428 | // Address |
| 6429 | #define D0F0xE4_WRAP_8022_ADDRESS 0x8022 |
| 6430 | |
| 6431 | // Type |
| 6432 | #define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 |
| 6433 | // Field Data |
| 6434 | #define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0 |
| 6435 | #define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4 |
| 6436 | #define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf |
| 6437 | #define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4 |
| 6438 | #define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4 |
| 6439 | #define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0 |
| 6440 | #define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8 |
| 6441 | #define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4 |
| 6442 | #define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00 |
| 6443 | #define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12 |
| 6444 | #define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4 |
| 6445 | #define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000 |
| 6446 | #define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16 |
| 6447 | #define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4 |
| 6448 | #define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000 |
| 6449 | #define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20 |
| 6450 | #define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4 |
| 6451 | #define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000 |
| 6452 | #define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24 |
| 6453 | #define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4 |
| 6454 | #define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000 |
| 6455 | #define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28 |
| 6456 | #define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4 |
| 6457 | #define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000 |
| 6458 | |
| 6459 | /// D0F0xE4_WRAP_8022 |
| 6460 | typedef union { |
| 6461 | struct { ///< |
| 6462 | UINT32 Lanes10:4 ; ///< |
| 6463 | UINT32 Lanes32:4 ; ///< |
| 6464 | UINT32 Lanes54:4 ; ///< |
| 6465 | UINT32 Lanes76:4 ; ///< |
| 6466 | UINT32 Lanes98:4 ; ///< |
| 6467 | UINT32 Lanes1110:4 ; ///< |
| 6468 | UINT32 Lanes1312:4 ; ///< |
| 6469 | UINT32 Lanes1514:4 ; ///< |
| 6470 | } Field; ///< |
| 6471 | UINT32 Value; ///< |
| 6472 | } D0F0xE4_WRAP_8022_STRUCT; |
| 6473 | |
| 6474 | // **** D0F0xE4_WRAP_8023 Register Definition **** |
| 6475 | // Address |
| 6476 | #define D0F0xE4_WRAP_8023_ADDRESS 0x8023 |
| 6477 | |
| 6478 | // Type |
| 6479 | #define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 |
| 6480 | // Field Data |
| 6481 | #define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0 |
| 6482 | #define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16 |
| 6483 | #define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff |
| 6484 | #define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16 |
| 6485 | #define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16 |
| 6486 | #define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000 |
| 6487 | |
| 6488 | /// D0F0xE4_WRAP_8023 |
| 6489 | typedef union { |
| 6490 | struct { ///< |
| 6491 | UINT32 LaneEnable:16; ///< |
| 6492 | UINT32 Reserved_31_16:16; ///< |
| 6493 | } Field; ///< |
| 6494 | UINT32 Value; ///< |
| 6495 | } D0F0xE4_WRAP_8023_STRUCT; |
| 6496 | |
| 6497 | // **** D0F0xE4_WRAP_8025 Register Definition **** |
| 6498 | // Address |
| 6499 | #define D0F0xE4_WRAP_8025_ADDRESS 0x8025 |
| 6500 | |
| 6501 | // Type |
| 6502 | #define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 |
| 6503 | // Field Data |
| 6504 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0 |
| 6505 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3 |
| 6506 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7 |
| 6507 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3 |
| 6508 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2 |
| 6509 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18 |
| 6510 | #define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5 |
| 6511 | #define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1 |
| 6512 | #define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20 |
| 6513 | #define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6 |
| 6514 | #define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2 |
| 6515 | #define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0 |
| 6516 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8 |
| 6517 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3 |
| 6518 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700 |
| 6519 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11 |
| 6520 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2 |
| 6521 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800 |
| 6522 | #define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13 |
| 6523 | #define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1 |
| 6524 | #define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000 |
| 6525 | #define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14 |
| 6526 | #define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2 |
| 6527 | #define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000 |
| 6528 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16 |
| 6529 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3 |
| 6530 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000 |
| 6531 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19 |
| 6532 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2 |
| 6533 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000 |
| 6534 | #define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21 |
| 6535 | #define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1 |
| 6536 | #define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000 |
| 6537 | #define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22 |
| 6538 | #define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2 |
| 6539 | #define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000 |
| 6540 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24 |
| 6541 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3 |
| 6542 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000 |
| 6543 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27 |
| 6544 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2 |
| 6545 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000 |
| 6546 | #define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29 |
| 6547 | #define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1 |
| 6548 | #define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000 |
| 6549 | #define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30 |
| 6550 | #define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2 |
| 6551 | #define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000 |
| 6552 | |
| 6553 | /// D0F0xE4_WRAP_8025 |
| 6554 | typedef union { |
| 6555 | struct { ///< |
| 6556 | UINT32 LMTxPhyCmd0:3 ; ///< |
| 6557 | UINT32 LMRxPhyCmd0:2 ; ///< |
| 6558 | UINT32 LMLinkSpeed0:1 ; ///< |
| 6559 | UINT32 Reserved_7_6:2 ; ///< |
| 6560 | UINT32 LMTxPhyCmd1:3 ; ///< |
| 6561 | UINT32 LMRxPhyCmd1:2 ; ///< |
| 6562 | UINT32 LMLinkSpeed1:1 ; ///< |
| 6563 | UINT32 Reserved_15_14:2 ; ///< |
| 6564 | UINT32 LMTxPhyCmd2:3 ; ///< |
| 6565 | UINT32 LMRxPhyCmd2:2 ; ///< |
| 6566 | UINT32 LMLinkSpeed2:1 ; ///< |
| 6567 | UINT32 Reserved_23_22:2 ; ///< |
| 6568 | UINT32 LMTxPhyCmd3:3 ; ///< |
| 6569 | UINT32 LMRxPhyCmd3:2 ; ///< |
| 6570 | UINT32 LMLinkSpeed3:1 ; ///< |
| 6571 | UINT32 Reserved_31_30:2 ; ///< |
| 6572 | } Field; ///< |
| 6573 | UINT32 Value; ///< |
| 6574 | } D0F0xE4_WRAP_8025_STRUCT; |
| 6575 | |
| 6576 | // **** D0F0xE4_WRAP_8031 Register Definition **** |
| 6577 | // Address |
| 6578 | #define D0F0xE4_WRAP_8031_ADDRESS 0x8031 |
| 6579 | |
| 6580 | // Type |
| 6581 | #define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4 |
| 6582 | // Field Data |
| 6583 | #define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0 |
| 6584 | #define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10 |
| 6585 | #define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff |
| 6586 | #define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10 |
| 6587 | #define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6 |
| 6588 | #define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00 |
| 6589 | #define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16 |
| 6590 | #define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1 |
| 6591 | #define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000 |
| 6592 | #define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17 |
| 6593 | #define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15 |
| 6594 | #define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000 |
| 6595 | |
| 6596 | /// D0F0xE4_WRAP_8031 |
| 6597 | typedef union { |
| 6598 | struct { ///< |
| 6599 | UINT32 LnCntBandwidth:10; ///< |
| 6600 | UINT32 Reserved_15_10:6 ; ///< |
| 6601 | UINT32 LnCntValid:1 ; ///< |
| 6602 | UINT32 Reserved_31_17:15; ///< |
| 6603 | } Field; ///< |
| 6604 | UINT32 Value; ///< |
| 6605 | } D0F0xE4_WRAP_8031_STRUCT; |
| 6606 | |
| 6607 | // **** D0F0xE4_WRAP_8060 Register Definition **** |
| 6608 | // Address |
| 6609 | #define D0F0xE4_WRAP_8060_ADDRESS 0x8060 |
| 6610 | |
| 6611 | // Type |
| 6612 | #define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 |
| 6613 | // Field Data |
| 6614 | #define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0 |
| 6615 | #define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1 |
| 6616 | #define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1 |
| 6617 | #define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1 |
| 6618 | #define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1 |
| 6619 | #define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2 |
| 6620 | #define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 |
| 6621 | #define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 |
| 6622 | #define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 6623 | #define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 |
| 6624 | #define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 |
| 6625 | #define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 |
| 6626 | #define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 |
| 6627 | #define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 |
| 6628 | #define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 |
| 6629 | #define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 |
| 6630 | #define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 |
| 6631 | #define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 |
| 6632 | #define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 |
| 6633 | #define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 |
| 6634 | #define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 6635 | |
| 6636 | /// D0F0xE4_WRAP_8060 |
| 6637 | typedef union { |
| 6638 | struct { ///< |
| 6639 | UINT32 Reconfigure:1 ; ///< |
| 6640 | UINT32 Reserved_1_1:1 ; ///< |
| 6641 | UINT32 ResetComplete:1 ; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 6642 | UINT32 Reserved_15_3:13; ///< |
| 6643 | UINT32 BifGlobalReset:1 ; ///< |
| 6644 | UINT32 BifCalibrationReset:1 ; ///< |
| 6645 | UINT32 Reserved_31_18:14; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 6646 | } Field; ///< |
| 6647 | UINT32 Value; ///< |
| 6648 | } D0F0xE4_WRAP_8060_STRUCT; |
| 6649 | |
| 6650 | // **** D0F0xE4_WRAP_8061 Register Definition **** |
| 6651 | // Address |
| 6652 | #define D0F0xE4_WRAP_8061_ADDRESS 0x8061 |
| 6653 | |
| 6654 | // Type |
| 6655 | #define D0F0xE4_WRAP_8061_TYPE TYPE_D0F0xE4 |
| 6656 | // Field Data |
| 6657 | #define D0F0xE4_WRAP_8061_Reserved_14_0_OFFSET 0 |
| 6658 | #define D0F0xE4_WRAP_8061_Reserved_14_0_WIDTH 15 |
| 6659 | #define D0F0xE4_WRAP_8061_Reserved_14_0_MASK 0x7fff |
| 6660 | #define D0F0xE4_WRAP_8061_ResetCpm_OFFSET 15 |
| 6661 | #define D0F0xE4_WRAP_8061_ResetCpm_WIDTH 1 |
| 6662 | #define D0F0xE4_WRAP_8061_ResetCpm_MASK 0x8000 |
| 6663 | #define D0F0xE4_WRAP_8061_ResetPif0_OFFSET 16 |
| 6664 | #define D0F0xE4_WRAP_8061_ResetPif0_WIDTH 1 |
| 6665 | #define D0F0xE4_WRAP_8061_ResetPif0_MASK 0x10000 |
| 6666 | #define D0F0xE4_WRAP_8061_Reserved_23_17_OFFSET 17 |
| 6667 | #define D0F0xE4_WRAP_8061_Reserved_23_17_WIDTH 7 |
| 6668 | #define D0F0xE4_WRAP_8061_Reserved_23_17_MASK 0xfe0000 |
| 6669 | #define D0F0xE4_WRAP_8061_ResetPhy0_OFFSET 24 |
| 6670 | #define D0F0xE4_WRAP_8061_ResetPhy0_WIDTH 1 |
| 6671 | #define D0F0xE4_WRAP_8061_ResetPhy0_MASK 0x1000000 |
| 6672 | #define D0F0xE4_WRAP_8061_Reserved_31_25_OFFSET 25 |
| 6673 | #define D0F0xE4_WRAP_8061_Reserved_31_25_WIDTH 7 |
| 6674 | #define D0F0xE4_WRAP_8061_Reserved_31_25_MASK 0xfe000000 |
| 6675 | |
| 6676 | /// D0F0xE4_WRAP_8061 |
| 6677 | typedef union { |
| 6678 | struct { ///< |
| 6679 | UINT32 Reserved_14_0:15; ///< |
| 6680 | UINT32 ResetCpm:1 ; ///< |
| 6681 | UINT32 ResetPif0:1 ; ///< |
| 6682 | UINT32 Reserved_23_17:7 ; ///< |
| 6683 | UINT32 ResetPhy0:1 ; ///< |
| 6684 | UINT32 Reserved_31_25:7 ; ///< |
| 6685 | } Field; ///< |
| 6686 | UINT32 Value; ///< |
| 6687 | } D0F0xE4_WRAP_8061_STRUCT; |
| 6688 | |
| 6689 | // **** D0F0xE4_WRAP_8062 Register Definition **** |
| 6690 | // Address |
| 6691 | #define D0F0xE4_WRAP_8062_ADDRESS 0x8062 |
| 6692 | |
| 6693 | // Type |
| 6694 | #define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 |
| 6695 | // Field Data |
| 6696 | #define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 |
| 6697 | #define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 |
| 6698 | #define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 |
| 6699 | #define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 |
| 6700 | #define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 |
| 6701 | #define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 |
| 6702 | #define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 |
| 6703 | #define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 |
| 6704 | #define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c |
| 6705 | #define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 |
| 6706 | #define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 |
| 6707 | #define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 |
| 6708 | #define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 |
| 6709 | #define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 |
| 6710 | #define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 |
| 6711 | #define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 |
| 6712 | #define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 |
| 6713 | #define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 |
| 6714 | #define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 |
| 6715 | #define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 |
| 6716 | #define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 |
| 6717 | |
| 6718 | /// D0F0xE4_WRAP_8062 |
| 6719 | typedef union { |
| 6720 | struct { ///< |
| 6721 | UINT32 ReconfigureEn:1 ; ///< |
| 6722 | UINT32 Reserved_1_1:1 ; ///< |
| 6723 | UINT32 ResetPeriod:3 ; ///< |
| 6724 | UINT32 Reserved_9_5:5 ; ///< |
| 6725 | UINT32 BlockOnIdle:1 ; ///< |
| 6726 | UINT32 ConfigXferMode:1 ; ///< |
| 6727 | UINT32 Reserved_31_12:20; ///< |
| 6728 | } Field; ///< |
| 6729 | UINT32 Value; ///< |
| 6730 | } D0F0xE4_WRAP_8062_STRUCT; |
| 6731 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 6732 | // **** D0F0xE4_WRAP_80F0 Register Definition **** |
| 6733 | // Address |
| 6734 | #define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 |
| 6735 | |
| 6736 | // Type |
| 6737 | #define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 |
| 6738 | // Field Data |
| 6739 | #define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 |
| 6740 | #define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 |
| 6741 | #define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff |
| 6742 | |
| 6743 | /// D0F0xE4_WRAP_80F0 |
| 6744 | typedef union { |
| 6745 | struct { ///< |
| 6746 | UINT32 MicroSeconds:32; ///< |
| 6747 | } Field; ///< |
| 6748 | UINT32 Value; ///< |
| 6749 | } D0F0xE4_WRAP_80F0_STRUCT; |
| 6750 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 6751 | // **** D0F0xE4_x0108_8071 Register Definition **** |
| 6752 | // Address |
| 6753 | #define D0F0xE4_x0108_8071_ADDRESS 0x1088071 |
| 6754 | |
| 6755 | // Type |
| 6756 | #define D0F0xE4_x0108_8071_TYPE TYPE_D0F0xE4 |
| 6757 | // Field Data |
| 6758 | #define D0F0xE4_x0108_8071_RxAdjust_OFFSET 0 |
| 6759 | #define D0F0xE4_x0108_8071_RxAdjust_WIDTH 3 |
| 6760 | #define D0F0xE4_x0108_8071_RxAdjust_MASK 0x7 |
| 6761 | #define D0F0xE4_x0108_8071_Reserved_31_3_OFFSET 3 |
| 6762 | #define D0F0xE4_x0108_8071_Reserved_31_3_WIDTH 29 |
| 6763 | #define D0F0xE4_x0108_8071_Reserved_31_3_MASK 0xfffffff8 |
| 6764 | |
| 6765 | /// D0F0xE4_x0108_8071 |
| 6766 | typedef union { |
| 6767 | struct { ///< |
| 6768 | UINT32 RxAdjust:3 ; ///< |
| 6769 | UINT32 Reserved_31_3:29; ///< |
| 6770 | } Field; ///< |
| 6771 | UINT32 Value; ///< |
| 6772 | } D0F0xE4_x0108_8071_STRUCT; |
| 6773 | |
| 6774 | // **** D0F0xE4_x0108_8072 Register Definition **** |
| 6775 | // Address |
| 6776 | #define D0F0xE4_x0108_8072_ADDRESS 0x1088072 |
| 6777 | |
| 6778 | // Type |
| 6779 | #define D0F0xE4_x0108_8072_TYPE TYPE_D0F0xE4 |
| 6780 | // Field Data |
| 6781 | #define D0F0xE4_x0108_8072_TxAdjust_OFFSET 0 |
| 6782 | #define D0F0xE4_x0108_8072_TxAdjust_WIDTH 3 |
| 6783 | #define D0F0xE4_x0108_8072_TxAdjust_MASK 0x7 |
| 6784 | #define D0F0xE4_x0108_8072_Reserved_31_3_OFFSET 3 |
| 6785 | #define D0F0xE4_x0108_8072_Reserved_31_3_WIDTH 29 |
| 6786 | #define D0F0xE4_x0108_8072_Reserved_31_3_MASK 0xfffffff8 |
| 6787 | |
| 6788 | /// D0F0xE4_x0108_8072 |
| 6789 | typedef union { |
| 6790 | struct { ///< |
| 6791 | UINT32 TxAdjust:3 ; ///< |
| 6792 | UINT32 Reserved_31_3:29; ///< |
| 6793 | } Field; ///< |
| 6794 | UINT32 Value; ///< |
| 6795 | } D0F0xE4_x0108_8072_STRUCT; |
| 6796 | |
| 6797 | // **** D0F0xE4_PIF_0010 Register Definition **** |
| 6798 | // Address |
| 6799 | #define D0F0xE4_PIF_0010_ADDRESS 0x10 |
| 6800 | |
| 6801 | // Type |
| 6802 | #define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 |
| 6803 | // Field Data |
| 6804 | #define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 |
| 6805 | #define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 |
| 6806 | #define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf |
| 6807 | #define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 |
| 6808 | #define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 |
| 6809 | #define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 |
| 6810 | #define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 |
| 6811 | #define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 |
| 6812 | #define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 |
| 6813 | #define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 |
| 6814 | #define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 |
| 6815 | #define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 |
| 6816 | #define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 |
| 6817 | #define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 |
| 6818 | #define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 |
| 6819 | #define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 |
| 6820 | #define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 |
| 6821 | #define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 |
| 6822 | #define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 |
| 6823 | #define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 |
| 6824 | #define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 |
| 6825 | #define D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET 20 |
| 6826 | #define D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH 3 |
| 6827 | #define D0F0xE4_PIF_0010_EiCycleOffTime_MASK 0x700000 |
| 6828 | #define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 |
| 6829 | #define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 |
| 6830 | #define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 |
| 6831 | |
| 6832 | /// D0F0xE4_PIF_0010 |
| 6833 | typedef union { |
| 6834 | struct { ///< |
| 6835 | UINT32 Reserved_3_0:4 ; ///< |
| 6836 | UINT32 EiDetCycleMode:1 ; ///< |
| 6837 | UINT32 Reserved_5_5:1 ; ///< |
| 6838 | UINT32 RxDetectFifoResetMode:1 ; ///< |
| 6839 | UINT32 RxDetectTxPwrMode:1 ; ///< |
| 6840 | UINT32 Reserved_16_8:9 ; ///< |
| 6841 | UINT32 Ls2ExitTime:3 ; ///< |
| 6842 | UINT32 EiCycleOffTime:3 ; ///< |
| 6843 | UINT32 Reserved_31_23:9 ; ///< |
| 6844 | } Field; ///< |
| 6845 | UINT32 Value; ///< |
| 6846 | } D0F0xE4_PIF_0010_STRUCT; |
| 6847 | |
| 6848 | // **** D0F0xE4_PIF_0011 Register Definition **** |
| 6849 | // Address |
| 6850 | #define D0F0xE4_PIF_0011_ADDRESS 0x11 |
| 6851 | |
| 6852 | // Type |
| 6853 | #define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 |
| 6854 | // Field Data |
| 6855 | #define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 |
| 6856 | #define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 |
| 6857 | #define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 |
| 6858 | #define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 |
| 6859 | #define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 |
| 6860 | #define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 |
| 6861 | #define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 |
| 6862 | #define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 |
| 6863 | #define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 |
| 6864 | #define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 |
| 6865 | #define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 |
| 6866 | #define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 |
| 6867 | #define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 |
| 6868 | #define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 |
| 6869 | #define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 |
| 6870 | #define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 |
| 6871 | #define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 |
| 6872 | #define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 |
| 6873 | #define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 |
| 6874 | #define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 |
| 6875 | #define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 |
| 6876 | #define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 |
| 6877 | #define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 |
| 6878 | #define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 |
| 6879 | #define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12 |
| 6880 | #define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1 |
| 6881 | #define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000 |
| 6882 | #define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 |
| 6883 | #define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 |
| 6884 | #define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 |
| 6885 | #define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 |
| 6886 | #define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 |
| 6887 | #define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 |
| 6888 | #define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 |
| 6889 | #define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 |
| 6890 | #define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 |
| 6891 | #define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 |
| 6892 | #define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 |
| 6893 | #define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 |
| 6894 | #define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 |
| 6895 | #define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 |
| 6896 | #define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 |
| 6897 | |
| 6898 | /// D0F0xE4_PIF_0011 |
| 6899 | typedef union { |
| 6900 | struct { ///< |
| 6901 | UINT32 X2Lane10:1 ; ///< |
| 6902 | UINT32 X2Lane32:1 ; ///< |
| 6903 | UINT32 X2Lane54:1 ; ///< |
| 6904 | UINT32 X2Lane76:1 ; ///< |
| 6905 | UINT32 Reserved_7_4:4 ; ///< |
| 6906 | UINT32 X4Lane30:1 ; ///< |
| 6907 | UINT32 X4Lane74:1 ; ///< |
| 6908 | UINT32 Reserved_11_10:2 ; ///< |
| 6909 | UINT32 X4Lane52:1 ; ///< |
| 6910 | UINT32 Reserved_15_13:3 ; ///< |
| 6911 | UINT32 X8Lane70:1 ; ///< |
| 6912 | UINT32 Reserved_24_17:8 ; ///< |
| 6913 | UINT32 MultiPif:1 ; ///< |
| 6914 | UINT32 Reserved_31_26:6 ; ///< |
| 6915 | } Field; ///< |
| 6916 | UINT32 Value; ///< |
| 6917 | } D0F0xE4_PIF_0011_STRUCT; |
| 6918 | |
| 6919 | // **** D0F0xE4_PIF_0012 Register Definition **** |
| 6920 | // Address |
| 6921 | #define D0F0xE4_PIF_0012_ADDRESS 0x12 |
| 6922 | |
| 6923 | // Type |
| 6924 | #define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 |
| 6925 | // Field Data |
| 6926 | #define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 |
| 6927 | #define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 |
| 6928 | #define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 |
| 6929 | #define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 |
| 6930 | #define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 |
| 6931 | #define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 |
| 6932 | #define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 |
| 6933 | #define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 |
| 6934 | #define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 |
| 6935 | #define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 |
| 6936 | #define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 |
| 6937 | #define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 |
| 6938 | #define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 |
| 6939 | #define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 |
| 6940 | #define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 |
| 6941 | #define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 |
| 6942 | #define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 |
| 6943 | #define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 |
| 6944 | #define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 |
| 6945 | #define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 |
| 6946 | #define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 |
| 6947 | #define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 |
| 6948 | #define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 |
| 6949 | #define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 |
| 6950 | #define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 |
| 6951 | #define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 |
| 6952 | #define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 |
| 6953 | #define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 |
| 6954 | #define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 |
| 6955 | #define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 |
| 6956 | #define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 |
| 6957 | #define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 |
| 6958 | #define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 |
| 6959 | #define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 |
| 6960 | #define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 |
| 6961 | #define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 |
| 6962 | |
| 6963 | /// D0F0xE4_PIF_0012 |
| 6964 | typedef union { |
| 6965 | struct { ///< |
| 6966 | UINT32 TxPowerStateInTxs2:3 ; ///< |
| 6967 | UINT32 ForceRxEnInL0s:1 ; ///< |
| 6968 | UINT32 RxPowerStateInRxs2:3 ; ///< |
| 6969 | UINT32 PllPowerStateInTxs2:3 ; ///< |
| 6970 | UINT32 PllPowerStateInOff:3 ; ///< |
| 6971 | UINT32 Reserved_15_13:3 ; ///< |
| 6972 | UINT32 Tx2p5clkClockGatingEn:1 ; ///< |
| 6973 | UINT32 Reserved_23_17:7 ; ///< |
| 6974 | UINT32 PllRampUpTime:3 ; ///< |
| 6975 | UINT32 Reserved_27_27:1 ; ///< |
| 6976 | UINT32 PllPwrOverrideEn:1 ; ///< |
| 6977 | UINT32 PllPwrOverrideVal:3 ; ///< |
| 6978 | } Field; ///< |
| 6979 | UINT32 Value; ///< |
| 6980 | } D0F0xE4_PIF_0012_STRUCT; |
| 6981 | |
| 6982 | // **** D0F0xE4_PIF_0013 Register Definition **** |
| 6983 | // Address |
| 6984 | #define D0F0xE4_PIF_0013_ADDRESS 0x13 |
| 6985 | |
| 6986 | // Type |
| 6987 | #define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 |
| 6988 | // Field Data |
| 6989 | #define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 |
| 6990 | #define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 |
| 6991 | #define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 |
| 6992 | #define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 |
| 6993 | #define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 |
| 6994 | #define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 |
| 6995 | #define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 |
| 6996 | #define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 |
| 6997 | #define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 |
| 6998 | #define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 |
| 6999 | #define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 |
| 7000 | #define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 |
| 7001 | #define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 |
| 7002 | #define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 |
| 7003 | #define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 |
| 7004 | #define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 |
| 7005 | #define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 |
| 7006 | #define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 |
| 7007 | #define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 |
| 7008 | #define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 |
| 7009 | #define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 |
| 7010 | #define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 |
| 7011 | #define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 |
| 7012 | #define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 |
| 7013 | #define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 |
| 7014 | #define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 |
| 7015 | #define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 |
| 7016 | #define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 |
| 7017 | #define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 |
| 7018 | #define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 |
| 7019 | #define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 |
| 7020 | #define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 |
| 7021 | #define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 |
| 7022 | #define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 |
| 7023 | #define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 |
| 7024 | #define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 |
| 7025 | |
| 7026 | /// D0F0xE4_PIF_0013 |
| 7027 | typedef union { |
| 7028 | struct { ///< |
| 7029 | UINT32 TxPowerStateInTxs2:3 ; ///< |
| 7030 | UINT32 ForceRxEnInL0s:1 ; ///< |
| 7031 | UINT32 RxPowerStateInRxs2:3 ; ///< |
| 7032 | UINT32 PllPowerStateInTxs2:3 ; ///< |
| 7033 | UINT32 PllPowerStateInOff:3 ; ///< |
| 7034 | UINT32 Reserved_15_13:3 ; ///< |
| 7035 | UINT32 Tx2p5clkClockGatingEn:1 ; ///< |
| 7036 | UINT32 Reserved_23_17:7 ; ///< |
| 7037 | UINT32 PllRampUpTime:3 ; ///< |
| 7038 | UINT32 Reserved_27_27:1 ; ///< |
| 7039 | UINT32 PllPwrOverrideEn:1 ; ///< |
| 7040 | UINT32 PllPwrOverrideVal:3 ; ///< |
| 7041 | } Field; ///< |
| 7042 | UINT32 Value; ///< |
| 7043 | } D0F0xE4_PIF_0013_STRUCT; |
| 7044 | |
| 7045 | // **** D0F0xE4_PIF_0015 Register Definition **** |
| 7046 | // Address |
| 7047 | #define D0F0xE4_PIF_0015_ADDRESS 0x15 |
| 7048 | |
| 7049 | // Type |
| 7050 | #define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4 |
| 7051 | // Field Data |
| 7052 | #define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0 |
| 7053 | #define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1 |
| 7054 | #define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1 |
| 7055 | #define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1 |
| 7056 | #define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1 |
| 7057 | #define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2 |
| 7058 | #define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2 |
| 7059 | #define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1 |
| 7060 | #define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4 |
| 7061 | #define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3 |
| 7062 | #define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1 |
| 7063 | #define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8 |
| 7064 | #define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4 |
| 7065 | #define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1 |
| 7066 | #define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10 |
| 7067 | #define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5 |
| 7068 | #define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1 |
| 7069 | #define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20 |
| 7070 | #define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6 |
| 7071 | #define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1 |
| 7072 | #define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40 |
| 7073 | #define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7 |
| 7074 | #define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1 |
| 7075 | #define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80 |
| 7076 | #define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8 |
| 7077 | #define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24 |
| 7078 | #define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00 |
| 7079 | |
| 7080 | /// D0F0xE4_PIF_0015 |
| 7081 | typedef union { |
| 7082 | struct { ///< |
| 7083 | UINT32 TxPhyStatus00:1 ; ///< |
| 7084 | UINT32 TxPhyStatus01:1 ; ///< |
| 7085 | UINT32 TxPhyStatus02:1 ; ///< |
| 7086 | UINT32 TxPhyStatus03:1 ; ///< |
| 7087 | UINT32 TxPhyStatus04:1 ; ///< |
| 7088 | UINT32 TxPhyStatus05:1 ; ///< |
| 7089 | UINT32 TxPhyStatus06:1 ; ///< |
| 7090 | UINT32 TxPhyStatus07:1 ; ///< |
| 7091 | UINT32 Reserved_31_8:24; ///< |
| 7092 | } Field; ///< |
| 7093 | UINT32 Value; ///< |
| 7094 | } D0F0xE4_PIF_0015_STRUCT; |
| 7095 | |
| 7096 | // **** D0F0xE4_CORE_0002 Register Definition **** |
| 7097 | // Address |
| 7098 | #define D0F0xE4_CORE_0002_ADDRESS 0x2 |
| 7099 | |
| 7100 | // Type |
| 7101 | #define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 |
| 7102 | // Field Data |
| 7103 | #define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0 |
| 7104 | #define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1 |
| 7105 | #define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1 |
| 7106 | #define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 |
| 7107 | #define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 |
| 7108 | #define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe |
| 7109 | |
| 7110 | /// D0F0xE4_CORE_0002 |
| 7111 | typedef union { |
| 7112 | struct { ///< |
| 7113 | UINT32 HwDebug_0_:1 ; ///< |
| 7114 | UINT32 Reserved_31_1:31; ///< |
| 7115 | } Field; ///< |
| 7116 | UINT32 Value; ///< |
| 7117 | } D0F0xE4_CORE_0002_STRUCT; |
| 7118 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 7119 | // **** D0F0xE4_CORE_0010 Register Definition **** |
| 7120 | // Address |
| 7121 | #define D0F0xE4_CORE_0010_ADDRESS 0x10 |
| 7122 | |
| 7123 | // Type |
| 7124 | #define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 |
| 7125 | // Field Data |
| 7126 | #define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 |
| 7127 | #define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 |
| 7128 | #define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 |
| 7129 | #define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 |
| 7130 | #define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 |
| 7131 | #define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe |
| 7132 | #define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 |
| 7133 | #define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 |
| 7134 | #define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 |
| 7135 | #define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 |
| 7136 | #define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 |
| 7137 | #define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 |
| 7138 | #define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 |
| 7139 | #define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 |
| 7140 | #define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 |
| 7141 | |
| 7142 | /// D0F0xE4_CORE_0010 |
| 7143 | typedef union { |
| 7144 | struct { ///< |
| 7145 | UINT32 HwInitWrLock:1 ; ///< |
| 7146 | UINT32 Reserved_8_1:8 ; ///< |
| 7147 | UINT32 UmiNpMemWrite:1 ; ///< |
| 7148 | UINT32 RxSbAdjPayloadSize:3 ; ///< |
| 7149 | UINT32 Reserved_31_13:19; ///< |
| 7150 | } Field; ///< |
| 7151 | UINT32 Value; ///< |
| 7152 | } D0F0xE4_CORE_0010_STRUCT; |
| 7153 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 7154 | // **** D0F0xE4_CORE_0011 Register Definition **** |
| 7155 | // Address |
| 7156 | #define D0F0xE4_CORE_0011_ADDRESS 0x11 |
| 7157 | |
| 7158 | // Type |
| 7159 | #define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 |
| 7160 | // Field Data |
| 7161 | #define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 |
| 7162 | #define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 |
| 7163 | #define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf |
| 7164 | #define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 |
| 7165 | #define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 |
| 7166 | #define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xfffffff0 |
| 7167 | |
| 7168 | /// D0F0xE4_CORE_0011 |
| 7169 | typedef union { |
| 7170 | struct { ///< |
| 7171 | UINT32 DynClkLatency:4 ; ///< |
| 7172 | UINT32 Reserved_31_4:28; ///< |
| 7173 | } Field; ///< |
| 7174 | UINT32 Value; ///< |
| 7175 | } D0F0xE4_CORE_0011_STRUCT; |
| 7176 | |
| 7177 | // **** D0F0xE4_CORE_001C Register Definition **** |
| 7178 | // Address |
| 7179 | #define D0F0xE4_CORE_001C_ADDRESS 0x1c |
| 7180 | |
| 7181 | // Type |
| 7182 | #define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 |
| 7183 | // Field Data |
| 7184 | #define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 |
| 7185 | #define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 |
| 7186 | #define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 |
| 7187 | #define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 |
| 7188 | #define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 |
| 7189 | #define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e |
| 7190 | #define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 |
| 7191 | #define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 |
| 7192 | #define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0 |
| 7193 | #define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 |
| 7194 | #define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 |
| 7195 | #define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800 |
| 7196 | |
| 7197 | /// D0F0xE4_CORE_001C |
| 7198 | typedef union { |
| 7199 | struct { ///< |
| 7200 | UINT32 TxArbRoundRobinEn:1 ; ///< |
| 7201 | UINT32 TxArbSlvLimit:5 ; ///< |
| 7202 | UINT32 TxArbMstLimit:5 ; ///< |
| 7203 | UINT32 Reserved_31_11:21; ///< |
| 7204 | } Field; ///< |
| 7205 | UINT32 Value; ///< |
| 7206 | } D0F0xE4_CORE_001C_STRUCT; |
| 7207 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 7208 | // **** D0F0xE4_CORE_0020 Register Definition **** |
| 7209 | // Address |
| 7210 | #define D0F0xE4_CORE_0020_ADDRESS 0x20 |
| 7211 | |
| 7212 | // Type |
| 7213 | #define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 |
| 7214 | // Field Data |
| 7215 | #define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 |
| 7216 | #define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 |
| 7217 | #define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff |
| 7218 | #define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 |
| 7219 | #define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 |
| 7220 | #define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 |
| 7221 | #define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 |
| 7222 | #define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 |
| 7223 | #define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 |
| 7224 | |
| 7225 | /// D0F0xE4_CORE_0020 |
| 7226 | typedef union { |
| 7227 | struct { ///< |
| 7228 | UINT32 Reserved_8_0:9 ; ///< |
| 7229 | UINT32 CiRcOrderingDis:1 ; ///< |
| 7230 | UINT32 Reserved_31_10:22; ///< |
| 7231 | } Field; ///< |
| 7232 | UINT32 Value; ///< |
| 7233 | } D0F0xE4_CORE_0020_STRUCT; |
| 7234 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 7235 | // **** D0F0xE4_CORE_0040 Register Definition **** |
| 7236 | // Address |
| 7237 | #define D0F0xE4_CORE_0040_ADDRESS 0x40 |
| 7238 | |
| 7239 | // Type |
| 7240 | #define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 |
| 7241 | // Field Data |
| 7242 | #define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 |
| 7243 | #define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 |
| 7244 | #define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff |
| 7245 | #define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 |
| 7246 | #define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 |
| 7247 | #define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000 |
| 7248 | #define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 |
| 7249 | #define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 |
| 7250 | #define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000 |
| 7251 | |
| 7252 | /// D0F0xE4_CORE_0040 |
| 7253 | typedef union { |
| 7254 | struct { ///< |
| 7255 | UINT32 Reserved_13_0:14; ///< |
| 7256 | UINT32 PElecIdleMode:2 ; ///< |
| 7257 | UINT32 Reserved_31_16:16; ///< |
| 7258 | } Field; ///< |
| 7259 | UINT32 Value; ///< |
| 7260 | } D0F0xE4_CORE_0040_STRUCT; |
| 7261 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 7262 | // **** D0F0xE4_CORE_00B0 Register Definition **** |
| 7263 | // Address |
| 7264 | #define D0F0xE4_CORE_00B0_ADDRESS 0xb0 |
| 7265 | |
| 7266 | // Type |
| 7267 | #define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 |
| 7268 | // Field Data |
| 7269 | #define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 |
| 7270 | #define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 |
| 7271 | #define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 |
| 7272 | #define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 |
| 7273 | #define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 |
| 7274 | #define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 |
| 7275 | #define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3 |
| 7276 | #define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29 |
| 7277 | #define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8 |
| 7278 | |
| 7279 | /// D0F0xE4_CORE_00B0 |
| 7280 | typedef union { |
| 7281 | struct { ///< |
| 7282 | UINT32 Reserved_1_0:2 ; ///< |
| 7283 | UINT32 StrapF0MsiEn:1 ; ///< |
| 7284 | UINT32 Reserved_31_3:29; ///< |
| 7285 | } Field; ///< |
| 7286 | UINT32 Value; ///< |
| 7287 | } D0F0xE4_CORE_00B0_STRUCT; |
| 7288 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 7289 | // **** D0F0xE4_CORE_00C0 Register Definition **** |
| 7290 | // Address |
| 7291 | #define D0F0xE4_CORE_00C0_ADDRESS 0xc0 |
| 7292 | |
| 7293 | // Type |
| 7294 | #define D0F0xE4_CORE_00C0_TYPE TYPE_D0F0xE4 |
| 7295 | // Field Data |
| 7296 | #define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET 0 |
| 7297 | #define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH 28 |
| 7298 | #define D0F0xE4_CORE_00C0_Reserved_27_0_MASK 0xfffffff |
| 7299 | #define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET 28 |
| 7300 | #define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH 1 |
| 7301 | #define D0F0xE4_CORE_00C0_StrapReverseAll_MASK 0x10000000 |
| 7302 | #define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET 29 |
| 7303 | #define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH 1 |
| 7304 | #define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK 0x20000000 |
| 7305 | #define D0F0xE4_CORE_00C0_Reserved_31_30_OFFSET 30 |
| 7306 | #define D0F0xE4_CORE_00C0_Reserved_31_30_WIDTH 2 |
| 7307 | #define D0F0xE4_CORE_00C0_Reserved_31_30_MASK 0xc0000000 |
| 7308 | |
| 7309 | /// D0F0xE4_CORE_00C0 |
| 7310 | typedef union { |
| 7311 | struct { ///< |
| 7312 | UINT32 Reserved_27_0:28; ///< |
| 7313 | UINT32 StrapReverseAll:1 ; ///< |
| 7314 | UINT32 StrapMstAdr64En:1 ; ///< |
| 7315 | UINT32 Reserved_31_30:2 ; ///< |
| 7316 | } Field; ///< |
| 7317 | UINT32 Value; ///< |
| 7318 | } D0F0xE4_CORE_00C0_STRUCT; |
| 7319 | |
| 7320 | // **** D0F0xE4_CORE_00C1 Register Definition **** |
| 7321 | // Address |
| 7322 | #define D0F0xE4_CORE_00C1_ADDRESS 0xc1 |
| 7323 | |
| 7324 | // Type |
| 7325 | #define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 |
| 7326 | // Field Data |
| 7327 | #define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 |
| 7328 | #define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 |
| 7329 | #define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 |
| 7330 | #define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 |
| 7331 | #define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 |
| 7332 | #define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 |
| 7333 | #define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 |
| 7334 | #define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 |
| 7335 | #define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc |
| 7336 | |
| 7337 | /// D0F0xE4_CORE_00C1 |
| 7338 | typedef union { |
| 7339 | struct { ///< |
| 7340 | UINT32 StrapLinkBwNotificationCapEn:1 ; ///< |
| 7341 | UINT32 StrapGen2Compliance:1 ; ///< |
| 7342 | UINT32 Reserved_31_2:30; ///< |
| 7343 | } Field; ///< |
| 7344 | UINT32 Value; ///< |
| 7345 | } D0F0xE4_CORE_00C1_STRUCT; |
| 7346 | |
| 7347 | // **** D0F0xE4_PHY_4004 Register Definition **** |
| 7348 | // Address |
| 7349 | #define D0F0xE4_PHY_4004_ADDRESS 0x4004 |
| 7350 | |
| 7351 | // Type |
| 7352 | #define D0F0xE4_PHY_4004_TYPE TYPE_D0F0xE4 |
| 7353 | // Field Data |
| 7354 | #define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET 0 |
| 7355 | #define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_WIDTH 1 |
| 7356 | #define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK 0x1 |
| 7357 | #define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET 1 |
| 7358 | #define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_WIDTH 1 |
| 7359 | #define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK 0x2 |
| 7360 | #define D0F0xE4_PHY_4004_Reserved_31_2_OFFSET 2 |
| 7361 | #define D0F0xE4_PHY_4004_Reserved_31_2_WIDTH 30 |
| 7362 | #define D0F0xE4_PHY_4004_Reserved_31_2_MASK 0xfffffffc |
| 7363 | |
| 7364 | /// D0F0xE4_PHY_4004 |
| 7365 | typedef union { |
| 7366 | struct { ///< |
| 7367 | UINT32 PllBiasGenPdnbOvrdEn:1 ; ///< |
| 7368 | UINT32 PllBiasGenPdnbOvrdVal:1 ; ///< |
| 7369 | UINT32 Reserved_31_2:30; ///< |
| 7370 | } Field; ///< |
| 7371 | UINT32 Value; ///< |
| 7372 | } D0F0xE4_PHY_4004_STRUCT; |
| 7373 | |
| 7374 | // **** DxF0xE4_x02 Register Definition **** |
| 7375 | // Address |
| 7376 | #define DxF0xE4_x02_ADDRESS 0x2 |
| 7377 | |
| 7378 | // Type |
| 7379 | #define DxF0xE4_x02_TYPE TYPE_D4F0xE4 |
| 7380 | // Field Data |
| 7381 | #define DxF0xE4_x02_Reserved_14_0_OFFSET 0 |
| 7382 | #define DxF0xE4_x02_Reserved_14_0_WIDTH 15 |
| 7383 | #define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff |
| 7384 | #define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15 |
| 7385 | #define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1 |
| 7386 | #define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000 |
| 7387 | #define DxF0xE4_x02_Reserved_31_16_OFFSET 16 |
| 7388 | #define DxF0xE4_x02_Reserved_31_16_WIDTH 16 |
| 7389 | #define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000 |
| 7390 | |
| 7391 | /// DxF0xE4_x02 |
| 7392 | typedef union { |
| 7393 | struct { ///< |
| 7394 | UINT32 Reserved_14_0:15; ///< |
| 7395 | UINT32 RegsLcAllowTxL1Control:1 ; ///< |
| 7396 | UINT32 Reserved_31_16:16; ///< |
| 7397 | } Field; ///< |
| 7398 | UINT32 Value; ///< |
| 7399 | } DxF0xE4_x02_STRUCT; |
| 7400 | |
| 7401 | // **** DxF0xE4_x20 Register Definition **** |
| 7402 | // Address |
| 7403 | #define DxF0xE4_x20_ADDRESS 0x20 |
| 7404 | |
| 7405 | // Type |
| 7406 | #define DxF0xE4_x20_TYPE TYPE_D4F0xE4 |
| 7407 | // Field Data |
| 7408 | #define DxF0xE4_x20_Reserved_14_0_OFFSET 0 |
| 7409 | #define DxF0xE4_x20_Reserved_14_0_WIDTH 15 |
| 7410 | #define DxF0xE4_x20_Reserved_14_0_MASK 0x7fff |
| 7411 | #define DxF0xE4_x20_TxFlushTlpDis_OFFSET 15 |
| 7412 | #define DxF0xE4_x20_TxFlushTlpDis_WIDTH 1 |
| 7413 | #define DxF0xE4_x20_TxFlushTlpDis_MASK 0x8000 |
| 7414 | #define DxF0xE4_x20_Reserved_31_16_OFFSET 16 |
| 7415 | #define DxF0xE4_x20_Reserved_31_16_WIDTH 16 |
| 7416 | #define DxF0xE4_x20_Reserved_31_16_MASK 0xffff0000 |
| 7417 | |
| 7418 | /// DxF0xE4_x20 |
| 7419 | typedef union { |
| 7420 | struct { ///< |
| 7421 | UINT32 Reserved_14_0:15; ///< |
| 7422 | UINT32 TxFlushTlpDis:1 ; ///< |
| 7423 | UINT32 Reserved_31_16:16; ///< |
| 7424 | } Field; ///< |
| 7425 | UINT32 Value; ///< |
| 7426 | } DxF0xE4_x20_STRUCT; |
| 7427 | |
| 7428 | // **** DxF0xE4_x50 Register Definition **** |
| 7429 | // Address |
| 7430 | #define DxF0xE4_x50_ADDRESS 0x50 |
| 7431 | |
| 7432 | // Type |
| 7433 | #define DxF0xE4_x50_TYPE TYPE_D4F0xE4 |
| 7434 | // Field Data |
| 7435 | #define DxF0xE4_x50_PortLaneReversal_OFFSET 0 |
| 7436 | #define DxF0xE4_x50_PortLaneReversal_WIDTH 1 |
| 7437 | #define DxF0xE4_x50_PortLaneReversal_MASK 0x1 |
| 7438 | #define DxF0xE4_x50_PhyLinkWidth_OFFSET 1 |
| 7439 | #define DxF0xE4_x50_PhyLinkWidth_WIDTH 6 |
| 7440 | #define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e |
| 7441 | #define DxF0xE4_x50_Reserved_31_7_OFFSET 7 |
| 7442 | #define DxF0xE4_x50_Reserved_31_7_WIDTH 25 |
| 7443 | #define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80 |
| 7444 | |
| 7445 | /// DxF0xE4_x50 |
| 7446 | typedef union { |
| 7447 | struct { ///< |
| 7448 | UINT32 PortLaneReversal:1 ; ///< |
| 7449 | UINT32 PhyLinkWidth:6 ; ///< |
| 7450 | UINT32 Reserved_31_7:25; ///< |
| 7451 | } Field; ///< |
| 7452 | UINT32 Value; ///< |
| 7453 | } DxF0xE4_x50_STRUCT; |
| 7454 | |
| 7455 | // **** DxF0xE4_x70 Register Definition **** |
| 7456 | // Address |
| 7457 | #define DxF0xE4_x70_ADDRESS 0x70 |
| 7458 | |
| 7459 | // Type |
| 7460 | #define DxF0xE4_x70_TYPE TYPE_D4F0xE4 |
| 7461 | // Field Data |
| 7462 | #define DxF0xE4_x70_Reserved_15_0_OFFSET 0 |
| 7463 | #define DxF0xE4_x70_Reserved_15_0_WIDTH 16 |
| 7464 | #define DxF0xE4_x70_Reserved_15_0_MASK 0xffff |
| 7465 | #define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16 |
| 7466 | #define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3 |
| 7467 | #define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000 |
| 7468 | #define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19 |
| 7469 | #define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1 |
| 7470 | #define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 |
| 7471 | #define DxF0xE4_x70_Reserved_31_20_OFFSET 20 |
| 7472 | #define DxF0xE4_x70_Reserved_31_20_WIDTH 12 |
| 7473 | #define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000 |
| 7474 | |
| 7475 | /// DxF0xE4_x70 |
| 7476 | typedef union { |
| 7477 | struct { ///< |
| 7478 | UINT32 Reserved_15_0:16; ///< |
| 7479 | UINT32 RxRcbCplTimeout:3 ; ///< |
| 7480 | UINT32 RxRcbCplTimeoutMode:1 ; ///< |
| 7481 | UINT32 Reserved_31_20:12; ///< |
| 7482 | } Field; ///< |
| 7483 | UINT32 Value; ///< |
| 7484 | } DxF0xE4_x70_STRUCT; |
| 7485 | |
| 7486 | // **** DxF0xE4_xA0 Register Definition **** |
| 7487 | // Address |
| 7488 | #define DxF0xE4_xA0_ADDRESS 0xa0 |
| 7489 | |
| 7490 | // Type |
| 7491 | #define DxF0xE4_xA0_TYPE TYPE_D4F0xE4 |
| 7492 | // Field Data |
| 7493 | #define DxF0xE4_xA0_Reserved_3_0_OFFSET 0 |
| 7494 | #define DxF0xE4_xA0_Reserved_3_0_WIDTH 4 |
| 7495 | #define DxF0xE4_xA0_Reserved_3_0_MASK 0xf |
| 7496 | #define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4 |
| 7497 | #define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4 |
| 7498 | #define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0 |
| 7499 | #define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8 |
| 7500 | #define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4 |
| 7501 | #define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00 |
| 7502 | #define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12 |
| 7503 | #define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4 |
| 7504 | #define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000 |
| 7505 | #define DxF0xE4_xA0_Reserved_22_16_OFFSET 16 |
| 7506 | #define DxF0xE4_xA0_Reserved_22_16_WIDTH 7 |
| 7507 | #define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000 |
| 7508 | #define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23 |
| 7509 | #define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1 |
| 7510 | #define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000 |
| 7511 | #define DxF0xE4_xA0_Reserved_31_24_OFFSET 24 |
| 7512 | #define DxF0xE4_xA0_Reserved_31_24_WIDTH 8 |
| 7513 | #define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000 |
| 7514 | |
| 7515 | /// DxF0xE4_xA0 |
| 7516 | typedef union { |
| 7517 | struct { ///< |
| 7518 | UINT32 Reserved_3_0:4 ; ///< |
| 7519 | UINT32 Lc16xClearTxPipe:4 ; ///< |
| 7520 | UINT32 LcL0sInactivity:4 ; ///< |
| 7521 | UINT32 LcL1Inactivity:4 ; ///< |
| 7522 | UINT32 Reserved_22_16:7 ; ///< |
| 7523 | UINT32 LcL1ImmediateAck:1 ; ///< |
| 7524 | UINT32 Reserved_31_24:8 ; ///< |
| 7525 | } Field; ///< |
| 7526 | UINT32 Value; ///< |
| 7527 | } DxF0xE4_xA0_STRUCT; |
| 7528 | |
| 7529 | // **** DxF0xE4_xA1 Register Definition **** |
| 7530 | // Address |
| 7531 | #define DxF0xE4_xA1_ADDRESS 0xa1 |
| 7532 | |
| 7533 | // Type |
| 7534 | #define DxF0xE4_xA1_TYPE TYPE_D4F0xE4 |
| 7535 | // Field Data |
| 7536 | #define DxF0xE4_xA1_Reserved_10_0_OFFSET 0 |
| 7537 | #define DxF0xE4_xA1_Reserved_10_0_WIDTH 11 |
| 7538 | #define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff |
| 7539 | #define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 |
| 7540 | #define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 |
| 7541 | #define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 |
| 7542 | #define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12 |
| 7543 | #define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1 |
| 7544 | #define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000 |
| 7545 | #define DxF0xE4_xA1_Reserved_31_13_OFFSET 13 |
| 7546 | #define DxF0xE4_xA1_Reserved_31_13_WIDTH 19 |
| 7547 | #define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000 |
| 7548 | |
| 7549 | /// DxF0xE4_xA1 |
| 7550 | typedef union { |
| 7551 | struct { ///< |
| 7552 | UINT32 Reserved_10_0:11; ///< |
| 7553 | UINT32 LcDontGotoL0sifL1Armed:1 ; ///< |
| 7554 | UINT32 LcInitSpdChgWithCsrEn:1 ; ///< |
| 7555 | UINT32 Reserved_31_13:19; ///< |
| 7556 | } Field; ///< |
| 7557 | UINT32 Value; ///< |
| 7558 | } DxF0xE4_xA1_STRUCT; |
| 7559 | |
| 7560 | // **** DxF0xE4_xA2 Register Definition **** |
| 7561 | // Address |
| 7562 | #define DxF0xE4_xA2_ADDRESS 0xa2 |
| 7563 | |
| 7564 | // Type |
| 7565 | #define DxF0xE4_xA2_TYPE TYPE_D4F0xE4 |
| 7566 | // Field Data |
| 7567 | #define DxF0xE4_xA2_LcLinkWidth_OFFSET 0 |
| 7568 | #define DxF0xE4_xA2_LcLinkWidth_WIDTH 3 |
| 7569 | #define DxF0xE4_xA2_LcLinkWidth_MASK 0x7 |
| 7570 | #define DxF0xE4_xA2_Reserved_3_3_OFFSET 3 |
| 7571 | #define DxF0xE4_xA2_Reserved_3_3_WIDTH 1 |
| 7572 | #define DxF0xE4_xA2_Reserved_3_3_MASK 0x8 |
| 7573 | #define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4 |
| 7574 | #define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3 |
| 7575 | #define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70 |
| 7576 | #define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 |
| 7577 | #define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 |
| 7578 | #define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 |
| 7579 | #define DxF0xE4_xA2_LcReconfigNow_OFFSET 8 |
| 7580 | #define DxF0xE4_xA2_LcReconfigNow_WIDTH 1 |
| 7581 | #define DxF0xE4_xA2_LcReconfigNow_MASK 0x100 |
| 7582 | #define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9 |
| 7583 | #define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1 |
| 7584 | #define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200 |
| 7585 | #define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10 |
| 7586 | #define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1 |
| 7587 | #define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400 |
| 7588 | #define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11 |
| 7589 | #define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1 |
| 7590 | #define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800 |
| 7591 | #define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12 |
| 7592 | #define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1 |
| 7593 | #define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000 |
| 7594 | #define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13 |
| 7595 | #define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1 |
| 7596 | #define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000 |
| 7597 | #define DxF0xE4_xA2_Reserved_19_14_OFFSET 14 |
| 7598 | #define DxF0xE4_xA2_Reserved_19_14_WIDTH 6 |
| 7599 | #define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000 |
| 7600 | #define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20 |
| 7601 | #define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1 |
| 7602 | #define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000 |
| 7603 | #define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21 |
| 7604 | #define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2 |
| 7605 | #define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000 |
| 7606 | #define DxF0xE4_xA2_Reserved_31_23_OFFSET 23 |
| 7607 | #define DxF0xE4_xA2_Reserved_31_23_WIDTH 9 |
| 7608 | #define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000 |
| 7609 | |
| 7610 | /// DxF0xE4_xA2 |
| 7611 | typedef union { |
| 7612 | struct { ///< |
| 7613 | UINT32 LcLinkWidth:3 ; ///< |
| 7614 | UINT32 Reserved_3_3:1 ; ///< |
| 7615 | UINT32 LcLinkWidthRd:3 ; ///< |
| 7616 | UINT32 LcReconfigArcMissingEscape:1 ; ///< |
| 7617 | UINT32 LcReconfigNow:1 ; ///< |
| 7618 | UINT32 LcRenegotiationSupport:1 ; ///< |
| 7619 | UINT32 LcRenegotiateEn:1 ; ///< |
| 7620 | UINT32 LcShortReconfigEn:1 ; ///< |
| 7621 | UINT32 LcUpconfigureSupport:1 ; ///< |
| 7622 | UINT32 LcUpconfigureDis:1 ; ///< |
| 7623 | UINT32 Reserved_19_14:6 ; ///< |
| 7624 | UINT32 LcUpconfigCapable:1 ; ///< |
| 7625 | UINT32 LcDynLanesPwrState:2 ; ///< |
| 7626 | UINT32 Reserved_31_23:9 ; ///< |
| 7627 | } Field; ///< |
| 7628 | UINT32 Value; ///< |
| 7629 | } DxF0xE4_xA2_STRUCT; |
| 7630 | |
| 7631 | // **** DxF0xE4_xA3 Register Definition **** |
| 7632 | // Address |
| 7633 | #define DxF0xE4_xA3_ADDRESS 0xa3 |
| 7634 | |
| 7635 | // Type |
| 7636 | #define DxF0xE4_xA3_TYPE TYPE_D4F0xE4 |
| 7637 | // Field Data |
| 7638 | #define DxF0xE4_xA3_Reserved_8_0_OFFSET 0 |
| 7639 | #define DxF0xE4_xA3_Reserved_8_0_WIDTH 9 |
| 7640 | #define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff |
| 7641 | #define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 |
| 7642 | #define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 |
| 7643 | #define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 |
| 7644 | #define DxF0xE4_xA3_Reserved_31_10_OFFSET 10 |
| 7645 | #define DxF0xE4_xA3_Reserved_31_10_WIDTH 22 |
| 7646 | #define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00 |
| 7647 | |
| 7648 | /// DxF0xE4_xA3 |
| 7649 | typedef union { |
| 7650 | struct { ///< |
| 7651 | UINT32 Reserved_8_0:9 ; ///< |
| 7652 | UINT32 LcXmitFtsBeforeRecovery:1 ; ///< |
| 7653 | UINT32 Reserved_31_10:22; ///< |
| 7654 | } Field; ///< |
| 7655 | UINT32 Value; ///< |
| 7656 | } DxF0xE4_xA3_STRUCT; |
| 7657 | |
| 7658 | // **** DxF0xE4_xA4 Register Definition **** |
| 7659 | // Address |
| 7660 | #define DxF0xE4_xA4_ADDRESS 0xa4 |
| 7661 | |
| 7662 | // Type |
| 7663 | #define DxF0xE4_xA4_TYPE TYPE_D4F0xE4 |
| 7664 | // Field Data |
| 7665 | #define DxF0xE4_xA4_LcGen2EnStrap_OFFSET 0 |
| 7666 | #define DxF0xE4_xA4_LcGen2EnStrap_WIDTH 1 |
| 7667 | #define DxF0xE4_xA4_LcGen2EnStrap_MASK 0x1 |
| 7668 | #define DxF0xE4_xA4_Reserved_3_1_OFFSET 1 |
| 7669 | #define DxF0xE4_xA4_Reserved_3_1_WIDTH 3 |
| 7670 | #define DxF0xE4_xA4_Reserved_3_1_MASK 0xe |
| 7671 | #define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET 4 |
| 7672 | #define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH 1 |
| 7673 | #define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK 0x10 |
| 7674 | #define DxF0xE4_xA4_Reserved_6_5_OFFSET 5 |
| 7675 | #define DxF0xE4_xA4_Reserved_6_5_WIDTH 2 |
| 7676 | #define DxF0xE4_xA4_Reserved_6_5_MASK 0x60 |
| 7677 | #define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET 7 |
| 7678 | #define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1 |
| 7679 | #define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK 0x80 |
| 7680 | #define DxF0xE4_xA4_LcSpeedChangeAttemptsAllowed_OFFSET 8 |
| 7681 | #define DxF0xE4_xA4_LcSpeedChangeAttemptsAllowed_WIDTH 2 |
| 7682 | #define DxF0xE4_xA4_LcSpeedChangeAttemptsAllowed_MASK 0x300 |
| 7683 | #define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 10 |
| 7684 | #define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1 |
| 7685 | #define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x400 |
| 7686 | #define DxF0xE4_xA4_Reserved_17_11_OFFSET 11 |
| 7687 | #define DxF0xE4_xA4_Reserved_17_11_WIDTH 7 |
| 7688 | #define DxF0xE4_xA4_Reserved_17_11_MASK 0x3f800 |
| 7689 | #define DxF0xE4_xA4_LcGoToRecovery_OFFSET 18 |
| 7690 | #define DxF0xE4_xA4_LcGoToRecovery_WIDTH 1 |
| 7691 | #define DxF0xE4_xA4_LcGoToRecovery_MASK 0x40000 |
| 7692 | #define DxF0xE4_xA4_Reserved_23_19_OFFSET 19 |
| 7693 | #define DxF0xE4_xA4_Reserved_23_19_WIDTH 5 |
| 7694 | #define DxF0xE4_xA4_Reserved_23_19_MASK 0xf80000 |
| 7695 | #define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET 24 |
| 7696 | #define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH 1 |
| 7697 | #define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK 0x1000000 |
| 7698 | #define DxF0xE4_xA4_Reserved_28_25_OFFSET 25 |
| 7699 | #define DxF0xE4_xA4_Reserved_28_25_WIDTH 4 |
| 7700 | #define DxF0xE4_xA4_Reserved_28_25_MASK 0x1e000000 |
| 7701 | #define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 29 |
| 7702 | #define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1 |
| 7703 | #define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x20000000 |
| 7704 | #define DxF0xE4_xA4_Reserved_31_30_OFFSET 30 |
| 7705 | #define DxF0xE4_xA4_Reserved_31_30_WIDTH 2 |
| 7706 | #define DxF0xE4_xA4_Reserved_31_30_MASK 0xc0000000 |
| 7707 | |
| 7708 | /// DxF0xE4_xA4 |
| 7709 | typedef union { |
| 7710 | struct { ///< |
| 7711 | UINT32 LcGen2EnStrap:1 ; ///< |
| 7712 | UINT32 Reserved_3_1:3 ; ///< |
| 7713 | UINT32 LcForceDisSwSpeedChange:1 ; ///< |
| 7714 | UINT32 Reserved_6_5:2 ; ///< |
| 7715 | UINT32 LcInitiateLinkSpeedChange:1 ; ///< |
| 7716 | UINT32 LcSpeedChangeAttemptsAllowed:2 ; ///< |
| 7717 | UINT32 LcSpeedChangeAttemptFailed:1 ; ///< |
| 7718 | UINT32 Reserved_17_11:7 ; ///< |
| 7719 | UINT32 LcGoToRecovery:1 ; ///< |
| 7720 | UINT32 Reserved_23_19:5 ; ///< |
| 7721 | UINT32 LcOtherSideSupportsGen2:1 ; ///< |
| 7722 | UINT32 Reserved_28_25:4 ; ///< |
| 7723 | UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< |
| 7724 | UINT32 Reserved_31_30:2 ; ///< |
| 7725 | } Field; ///< |
| 7726 | UINT32 Value; ///< |
| 7727 | } DxF0xE4_xA4_STRUCT; |
| 7728 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 7729 | // **** DxF0xE4_xA5 Register Definition **** |
| 7730 | // Address |
| 7731 | #define DxF0xE4_xA5_ADDRESS 0xa5 |
| 7732 | |
| 7733 | // Type |
| 7734 | #define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 |
| 7735 | // Field Data |
| 7736 | #define DxF0xE4_xA5_LcCurrentState_OFFSET 0 |
| 7737 | #define DxF0xE4_xA5_LcCurrentState_WIDTH 6 |
| 7738 | #define DxF0xE4_xA5_LcCurrentState_MASK 0x3f |
| 7739 | #define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 |
| 7740 | #define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 |
| 7741 | #define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 |
| 7742 | #define DxF0xE4_xA5_LcPrevState1_OFFSET 8 |
| 7743 | #define DxF0xE4_xA5_LcPrevState1_WIDTH 6 |
| 7744 | #define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 |
| 7745 | #define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 |
| 7746 | #define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 |
| 7747 | #define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 |
| 7748 | #define DxF0xE4_xA5_LcPrevState2_OFFSET 16 |
| 7749 | #define DxF0xE4_xA5_LcPrevState2_WIDTH 6 |
| 7750 | #define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 |
| 7751 | #define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 |
| 7752 | #define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 |
| 7753 | #define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 |
| 7754 | #define DxF0xE4_xA5_LcPrevState3_OFFSET 24 |
| 7755 | #define DxF0xE4_xA5_LcPrevState3_WIDTH 6 |
| 7756 | #define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 |
| 7757 | #define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 |
| 7758 | #define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 |
| 7759 | #define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 |
| 7760 | |
| 7761 | /// DxF0xE4_xA5 |
| 7762 | typedef union { |
| 7763 | struct { ///< |
| 7764 | UINT32 LcCurrentState:6 ; ///< |
| 7765 | UINT32 Reserved_7_6:2 ; ///< |
| 7766 | UINT32 LcPrevState1:6 ; ///< |
| 7767 | UINT32 Reserved_15_14:2 ; ///< |
| 7768 | UINT32 LcPrevState2:6 ; ///< |
| 7769 | UINT32 Reserved_23_22:2 ; ///< |
| 7770 | UINT32 LcPrevState3:6 ; ///< |
| 7771 | UINT32 Reserved_31_30:2 ; ///< |
| 7772 | } Field; ///< |
| 7773 | UINT32 Value; ///< |
| 7774 | } DxF0xE4_xA5_STRUCT; |
| 7775 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 7776 | // **** DxF0xE4_xB1 Register Definition **** |
| 7777 | // Address |
| 7778 | #define DxF0xE4_xB1_ADDRESS 0xb1 |
| 7779 | |
| 7780 | // Type |
| 7781 | #define DxF0xE4_xB1_TYPE TYPE_D4F0xE4 |
| 7782 | // Field Data |
| 7783 | #define DxF0xE4_xB1_Reserved_18_0_OFFSET 0 |
| 7784 | #define DxF0xE4_xB1_Reserved_18_0_WIDTH 19 |
| 7785 | #define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff |
| 7786 | #define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 |
| 7787 | #define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 |
| 7788 | #define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 |
| 7789 | #define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20 |
| 7790 | #define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1 |
| 7791 | #define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000 |
| 7792 | #define DxF0xE4_xB1_Reserved_31_21_OFFSET 21 |
| 7793 | #define DxF0xE4_xB1_Reserved_31_21_WIDTH 11 |
| 7794 | #define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000 |
| 7795 | |
| 7796 | /// DxF0xE4_xB1 |
| 7797 | typedef union { |
| 7798 | struct { ///< |
| 7799 | UINT32 Reserved_18_0:19; ///< |
| 7800 | UINT32 LcDeassertRxEnInL0s:1 ; ///< |
| 7801 | UINT32 LcBlockElIdleinL0:1 ; ///< |
| 7802 | UINT32 Reserved_31_21:11; ///< |
| 7803 | } Field; ///< |
| 7804 | UINT32 Value; ///< |
| 7805 | } DxF0xE4_xB1_STRUCT; |
| 7806 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 7807 | // **** DxF0xE4_xB5 Register Definition **** |
| 7808 | // Address |
| 7809 | #define DxF0xE4_xB5_ADDRESS 0xb5 |
| 7810 | |
| 7811 | // Type |
| 7812 | #define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 |
| 7813 | // Field Data |
| 7814 | #define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 |
| 7815 | #define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 |
| 7816 | #define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 |
| 7817 | #define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 |
| 7818 | #define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 |
| 7819 | #define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 |
| 7820 | #define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 |
| 7821 | #define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 |
| 7822 | #define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 |
| 7823 | #define DxF0xE4_xB5_Reserved_9_4_OFFSET 4 |
| 7824 | #define DxF0xE4_xB5_Reserved_9_4_WIDTH 6 |
| 7825 | #define DxF0xE4_xB5_Reserved_9_4_MASK 0x3f0 |
| 7826 | #define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 |
| 7827 | #define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 |
| 7828 | #define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 |
| 7829 | #define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 |
| 7830 | #define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 |
| 7831 | #define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 |
| 7832 | #define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 |
| 7833 | #define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 |
| 7834 | #define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 |
| 7835 | #define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 |
| 7836 | #define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 |
| 7837 | #define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 |
| 7838 | #define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 |
| 7839 | #define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 |
| 7840 | #define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 |
| 7841 | |
| 7842 | /// DxF0xE4_xB5 |
| 7843 | typedef union { |
| 7844 | struct { ///< |
| 7845 | UINT32 LcSelectDeemphasis:1 ; ///< |
| 7846 | UINT32 LcSelectDeemphasisCntl:2 ; ///< |
| 7847 | UINT32 LcRcvdDeemphasis:1 ; ///< |
| 7848 | UINT32 Reserved_9_4:6 ; ///< |
| 7849 | UINT32 LcEnhancedHotPlugEn:1 ; ///< |
| 7850 | UINT32 Reserved_11_11:1 ; ///< |
| 7851 | UINT32 LcEhpRxPhyCmd:2 ; ///< |
| 7852 | UINT32 LcEhpTxPhyCmd:2 ; ///< |
| 7853 | UINT32 Reserved_31_16:16; ///< |
| 7854 | } Field; ///< |
| 7855 | UINT32 Value; ///< |
| 7856 | } DxF0xE4_xB5_STRUCT; |
| 7857 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 7858 | // **** DxF0xE4_xC0 Register Definition **** |
| 7859 | // Address |
| 7860 | #define DxF0xE4_xC0_ADDRESS 0xc0 |
| 7861 | |
| 7862 | // Type |
| 7863 | #define DxF0xE4_xC0_TYPE TYPE_D4F0xE4 |
| 7864 | // Field Data |
| 7865 | #define DxF0xE4_xC0_Reserved_12_0_OFFSET 0 |
| 7866 | #define DxF0xE4_xC0_Reserved_12_0_WIDTH 13 |
| 7867 | #define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff |
| 7868 | #define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13 |
| 7869 | #define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1 |
| 7870 | #define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000 |
| 7871 | #define DxF0xE4_xC0_Reserved_14_14_OFFSET 14 |
| 7872 | #define DxF0xE4_xC0_Reserved_14_14_WIDTH 1 |
| 7873 | #define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000 |
| 7874 | #define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 |
| 7875 | #define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 |
| 7876 | #define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 |
| 7877 | #define DxF0xE4_xC0_Reserved_31_16_OFFSET 16 |
| 7878 | #define DxF0xE4_xC0_Reserved_31_16_WIDTH 16 |
| 7879 | #define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000 |
| 7880 | |
| 7881 | /// DxF0xE4_xC0 |
| 7882 | typedef union { |
| 7883 | struct { ///< |
| 7884 | UINT32 Reserved_12_0:13; ///< |
| 7885 | UINT32 StrapForceCompliance:1 ; ///< |
| 7886 | UINT32 Reserved_14_14:1 ; ///< |
| 7887 | UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< |
| 7888 | UINT32 Reserved_31_16:16; ///< |
| 7889 | } Field; ///< |
| 7890 | UINT32 Value; ///< |
| 7891 | } DxF0xE4_xC0_STRUCT; |
| 7892 | |
| 7893 | // **** DxF0xE4_xC1 Register Definition **** |
| 7894 | // Address |
| 7895 | #define DxF0xE4_xC1_ADDRESS 0xc1 |
| 7896 | |
| 7897 | // Type |
| 7898 | #define DxF0xE4_xC1_TYPE TYPE_D4F0xE4 |
| 7899 | // Field Data |
| 7900 | #define DxF0xE4_xC1_Reserved_3_0_OFFSET 0 |
| 7901 | #define DxF0xE4_xC1_Reserved_3_0_WIDTH 4 |
| 7902 | #define DxF0xE4_xC1_Reserved_3_0_MASK 0xf |
| 7903 | #define DxF0xE4_xC1_StrapReverseLanes_OFFSET 4 |
| 7904 | #define DxF0xE4_xC1_StrapReverseLanes_WIDTH 1 |
| 7905 | #define DxF0xE4_xC1_StrapReverseLanes_MASK 0x10 |
| 7906 | #define DxF0xE4_xC1_Reserved_31_5_OFFSET 5 |
| 7907 | #define DxF0xE4_xC1_Reserved_31_5_WIDTH 27 |
| 7908 | #define DxF0xE4_xC1_Reserved_31_5_MASK 0xffffffe0 |
| 7909 | |
| 7910 | /// DxF0xE4_xC1 |
| 7911 | typedef union { |
| 7912 | struct { ///< |
| 7913 | UINT32 Reserved_3_0:4 ; ///< |
| 7914 | UINT32 StrapReverseLanes:1 ; ///< |
| 7915 | UINT32 Reserved_31_5:27; ///< |
| 7916 | } Field; ///< |
| 7917 | UINT32 Value; ///< |
| 7918 | } DxF0xE4_xC1_STRUCT; |
| 7919 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 7920 | // **** SMUx01 Register Definition **** |
| 7921 | // Address |
| 7922 | #define SMUx01_ADDRESS 0x1 |
| 7923 | |
| 7924 | // Type |
| 7925 | #define SMUx01_TYPE TYPE_SMU |
| 7926 | // Field Data |
| 7927 | #define SMUx01_RamSwitch_OFFSET 0 |
| 7928 | #define SMUx01_RamSwitch_WIDTH 1 |
| 7929 | #define SMUx01_RamSwitch_MASK 0x1 |
| 7930 | #define SMUx01_Reset_OFFSET 1 |
| 7931 | #define SMUx01_Reset_WIDTH 1 |
| 7932 | #define SMUx01_Reset_MASK 0x2 |
| 7933 | #define SMUx01_Reserved_17_2_OFFSET 2 |
| 7934 | #define SMUx01_Reserved_17_2_WIDTH 16 |
| 7935 | #define SMUx01_Reserved_17_2_MASK 0x3fffc |
| 7936 | #define SMUx01_VectorOverride_OFFSET 18 |
| 7937 | #define SMUx01_VectorOverride_WIDTH 1 |
| 7938 | #define SMUx01_VectorOverride_MASK 0x40000 |
| 7939 | #define SMUx01_Reserved_31_19_OFFSET 19 |
| 7940 | #define SMUx01_Reserved_31_19_WIDTH 13 |
| 7941 | #define SMUx01_Reserved_31_19_MASK 0xfff80000 |
| 7942 | |
| 7943 | /// SMUx01 |
| 7944 | typedef union { |
| 7945 | struct { ///< |
| 7946 | UINT32 RamSwitch:1 ; ///< |
| 7947 | UINT32 Reset:1 ; ///< |
| 7948 | UINT32 Reserved_17_2:16; ///< |
| 7949 | UINT32 VectorOverride:1 ; ///< |
| 7950 | UINT32 Reserved_31_19:13; ///< |
| 7951 | } Field; ///< |
| 7952 | UINT32 Value; ///< |
| 7953 | } SMUx01_STRUCT; |
| 7954 | |
| 7955 | // **** SMUx03 Register Definition **** |
| 7956 | // Address |
| 7957 | #define SMUx03_ADDRESS 0x3 |
| 7958 | |
| 7959 | // Type |
| 7960 | #define SMUx03_TYPE TYPE_SMU |
| 7961 | // Field Data |
| 7962 | #define SMUx03_IntReq_OFFSET 0 |
| 7963 | #define SMUx03_IntReq_WIDTH 1 |
| 7964 | #define SMUx03_IntReq_MASK 0x1 |
| 7965 | #define SMUx03_IntAck_OFFSET 1 |
| 7966 | #define SMUx03_IntAck_WIDTH 1 |
| 7967 | #define SMUx03_IntAck_MASK 0x2 |
| 7968 | #define SMUx03_IntDone_OFFSET 2 |
| 7969 | #define SMUx03_IntDone_WIDTH 1 |
| 7970 | #define SMUx03_IntDone_MASK 0x4 |
| 7971 | #define SMUx03_ServiceIndex_OFFSET 3 |
| 7972 | #define SMUx03_ServiceIndex_WIDTH 8 |
| 7973 | #define SMUx03_ServiceIndex_MASK 0x7f8 |
| 7974 | #define SMUx03_Reserved_31_11_OFFSET 11 |
| 7975 | #define SMUx03_Reserved_31_11_WIDTH 21 |
| 7976 | #define SMUx03_Reserved_31_11_MASK 0xfffff800 |
| 7977 | |
| 7978 | /// SMUx03 |
| 7979 | typedef union { |
| 7980 | struct { ///< |
| 7981 | UINT32 IntReq:1 ; ///< |
| 7982 | UINT32 IntAck:1 ; ///< |
| 7983 | UINT32 IntDone:1 ; ///< |
| 7984 | UINT32 ServiceIndex:8 ; ///< |
| 7985 | UINT32 Reserved_31_11:21; ///< |
| 7986 | } Field; ///< |
| 7987 | UINT32 Value; ///< |
| 7988 | } SMUx03_STRUCT; |
| 7989 | |
| 7990 | // **** SMUx05 Register Definition **** |
| 7991 | // Address |
| 7992 | #define SMUx05_ADDRESS 0x5 |
| 7993 | |
| 7994 | // Type |
| 7995 | #define SMUx05_TYPE TYPE_SMU |
| 7996 | // Field Data |
| 7997 | #define SMUx05_McuRam_OFFSET 0 |
| 7998 | #define SMUx05_McuRam_WIDTH 32 |
| 7999 | #define SMUx05_McuRam_MASK 0xffffffff |
| 8000 | |
| 8001 | /// SMUx05 |
| 8002 | typedef union { |
| 8003 | struct { ///< |
| 8004 | UINT32 McuRam:32; ///< |
| 8005 | } Field; ///< |
| 8006 | UINT32 Value; ///< |
| 8007 | } SMUx05_STRUCT; |
| 8008 | |
| 8009 | // **** SMUx0B_x8580 Register Definition **** |
| 8010 | // Address |
| 8011 | #define SMUx0B_x8580_ADDRESS 0x8580 |
| 8012 | |
| 8013 | // Type |
| 8014 | #define SMUx0B_x8580_TYPE TYPE_SMUx0B |
| 8015 | // Field Data |
| 8016 | #define SMUx0B_x8580_Reserved_0_0_OFFSET 0 |
| 8017 | #define SMUx0B_x8580_Reserved_0_0_WIDTH 1 |
| 8018 | #define SMUx0B_x8580_Reserved_0_0_MASK 0x1 |
| 8019 | #define SMUx0B_x8580_Reserved_9_1_OFFSET 1 |
| 8020 | #define SMUx0B_x8580_Reserved_9_1_WIDTH 9 |
| 8021 | #define SMUx0B_x8580_Reserved_9_1_MASK 0x3fe |
| 8022 | #define SMUx0B_x8580_Reserved_10_10_OFFSET 10 |
| 8023 | #define SMUx0B_x8580_Reserved_10_10_WIDTH 1 |
| 8024 | #define SMUx0B_x8580_Reserved_10_10_MASK 0x400 |
| 8025 | #define SMUx0B_x8580_Reserved_11_11_OFFSET 11 |
| 8026 | #define SMUx0B_x8580_Reserved_11_11_WIDTH 1 |
| 8027 | #define SMUx0B_x8580_Reserved_11_11_MASK 0x800 |
| 8028 | #define SMUx0B_x8580_Reserved_15_12_OFFSET 12 |
| 8029 | #define SMUx0B_x8580_Reserved_15_12_WIDTH 4 |
| 8030 | #define SMUx0B_x8580_Reserved_15_12_MASK 0xf000 |
| 8031 | #define SMUx0B_x8580_Reserved_31_16_OFFSET 16 |
| 8032 | #define SMUx0B_x8580_Reserved_31_16_WIDTH 16 |
| 8033 | #define SMUx0B_x8580_Reserved_31_16_MASK 0xffff0000 |
| 8034 | |
| 8035 | /// SMUx0B_x8580 |
| 8036 | typedef union { |
| 8037 | struct { ///< |
| 8038 | UINT32 PdmEn:1 ; ///< |
| 8039 | UINT32 Reserved_9_1:9 ; ///< |
| 8040 | UINT32 PdmCacEn:1 ; ///< |
| 8041 | UINT32 PdmParamLoc:1 ; ///< |
| 8042 | UINT32 PdmUnit:4 ; ///< |
| 8043 | UINT32 PdmPeriod:16; ///< |
| 8044 | } Field; ///< |
| 8045 | UINT32 Value; ///< |
| 8046 | } SMUx0B_x8580_STRUCT; |
| 8047 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 8048 | // **** SMUx0B_x8600 Register Definition **** |
| 8049 | // Address |
| 8050 | #define SMUx0B_x8600_ADDRESS 0x8600 |
| 8051 | |
| 8052 | // Type |
| 8053 | #define SMUx0B_x8600_TYPE TYPE_SMUx0B |
| 8054 | // Field Data |
| 8055 | #define SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET 0 |
| 8056 | #define SMUx0B_x8600_Txn1MBusAddr_7_0__WIDTH 8 |
| 8057 | #define SMUx0B_x8600_Txn1MBusAddr_7_0__MASK 0xff |
| 8058 | #define SMUx0B_x8600_MemAddr_7_0__OFFSET 8 |
| 8059 | #define SMUx0B_x8600_MemAddr_7_0__WIDTH 8 |
| 8060 | #define SMUx0B_x8600_MemAddr_7_0__MASK 0xff00 |
| 8061 | #define SMUx0B_x8600_MemAddr_15_8__OFFSET 16 |
| 8062 | #define SMUx0B_x8600_MemAddr_15_8__WIDTH 8 |
| 8063 | #define SMUx0B_x8600_MemAddr_15_8__MASK 0xff0000 |
| 8064 | #define SMUx0B_x8600_TransactionCount_OFFSET 24 |
| 8065 | #define SMUx0B_x8600_TransactionCount_WIDTH 8 |
| 8066 | #define SMUx0B_x8600_TransactionCount_MASK 0xff000000 |
| 8067 | |
| 8068 | /// SMUx0B_x8600 |
| 8069 | typedef union { |
| 8070 | struct { ///< |
| 8071 | UINT32 Txn1MBusAddr_7_0_:8 ; ///< |
| 8072 | UINT32 MemAddr_7_0_:8 ; ///< |
| 8073 | UINT32 MemAddr_15_8_:8 ; ///< |
| 8074 | UINT32 TransactionCount:8 ; ///< |
| 8075 | } Field; ///< |
| 8076 | UINT32 Value; ///< |
| 8077 | } SMUx0B_x8600_STRUCT; |
| 8078 | |
| 8079 | // **** SMUx0B_x8604 Register Definition **** |
| 8080 | // Address |
| 8081 | #define SMUx0B_x8604_ADDRESS 0x8604 |
| 8082 | |
| 8083 | // Type |
| 8084 | #define SMUx0B_x8604_TYPE TYPE_SMUx0B |
| 8085 | // Field Data |
| 8086 | #define SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET 0 |
| 8087 | #define SMUx0B_x8604_Txn1TransferLength_7_0__WIDTH 8 |
| 8088 | #define SMUx0B_x8604_Txn1TransferLength_7_0__MASK 0xff |
| 8089 | #define SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET 8 |
| 8090 | #define SMUx0B_x8604_Txn1MBusAddr_31_24__WIDTH 8 |
| 8091 | #define SMUx0B_x8604_Txn1MBusAddr_31_24__MASK 0xff00 |
| 8092 | #define SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET 16 |
| 8093 | #define SMUx0B_x8604_Txn1MBusAddr_23_16__WIDTH 8 |
| 8094 | #define SMUx0B_x8604_Txn1MBusAddr_23_16__MASK 0xff0000 |
| 8095 | #define SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET 24 |
| 8096 | #define SMUx0B_x8604_Txn1MBusAddr_15_8__WIDTH 8 |
| 8097 | #define SMUx0B_x8604_Txn1MBusAddr_15_8__MASK 0xff000000 |
| 8098 | |
| 8099 | /// SMUx0B_x8604 |
| 8100 | typedef union { |
| 8101 | struct { ///< |
| 8102 | UINT32 Txn1TransferLength_7_0_:8 ; ///< |
| 8103 | UINT32 Txn1MBusAddr_31_24_:8 ; ///< |
| 8104 | UINT32 Txn1MBusAddr_23_16_:8 ; ///< |
| 8105 | UINT32 Txn1MBusAddr_15_8_:8 ; ///< |
| 8106 | } Field; ///< |
| 8107 | UINT32 Value; ///< |
| 8108 | } SMUx0B_x8604_STRUCT; |
| 8109 | |
| 8110 | // **** SMUx0B_x8608 Register Definition **** |
| 8111 | // Address |
| 8112 | #define SMUx0B_x8608_ADDRESS 0x8608 |
| 8113 | |
| 8114 | // Type |
| 8115 | #define SMUx0B_x8608_TYPE TYPE_SMUx0B |
| 8116 | // Field Data |
| 8117 | #define SMUx0B_x8608_Txn2Mbusaddr158_OFFSET 0 |
| 8118 | #define SMUx0B_x8608_Txn2Mbusaddr158_WIDTH 8 |
| 8119 | #define SMUx0B_x8608_Txn2Mbusaddr158_MASK 0xff |
| 8120 | #define SMUx0B_x8608_Txn2Mbusaddr70_OFFSET 8 |
| 8121 | #define SMUx0B_x8608_Txn2Mbusaddr70_WIDTH 8 |
| 8122 | #define SMUx0B_x8608_Txn2Mbusaddr70_MASK 0xff00 |
| 8123 | #define SMUx0B_x8608_Txn1Mode_OFFSET 16 |
| 8124 | #define SMUx0B_x8608_Txn1Mode_WIDTH 2 |
| 8125 | #define SMUx0B_x8608_Txn1Mode_MASK 0x30000 |
| 8126 | #define SMUx0B_x8608_Txn1Static_OFFSET 18 |
| 8127 | #define SMUx0B_x8608_Txn1Static_WIDTH 1 |
| 8128 | #define SMUx0B_x8608_Txn1Static_MASK 0x40000 |
| 8129 | #define SMUx0B_x8608_Txn1Overlap_OFFSET 19 |
| 8130 | #define SMUx0B_x8608_Txn1Overlap_WIDTH 1 |
| 8131 | #define SMUx0B_x8608_Txn1Overlap_MASK 0x80000 |
| 8132 | #define SMUx0B_x8608_Txn1Spare_OFFSET 20 |
| 8133 | #define SMUx0B_x8608_Txn1Spare_WIDTH 4 |
| 8134 | #define SMUx0B_x8608_Txn1Spare_MASK 0xf00000 |
| 8135 | #define SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET 24 |
| 8136 | #define SMUx0B_x8608_Txn1TransferLength_13_8__WIDTH 6 |
| 8137 | #define SMUx0B_x8608_Txn1TransferLength_13_8__MASK 0x3f000000 |
| 8138 | #define SMUx0B_x8608_Txn1Tsize_OFFSET 30 |
| 8139 | #define SMUx0B_x8608_Txn1Tsize_WIDTH 2 |
| 8140 | #define SMUx0B_x8608_Txn1Tsize_MASK 0xc0000000 |
| 8141 | |
| 8142 | /// SMUx0B_x8608 |
| 8143 | typedef union { |
| 8144 | struct { ///< |
| 8145 | UINT32 Txn2Mbusaddr158:8 ; ///< |
| 8146 | UINT32 Txn2Mbusaddr70:8 ; ///< |
| 8147 | UINT32 Txn1Mode:2 ; ///< |
| 8148 | UINT32 Txn1Static:1 ; ///< |
| 8149 | UINT32 Txn1Overlap:1 ; ///< |
| 8150 | UINT32 Txn1Spare:4 ; ///< |
| 8151 | UINT32 Txn1TransferLength_13_8_:6 ; ///< |
| 8152 | UINT32 Txn1Tsize:2 ; ///< |
| 8153 | } Field; ///< |
| 8154 | UINT32 Value; ///< |
| 8155 | } SMUx0B_x8608_STRUCT; |
| 8156 | |
| 8157 | // **** SMUx0B_x860C Register Definition **** |
| 8158 | // Address |
| 8159 | #define SMUx0B_x860C_ADDRESS 0x860c |
| 8160 | |
| 8161 | // Type |
| 8162 | #define SMUx0B_x860C_TYPE TYPE_SMUx0B |
| 8163 | // Field Data |
| 8164 | #define SMUx0B_x860C_Txn2TransferLength138_OFFSET 0 |
| 8165 | #define SMUx0B_x860C_Txn2TransferLength138_WIDTH 6 |
| 8166 | #define SMUx0B_x860C_Txn2TransferLength138_MASK 0x3f |
| 8167 | #define SMUx0B_x860C_Txn2Tsize_OFFSET 6 |
| 8168 | #define SMUx0B_x860C_Txn2Tsize_WIDTH 2 |
| 8169 | #define SMUx0B_x860C_Txn2Tsize_MASK 0xc0 |
| 8170 | #define SMUx0B_x860C_Txn2TransferLength70_OFFSET 8 |
| 8171 | #define SMUx0B_x860C_Txn2TransferLength70_WIDTH 8 |
| 8172 | #define SMUx0B_x860C_Txn2TransferLength70_MASK 0xff00 |
| 8173 | #define SMUx0B_x860C_Txn2MBusAddr3124_OFFSET 16 |
| 8174 | #define SMUx0B_x860C_Txn2MBusAddr3124_WIDTH 8 |
| 8175 | #define SMUx0B_x860C_Txn2MBusAddr3124_MASK 0xff0000 |
| 8176 | #define SMUx0B_x860C_Txn2MBusAddr2316_OFFSET 24 |
| 8177 | #define SMUx0B_x860C_Txn2MBusAddr2316_WIDTH 8 |
| 8178 | #define SMUx0B_x860C_Txn2MBusAddr2316_MASK 0xff000000 |
| 8179 | |
| 8180 | /// SMUx0B_x860C |
| 8181 | typedef union { |
| 8182 | struct { ///< |
| 8183 | UINT32 Txn2TransferLength138:6 ; ///< |
| 8184 | UINT32 Txn2Tsize:2 ; ///< |
| 8185 | UINT32 Txn2TransferLength70:8 ; ///< |
| 8186 | UINT32 Txn2MBusAddr3124:8 ; ///< |
| 8187 | UINT32 Txn2MBusAddr2316:8 ; ///< |
| 8188 | } Field; ///< |
| 8189 | UINT32 Value; ///< |
| 8190 | } SMUx0B_x860C_STRUCT; |
| 8191 | |
| 8192 | // **** SMUx0B_x8610 Register Definition **** |
| 8193 | // Address |
| 8194 | #define SMUx0B_x8610_ADDRESS 0x8610 |
| 8195 | |
| 8196 | // Type |
| 8197 | #define SMUx0B_x8610_TYPE TYPE_SMUx0B |
| 8198 | // Field Data |
| 8199 | #define SMUx0B_x8610_Txn3MBusAddr2316_OFFSET 0 |
| 8200 | #define SMUx0B_x8610_Txn3MBusAddr2316_WIDTH 8 |
| 8201 | #define SMUx0B_x8610_Txn3MBusAddr2316_MASK 0xff |
| 8202 | #define SMUx0B_x8610_Txn3MBusAddr158_OFFSET 8 |
| 8203 | #define SMUx0B_x8610_Txn3MBusAddr158_WIDTH 8 |
| 8204 | #define SMUx0B_x8610_Txn3MBusAddr158_MASK 0xff00 |
| 8205 | #define SMUx0B_x8610_Txn3MBusAddr70_OFFSET 16 |
| 8206 | #define SMUx0B_x8610_Txn3MBusAddr70_WIDTH 8 |
| 8207 | #define SMUx0B_x8610_Txn3MBusAddr70_MASK 0xff0000 |
| 8208 | #define SMUx0B_x8610_Txn2Mode_OFFSET 24 |
| 8209 | #define SMUx0B_x8610_Txn2Mode_WIDTH 2 |
| 8210 | #define SMUx0B_x8610_Txn2Mode_MASK 0x3000000 |
| 8211 | #define SMUx0B_x8610_Txn2Static_OFFSET 26 |
| 8212 | #define SMUx0B_x8610_Txn2Static_WIDTH 1 |
| 8213 | #define SMUx0B_x8610_Txn2Static_MASK 0x4000000 |
| 8214 | #define SMUx0B_x8610_Txn2Overlap_OFFSET 27 |
| 8215 | #define SMUx0B_x8610_Txn2Overlap_WIDTH 1 |
| 8216 | #define SMUx0B_x8610_Txn2Overlap_MASK 0x8000000 |
| 8217 | #define SMUx0B_x8610_Txn2Spare_OFFSET 28 |
| 8218 | #define SMUx0B_x8610_Txn2Spare_WIDTH 4 |
| 8219 | #define SMUx0B_x8610_Txn2Spare_MASK 0xf0000000 |
| 8220 | |
| 8221 | /// SMUx0B_x8610 |
| 8222 | typedef union { |
| 8223 | struct { ///< |
| 8224 | UINT32 Txn3MBusAddr2316:8 ; ///< |
| 8225 | UINT32 Txn3MBusAddr158:8 ; ///< |
| 8226 | UINT32 Txn3MBusAddr70:8 ; ///< |
| 8227 | UINT32 Txn2Mode:2 ; ///< |
| 8228 | UINT32 Txn2Static:1 ; ///< |
| 8229 | UINT32 Txn2Overlap:1 ; ///< |
| 8230 | UINT32 Txn2Spare:4 ; ///< |
| 8231 | } Field; ///< |
| 8232 | UINT32 Value; ///< |
| 8233 | } SMUx0B_x8610_STRUCT; |
| 8234 | |
| 8235 | // **** SMUx0B_x8614 Register Definition **** |
| 8236 | // Address |
| 8237 | #define SMUx0B_x8614_ADDRESS 0x8614 |
| 8238 | |
| 8239 | // Type |
| 8240 | #define SMUx0B_x8614_TYPE TYPE_SMUx0B |
| 8241 | // Field Data |
| 8242 | #define SMUx0B_x8614_Txn3Mode_OFFSET 0 |
| 8243 | #define SMUx0B_x8614_Txn3Mode_WIDTH 2 |
| 8244 | #define SMUx0B_x8614_Txn3Mode_MASK 0x3 |
| 8245 | #define SMUx0B_x8614_Txn3Static_OFFSET 2 |
| 8246 | #define SMUx0B_x8614_Txn3Static_WIDTH 1 |
| 8247 | #define SMUx0B_x8614_Txn3Static_MASK 0x4 |
| 8248 | #define SMUx0B_x8614_Txn3Overlap_OFFSET 3 |
| 8249 | #define SMUx0B_x8614_Txn3Overlap_WIDTH 1 |
| 8250 | #define SMUx0B_x8614_Txn3Overlap_MASK 0x8 |
| 8251 | #define SMUx0B_x8614_Txn3Spare_OFFSET 4 |
| 8252 | #define SMUx0B_x8614_Txn3Spare_WIDTH 4 |
| 8253 | #define SMUx0B_x8614_Txn3Spare_MASK 0xf0 |
| 8254 | #define SMUx0B_x8614_Txn3TransferLength138_OFFSET 8 |
| 8255 | #define SMUx0B_x8614_Txn3TransferLength138_WIDTH 6 |
| 8256 | #define SMUx0B_x8614_Txn3TransferLength138_MASK 0x3f00 |
| 8257 | #define SMUx0B_x8614_Txn3Tsize_OFFSET 14 |
| 8258 | #define SMUx0B_x8614_Txn3Tsize_WIDTH 2 |
| 8259 | #define SMUx0B_x8614_Txn3Tsize_MASK 0xc000 |
| 8260 | #define SMUx0B_x8614_Txn3TransferLength70_OFFSET 16 |
| 8261 | #define SMUx0B_x8614_Txn3TransferLength70_WIDTH 8 |
| 8262 | #define SMUx0B_x8614_Txn3TransferLength70_MASK 0xff0000 |
| 8263 | #define SMUx0B_x8614_Txn3MBusAddr3124_OFFSET 24 |
| 8264 | #define SMUx0B_x8614_Txn3MBusAddr3124_WIDTH 8 |
| 8265 | #define SMUx0B_x8614_Txn3MBusAddr3124_MASK 0xff000000 |
| 8266 | |
| 8267 | /// SMUx0B_x8614 |
| 8268 | typedef union { |
| 8269 | struct { ///< |
| 8270 | UINT32 Txn3Mode:2 ; ///< |
| 8271 | UINT32 Txn3Static:1 ; ///< |
| 8272 | UINT32 Txn3Overlap:1 ; ///< |
| 8273 | UINT32 Txn3Spare:4 ; ///< |
| 8274 | UINT32 Txn3TransferLength138:6 ; ///< |
| 8275 | UINT32 Txn3Tsize:2 ; ///< |
| 8276 | UINT32 Txn3TransferLength70:8 ; ///< |
| 8277 | UINT32 Txn3MBusAddr3124:8 ; ///< |
| 8278 | } Field; ///< |
| 8279 | UINT32 Value; ///< |
| 8280 | } SMUx0B_x8614_STRUCT; |
| 8281 | |
| 8282 | // **** SMUx0B_x8618 Register Definition **** |
| 8283 | // Address |
| 8284 | #define SMUx0B_x8618_ADDRESS 0x8618 |
| 8285 | |
| 8286 | // Type |
| 8287 | #define SMUx0B_x8618_TYPE TYPE_SMUx0B |
| 8288 | // Field Data |
| 8289 | #define SMUx0B_x8618_Txn4MBusAddr3124_OFFSET 0 |
| 8290 | #define SMUx0B_x8618_Txn4MBusAddr3124_WIDTH 8 |
| 8291 | #define SMUx0B_x8618_Txn4MBusAddr3124_MASK 0xff |
| 8292 | #define SMUx0B_x8618_Txn4MBusAddr2316_OFFSET 8 |
| 8293 | #define SMUx0B_x8618_Txn4MBusAddr2316_WIDTH 8 |
| 8294 | #define SMUx0B_x8618_Txn4MBusAddr2316_MASK 0xff00 |
| 8295 | #define SMUx0B_x8618_Txn4MBusAddr158_OFFSET 16 |
| 8296 | #define SMUx0B_x8618_Txn4MBusAddr158_WIDTH 8 |
| 8297 | #define SMUx0B_x8618_Txn4MBusAddr158_MASK 0xff0000 |
| 8298 | #define SMUx0B_x8618_Txn4MBusAddr70_OFFSET 24 |
| 8299 | #define SMUx0B_x8618_Txn4MBusAddr70_WIDTH 8 |
| 8300 | #define SMUx0B_x8618_Txn4MBusAddr70_MASK 0xff000000 |
| 8301 | |
| 8302 | /// SMUx0B_x8618 |
| 8303 | typedef union { |
| 8304 | struct { ///< |
| 8305 | UINT32 Txn4MBusAddr3124:8 ; ///< |
| 8306 | UINT32 Txn4MBusAddr2316:8 ; ///< |
| 8307 | UINT32 Txn4MBusAddr158:8 ; ///< |
| 8308 | UINT32 Txn4MBusAddr70:8 ; ///< |
| 8309 | } Field; ///< |
| 8310 | UINT32 Value; ///< |
| 8311 | } SMUx0B_x8618_STRUCT; |
| 8312 | |
| 8313 | // **** SMUx0B_x861C Register Definition **** |
| 8314 | // Address |
| 8315 | #define SMUx0B_x861C_ADDRESS 0x861c |
| 8316 | |
| 8317 | // Type |
| 8318 | #define SMUx0B_x861C_TYPE TYPE_SMUx0B |
| 8319 | // Field Data |
| 8320 | #define SMUx0B_x861C_Txn5Mbusaddr70_OFFSET 0 |
| 8321 | #define SMUx0B_x861C_Txn5Mbusaddr70_WIDTH 8 |
| 8322 | #define SMUx0B_x861C_Txn5Mbusaddr70_MASK 0xff |
| 8323 | #define SMUx0B_x861C_Txn4Mode_OFFSET 8 |
| 8324 | #define SMUx0B_x861C_Txn4Mode_WIDTH 2 |
| 8325 | #define SMUx0B_x861C_Txn4Mode_MASK 0x300 |
| 8326 | #define SMUx0B_x861C_Txn4Static_OFFSET 10 |
| 8327 | #define SMUx0B_x861C_Txn4Static_WIDTH 1 |
| 8328 | #define SMUx0B_x861C_Txn4Static_MASK 0x400 |
| 8329 | #define SMUx0B_x861C_Txn4Overlap_OFFSET 11 |
| 8330 | #define SMUx0B_x861C_Txn4Overlap_WIDTH 1 |
| 8331 | #define SMUx0B_x861C_Txn4Overlap_MASK 0x800 |
| 8332 | #define SMUx0B_x861C_Txn4Spare_OFFSET 12 |
| 8333 | #define SMUx0B_x861C_Txn4Spare_WIDTH 4 |
| 8334 | #define SMUx0B_x861C_Txn4Spare_MASK 0xf000 |
| 8335 | #define SMUx0B_x861C_Txn4TransferLength138_OFFSET 16 |
| 8336 | #define SMUx0B_x861C_Txn4TransferLength138_WIDTH 6 |
| 8337 | #define SMUx0B_x861C_Txn4TransferLength138_MASK 0x3f0000 |
| 8338 | #define SMUx0B_x861C_Txn4Tsize_OFFSET 22 |
| 8339 | #define SMUx0B_x861C_Txn4Tsize_WIDTH 2 |
| 8340 | #define SMUx0B_x861C_Txn4Tsize_MASK 0xc00000 |
| 8341 | #define SMUx0B_x861C_Txn4TransferLength70_OFFSET 24 |
| 8342 | #define SMUx0B_x861C_Txn4TransferLength70_WIDTH 8 |
| 8343 | #define SMUx0B_x861C_Txn4TransferLength70_MASK 0xff000000 |
| 8344 | |
| 8345 | /// SMUx0B_x861C |
| 8346 | typedef union { |
| 8347 | struct { ///< |
| 8348 | UINT32 Txn5Mbusaddr70:8 ; ///< |
| 8349 | UINT32 Txn4Mode:2 ; ///< |
| 8350 | UINT32 Txn4Static:1 ; ///< |
| 8351 | UINT32 Txn4Overlap:1 ; ///< |
| 8352 | UINT32 Txn4Spare:4 ; ///< |
| 8353 | UINT32 Txn4TransferLength138:6 ; ///< |
| 8354 | UINT32 Txn4Tsize:2 ; ///< |
| 8355 | UINT32 Txn4TransferLength70:8 ; ///< |
| 8356 | } Field; ///< |
| 8357 | UINT32 Value; ///< |
| 8358 | } SMUx0B_x861C_STRUCT; |
| 8359 | |
| 8360 | // **** SMUx0B_x8620 Register Definition **** |
| 8361 | // Address |
| 8362 | #define SMUx0B_x8620_ADDRESS 0x8620 |
| 8363 | |
| 8364 | // Type |
| 8365 | #define SMUx0B_x8620_TYPE TYPE_SMUx0B |
| 8366 | // Field Data |
| 8367 | #define SMUx0B_x8620_Txn5TransferLength70_OFFSET 0 |
| 8368 | #define SMUx0B_x8620_Txn5TransferLength70_WIDTH 8 |
| 8369 | #define SMUx0B_x8620_Txn5TransferLength70_MASK 0xff |
| 8370 | #define SMUx0B_x8620_Txn5MBusAddr3124_OFFSET 8 |
| 8371 | #define SMUx0B_x8620_Txn5MBusAddr3124_WIDTH 8 |
| 8372 | #define SMUx0B_x8620_Txn5MBusAddr3124_MASK 0xff00 |
| 8373 | #define SMUx0B_x8620_Txn5MBusAddr2316_OFFSET 16 |
| 8374 | #define SMUx0B_x8620_Txn5MBusAddr2316_WIDTH 8 |
| 8375 | #define SMUx0B_x8620_Txn5MBusAddr2316_MASK 0xff0000 |
| 8376 | #define SMUx0B_x8620_Txn5MBusAddr158_OFFSET 24 |
| 8377 | #define SMUx0B_x8620_Txn5MBusAddr158_WIDTH 8 |
| 8378 | #define SMUx0B_x8620_Txn5MBusAddr158_MASK 0xff000000 |
| 8379 | |
| 8380 | /// SMUx0B_x8620 |
| 8381 | typedef union { |
| 8382 | struct { ///< |
| 8383 | UINT32 Txn5TransferLength70:8 ; ///< |
| 8384 | UINT32 Txn5MBusAddr3124:8 ; ///< |
| 8385 | UINT32 Txn5MBusAddr2316:8 ; ///< |
| 8386 | UINT32 Txn5MBusAddr158:8 ; ///< |
| 8387 | } Field; ///< |
| 8388 | UINT32 Value; ///< |
| 8389 | } SMUx0B_x8620_STRUCT; |
| 8390 | |
| 8391 | // **** SMUx0B_x8624 Register Definition **** |
| 8392 | // Address |
| 8393 | #define SMUx0B_x8624_ADDRESS 0x8624 |
| 8394 | |
| 8395 | // Type |
| 8396 | #define SMUx0B_x8624_TYPE TYPE_SMUx0B |
| 8397 | // Field Data |
| 8398 | #define SMUx0B_x8624_Txn6MBusAddr158_OFFSET 0 |
| 8399 | #define SMUx0B_x8624_Txn6MBusAddr158_WIDTH 8 |
| 8400 | #define SMUx0B_x8624_Txn6MBusAddr158_MASK 0xff |
| 8401 | #define SMUx0B_x8624_Txn6MBusAddr70_OFFSET 8 |
| 8402 | #define SMUx0B_x8624_Txn6MBusAddr70_WIDTH 8 |
| 8403 | #define SMUx0B_x8624_Txn6MBusAddr70_MASK 0xff00 |
| 8404 | #define SMUx0B_x8624_Txn5Mode_OFFSET 16 |
| 8405 | #define SMUx0B_x8624_Txn5Mode_WIDTH 2 |
| 8406 | #define SMUx0B_x8624_Txn5Mode_MASK 0x30000 |
| 8407 | #define SMUx0B_x8624_Txn5Static_OFFSET 18 |
| 8408 | #define SMUx0B_x8624_Txn5Static_WIDTH 1 |
| 8409 | #define SMUx0B_x8624_Txn5Static_MASK 0x40000 |
| 8410 | #define SMUx0B_x8624_Txn5Overlap_OFFSET 19 |
| 8411 | #define SMUx0B_x8624_Txn5Overlap_WIDTH 1 |
| 8412 | #define SMUx0B_x8624_Txn5Overlap_MASK 0x80000 |
| 8413 | #define SMUx0B_x8624_Txn5Spare_OFFSET 20 |
| 8414 | #define SMUx0B_x8624_Txn5Spare_WIDTH 4 |
| 8415 | #define SMUx0B_x8624_Txn5Spare_MASK 0xf00000 |
| 8416 | #define SMUx0B_x8624_Txn5TransferLength138_OFFSET 24 |
| 8417 | #define SMUx0B_x8624_Txn5TransferLength138_WIDTH 6 |
| 8418 | #define SMUx0B_x8624_Txn5TransferLength138_MASK 0x3f000000 |
| 8419 | #define SMUx0B_x8624_Txn5Tsize_OFFSET 30 |
| 8420 | #define SMUx0B_x8624_Txn5Tsize_WIDTH 2 |
| 8421 | #define SMUx0B_x8624_Txn5Tsize_MASK 0xc0000000 |
| 8422 | |
| 8423 | /// SMUx0B_x8624 |
| 8424 | typedef union { |
| 8425 | struct { ///< |
| 8426 | UINT32 Txn6MBusAddr158:8 ; ///< |
| 8427 | UINT32 Txn6MBusAddr70:8 ; ///< |
| 8428 | UINT32 Txn5Mode:2 ; ///< |
| 8429 | UINT32 Txn5Static:1 ; ///< |
| 8430 | UINT32 Txn5Overlap:1 ; ///< |
| 8431 | UINT32 Txn5Spare:4 ; ///< |
| 8432 | UINT32 Txn5TransferLength138:6 ; ///< |
| 8433 | UINT32 Txn5Tsize:2 ; ///< |
| 8434 | } Field; ///< |
| 8435 | UINT32 Value; ///< |
| 8436 | } SMUx0B_x8624_STRUCT; |
| 8437 | |
| 8438 | // **** SMUx0B_x8628 Register Definition **** |
| 8439 | // Address |
| 8440 | #define SMUx0B_x8628_ADDRESS 0x8628 |
| 8441 | |
| 8442 | // Type |
| 8443 | #define SMUx0B_x8628_TYPE TYPE_SMUx0B |
| 8444 | // Field Data |
| 8445 | #define SMUx0B_x8628_Txn6TransferLength138_OFFSET 0 |
| 8446 | #define SMUx0B_x8628_Txn6TransferLength138_WIDTH 6 |
| 8447 | #define SMUx0B_x8628_Txn6TransferLength138_MASK 0x3f |
| 8448 | #define SMUx0B_x8628_Txn6Tsize_OFFSET 6 |
| 8449 | #define SMUx0B_x8628_Txn6Tsize_WIDTH 2 |
| 8450 | #define SMUx0B_x8628_Txn6Tsize_MASK 0xc0 |
| 8451 | #define SMUx0B_x8628_Txn6TransferLength70_OFFSET 8 |
| 8452 | #define SMUx0B_x8628_Txn6TransferLength70_WIDTH 8 |
| 8453 | #define SMUx0B_x8628_Txn6TransferLength70_MASK 0xff00 |
| 8454 | #define SMUx0B_x8628_Txn6MBusAddr3124_OFFSET 16 |
| 8455 | #define SMUx0B_x8628_Txn6MBusAddr3124_WIDTH 8 |
| 8456 | #define SMUx0B_x8628_Txn6MBusAddr3124_MASK 0xff0000 |
| 8457 | #define SMUx0B_x8628_Txn6MBusAddr2316_OFFSET 24 |
| 8458 | #define SMUx0B_x8628_Txn6MBusAddr2316_WIDTH 8 |
| 8459 | #define SMUx0B_x8628_Txn6MBusAddr2316_MASK 0xff000000 |
| 8460 | |
| 8461 | /// SMUx0B_x8628 |
| 8462 | typedef union { |
| 8463 | struct { ///< |
| 8464 | UINT32 Txn6TransferLength138:6 ; ///< |
| 8465 | UINT32 Txn6Tsize:2 ; ///< |
| 8466 | UINT32 Txn6TransferLength70:8 ; ///< |
| 8467 | UINT32 Txn6MBusAddr3124:8 ; ///< |
| 8468 | UINT32 Txn6MBusAddr2316:8 ; ///< |
| 8469 | } Field; ///< |
| 8470 | UINT32 Value; ///< |
| 8471 | } SMUx0B_x8628_STRUCT; |
| 8472 | |
| 8473 | // **** SMUx0B_x862C Register Definition **** |
| 8474 | // Address |
| 8475 | #define SMUx0B_x862C_ADDRESS 0x862c |
| 8476 | |
| 8477 | // Type |
| 8478 | #define SMUx0B_x862C_TYPE TYPE_SMUx0B |
| 8479 | // Field Data |
| 8480 | #define SMUx0B_x862C_Txn7MBusAddr2316_OFFSET 0 |
| 8481 | #define SMUx0B_x862C_Txn7MBusAddr2316_WIDTH 8 |
| 8482 | #define SMUx0B_x862C_Txn7MBusAddr2316_MASK 0xff |
| 8483 | #define SMUx0B_x862C_Txn7MBusAddr158_OFFSET 8 |
| 8484 | #define SMUx0B_x862C_Txn7MBusAddr158_WIDTH 8 |
| 8485 | #define SMUx0B_x862C_Txn7MBusAddr158_MASK 0xff00 |
| 8486 | #define SMUx0B_x862C_Txn7MBusAddr70_OFFSET 16 |
| 8487 | #define SMUx0B_x862C_Txn7MBusAddr70_WIDTH 8 |
| 8488 | #define SMUx0B_x862C_Txn7MBusAddr70_MASK 0xff0000 |
| 8489 | #define SMUx0B_x862C_Txn6Mode_OFFSET 24 |
| 8490 | #define SMUx0B_x862C_Txn6Mode_WIDTH 2 |
| 8491 | #define SMUx0B_x862C_Txn6Mode_MASK 0x3000000 |
| 8492 | #define SMUx0B_x862C_Txn6Static_OFFSET 26 |
| 8493 | #define SMUx0B_x862C_Txn6Static_WIDTH 1 |
| 8494 | #define SMUx0B_x862C_Txn6Static_MASK 0x4000000 |
| 8495 | #define SMUx0B_x862C_Txn6Overlap_OFFSET 27 |
| 8496 | #define SMUx0B_x862C_Txn6Overlap_WIDTH 1 |
| 8497 | #define SMUx0B_x862C_Txn6Overlap_MASK 0x8000000 |
| 8498 | #define SMUx0B_x862C_Txn6Spare_OFFSET 28 |
| 8499 | #define SMUx0B_x862C_Txn6Spare_WIDTH 4 |
| 8500 | #define SMUx0B_x862C_Txn6Spare_MASK 0xf0000000 |
| 8501 | |
| 8502 | /// SMUx0B_x862C |
| 8503 | typedef union { |
| 8504 | struct { ///< |
| 8505 | UINT32 Txn7MBusAddr2316:8 ; ///< |
| 8506 | UINT32 Txn7MBusAddr158:8 ; ///< |
| 8507 | UINT32 Txn7MBusAddr70:8 ; ///< |
| 8508 | UINT32 Txn6Mode:2 ; ///< |
| 8509 | UINT32 Txn6Static:1 ; ///< |
| 8510 | UINT32 Txn6Overlap:1 ; ///< |
| 8511 | UINT32 Txn6Spare:4 ; ///< |
| 8512 | } Field; ///< |
| 8513 | UINT32 Value; ///< |
| 8514 | } SMUx0B_x862C_STRUCT; |
| 8515 | |
| 8516 | // **** SMUx0B_x8630 Register Definition **** |
| 8517 | // Address |
| 8518 | #define SMUx0B_x8630_ADDRESS 0x8630 |
| 8519 | |
| 8520 | // Type |
| 8521 | #define SMUx0B_x8630_TYPE TYPE_SMUx0B |
| 8522 | // Field Data |
| 8523 | #define SMUx0B_x8630_Txn7Mode_OFFSET 0 |
| 8524 | #define SMUx0B_x8630_Txn7Mode_WIDTH 2 |
| 8525 | #define SMUx0B_x8630_Txn7Mode_MASK 0x3 |
| 8526 | #define SMUx0B_x8630_Txn7Static_OFFSET 2 |
| 8527 | #define SMUx0B_x8630_Txn7Static_WIDTH 1 |
| 8528 | #define SMUx0B_x8630_Txn7Static_MASK 0x4 |
| 8529 | #define SMUx0B_x8630_Txn7Overlap_OFFSET 3 |
| 8530 | #define SMUx0B_x8630_Txn7Overlap_WIDTH 1 |
| 8531 | #define SMUx0B_x8630_Txn7Overlap_MASK 0x8 |
| 8532 | #define SMUx0B_x8630_Txn7Spare_OFFSET 4 |
| 8533 | #define SMUx0B_x8630_Txn7Spare_WIDTH 4 |
| 8534 | #define SMUx0B_x8630_Txn7Spare_MASK 0xf0 |
| 8535 | #define SMUx0B_x8630_Txn7TransferLength138_OFFSET 8 |
| 8536 | #define SMUx0B_x8630_Txn7TransferLength138_WIDTH 6 |
| 8537 | #define SMUx0B_x8630_Txn7TransferLength138_MASK 0x3f00 |
| 8538 | #define SMUx0B_x8630_Txn7Tsize_OFFSET 14 |
| 8539 | #define SMUx0B_x8630_Txn7Tsize_WIDTH 2 |
| 8540 | #define SMUx0B_x8630_Txn7Tsize_MASK 0xc000 |
| 8541 | #define SMUx0B_x8630_Txn7TransferLength70_OFFSET 16 |
| 8542 | #define SMUx0B_x8630_Txn7TransferLength70_WIDTH 8 |
| 8543 | #define SMUx0B_x8630_Txn7TransferLength70_MASK 0xff0000 |
| 8544 | #define SMUx0B_x8630_Txn7MBusAddr3124_OFFSET 24 |
| 8545 | #define SMUx0B_x8630_Txn7MBusAddr3124_WIDTH 8 |
| 8546 | #define SMUx0B_x8630_Txn7MBusAddr3124_MASK 0xff000000 |
| 8547 | |
| 8548 | /// SMUx0B_x8630 |
| 8549 | typedef union { |
| 8550 | struct { ///< |
| 8551 | UINT32 Txn7Mode:2 ; ///< |
| 8552 | UINT32 Txn7Static:1 ; ///< |
| 8553 | UINT32 Txn7Overlap:1 ; ///< |
| 8554 | UINT32 Txn7Spare:4 ; ///< |
| 8555 | UINT32 Txn7TransferLength138:6 ; ///< |
| 8556 | UINT32 Txn7Tsize:2 ; ///< |
| 8557 | UINT32 Txn7TransferLength70:8 ; ///< |
| 8558 | UINT32 Txn7MBusAddr3124:8 ; ///< |
| 8559 | } Field; ///< |
| 8560 | UINT32 Value; ///< |
| 8561 | } SMUx0B_x8630_STRUCT; |
| 8562 | |
| 8563 | // **** SMUx0B_x8634 Register Definition **** |
| 8564 | // Address |
| 8565 | #define SMUx0B_x8634_ADDRESS 0x8634 |
| 8566 | |
| 8567 | // Type |
| 8568 | #define SMUx0B_x8634_TYPE TYPE_SMUx0B |
| 8569 | // Field Data |
| 8570 | #define SMUx0B_x8634_Txn8MBusAddr3124_OFFSET 0 |
| 8571 | #define SMUx0B_x8634_Txn8MBusAddr3124_WIDTH 8 |
| 8572 | #define SMUx0B_x8634_Txn8MBusAddr3124_MASK 0xff |
| 8573 | #define SMUx0B_x8634_Txn8MBusAddr2316_OFFSET 8 |
| 8574 | #define SMUx0B_x8634_Txn8MBusAddr2316_WIDTH 8 |
| 8575 | #define SMUx0B_x8634_Txn8MBusAddr2316_MASK 0xff00 |
| 8576 | #define SMUx0B_x8634_Txn8MBusAddr158_OFFSET 16 |
| 8577 | #define SMUx0B_x8634_Txn8MBusAddr158_WIDTH 8 |
| 8578 | #define SMUx0B_x8634_Txn8MBusAddr158_MASK 0xff0000 |
| 8579 | #define SMUx0B_x8634_Txn8MBusAddr70_OFFSET 24 |
| 8580 | #define SMUx0B_x8634_Txn8MBusAddr70_WIDTH 8 |
| 8581 | #define SMUx0B_x8634_Txn8MBusAddr70_MASK 0xff000000 |
| 8582 | |
| 8583 | /// SMUx0B_x8634 |
| 8584 | typedef union { |
| 8585 | struct { ///< |
| 8586 | UINT32 Txn8MBusAddr3124:8 ; ///< |
| 8587 | UINT32 Txn8MBusAddr2316:8 ; ///< |
| 8588 | UINT32 Txn8MBusAddr158:8 ; ///< |
| 8589 | UINT32 Txn8MBusAddr70:8 ; ///< |
| 8590 | } Field; ///< |
| 8591 | UINT32 Value; ///< |
| 8592 | } SMUx0B_x8634_STRUCT; |
| 8593 | |
| 8594 | // **** SMUx0B_x8638 Register Definition **** |
| 8595 | // Address |
| 8596 | #define SMUx0B_x8638_ADDRESS 0x8638 |
| 8597 | |
| 8598 | // Type |
| 8599 | #define SMUx0B_x8638_TYPE TYPE_SMUx0B |
| 8600 | // Field Data |
| 8601 | #define SMUx0B_x8638_Txn9MBusAddr70_OFFSET 0 |
| 8602 | #define SMUx0B_x8638_Txn9MBusAddr70_WIDTH 8 |
| 8603 | #define SMUx0B_x8638_Txn9MBusAddr70_MASK 0xff |
| 8604 | #define SMUx0B_x8638_Txn8Mode_OFFSET 8 |
| 8605 | #define SMUx0B_x8638_Txn8Mode_WIDTH 2 |
| 8606 | #define SMUx0B_x8638_Txn8Mode_MASK 0x300 |
| 8607 | #define SMUx0B_x8638_Txn8Static_OFFSET 10 |
| 8608 | #define SMUx0B_x8638_Txn8Static_WIDTH 1 |
| 8609 | #define SMUx0B_x8638_Txn8Static_MASK 0x400 |
| 8610 | #define SMUx0B_x8638_Txn8Overlap_OFFSET 11 |
| 8611 | #define SMUx0B_x8638_Txn8Overlap_WIDTH 1 |
| 8612 | #define SMUx0B_x8638_Txn8Overlap_MASK 0x800 |
| 8613 | #define SMUx0B_x8638_Txn8Spare_OFFSET 12 |
| 8614 | #define SMUx0B_x8638_Txn8Spare_WIDTH 4 |
| 8615 | #define SMUx0B_x8638_Txn8Spare_MASK 0xf000 |
| 8616 | #define SMUx0B_x8638_Txn8TransferLength138_OFFSET 16 |
| 8617 | #define SMUx0B_x8638_Txn8TransferLength138_WIDTH 6 |
| 8618 | #define SMUx0B_x8638_Txn8TransferLength138_MASK 0x3f0000 |
| 8619 | #define SMUx0B_x8638_Txn8Tsize_OFFSET 22 |
| 8620 | #define SMUx0B_x8638_Txn8Tsize_WIDTH 2 |
| 8621 | #define SMUx0B_x8638_Txn8Tsize_MASK 0xc00000 |
| 8622 | #define SMUx0B_x8638_Txn8TransferLength70_OFFSET 24 |
| 8623 | #define SMUx0B_x8638_Txn8TransferLength70_WIDTH 8 |
| 8624 | #define SMUx0B_x8638_Txn8TransferLength70_MASK 0xff000000 |
| 8625 | |
| 8626 | /// SMUx0B_x8638 |
| 8627 | typedef union { |
| 8628 | struct { ///< |
| 8629 | UINT32 Txn9MBusAddr70:8 ; ///< |
| 8630 | UINT32 Txn8Mode:2 ; ///< |
| 8631 | UINT32 Txn8Static:1 ; ///< |
| 8632 | UINT32 Txn8Overlap:1 ; ///< |
| 8633 | UINT32 Txn8Spare:4 ; ///< |
| 8634 | UINT32 Txn8TransferLength138:6 ; ///< |
| 8635 | UINT32 Txn8Tsize:2 ; ///< |
| 8636 | UINT32 Txn8TransferLength70:8 ; ///< |
| 8637 | } Field; ///< |
| 8638 | UINT32 Value; ///< |
| 8639 | } SMUx0B_x8638_STRUCT; |
| 8640 | |
| 8641 | // **** SMUx0B_x863C Register Definition **** |
| 8642 | // Address |
| 8643 | #define SMUx0B_x863C_ADDRESS 0x863c |
| 8644 | |
| 8645 | // Type |
| 8646 | #define SMUx0B_x863C_TYPE TYPE_SMUx0B |
| 8647 | // Field Data |
| 8648 | #define SMUx0B_x863C_Txn9TransferLength70_OFFSET 0 |
| 8649 | #define SMUx0B_x863C_Txn9TransferLength70_WIDTH 8 |
| 8650 | #define SMUx0B_x863C_Txn9TransferLength70_MASK 0xff |
| 8651 | #define SMUx0B_x863C_Txn9MBusAddr3124_OFFSET 8 |
| 8652 | #define SMUx0B_x863C_Txn9MBusAddr3124_WIDTH 8 |
| 8653 | #define SMUx0B_x863C_Txn9MBusAddr3124_MASK 0xff00 |
| 8654 | #define SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET 16 |
| 8655 | #define SMUx0B_x863C_Txn9MBuAaddr2316_WIDTH 8 |
| 8656 | #define SMUx0B_x863C_Txn9MBuAaddr2316_MASK 0xff0000 |
| 8657 | #define SMUx0B_x863C_Txn9MBusAddr158_OFFSET 24 |
| 8658 | #define SMUx0B_x863C_Txn9MBusAddr158_WIDTH 8 |
| 8659 | #define SMUx0B_x863C_Txn9MBusAddr158_MASK 0xff000000 |
| 8660 | |
| 8661 | /// SMUx0B_x863C |
| 8662 | typedef union { |
| 8663 | struct { ///< |
| 8664 | UINT32 Txn9TransferLength70:8 ; ///< |
| 8665 | UINT32 Txn9MBusAddr3124:8 ; ///< |
| 8666 | UINT32 Txn9MBuAaddr2316:8 ; ///< |
| 8667 | UINT32 Txn9MBusAddr158:8 ; ///< |
| 8668 | } Field; ///< |
| 8669 | UINT32 Value; ///< |
| 8670 | } SMUx0B_x863C_STRUCT; |
| 8671 | |
| 8672 | // **** SMUx0B_x8640 Register Definition **** |
| 8673 | // Address |
| 8674 | #define SMUx0B_x8640_ADDRESS 0x8640 |
| 8675 | |
| 8676 | // Type |
| 8677 | #define SMUx0B_x8640_TYPE TYPE_SMUx0B |
| 8678 | // Field Data |
| 8679 | #define SMUx0B_x8640_Txn10MBusAddr158_OFFSET 0 |
| 8680 | #define SMUx0B_x8640_Txn10MBusAddr158_WIDTH 8 |
| 8681 | #define SMUx0B_x8640_Txn10MBusAddr158_MASK 0xff |
| 8682 | #define SMUx0B_x8640_Txn10MBusAddr70_OFFSET 8 |
| 8683 | #define SMUx0B_x8640_Txn10MBusAddr70_WIDTH 8 |
| 8684 | #define SMUx0B_x8640_Txn10MBusAddr70_MASK 0xff00 |
| 8685 | #define SMUx0B_x8640_Txn9Mode_OFFSET 16 |
| 8686 | #define SMUx0B_x8640_Txn9Mode_WIDTH 2 |
| 8687 | #define SMUx0B_x8640_Txn9Mode_MASK 0x30000 |
| 8688 | #define SMUx0B_x8640_Txn9Static_OFFSET 18 |
| 8689 | #define SMUx0B_x8640_Txn9Static_WIDTH 1 |
| 8690 | #define SMUx0B_x8640_Txn9Static_MASK 0x40000 |
| 8691 | #define SMUx0B_x8640_Txn9Overlap_OFFSET 19 |
| 8692 | #define SMUx0B_x8640_Txn9Overlap_WIDTH 1 |
| 8693 | #define SMUx0B_x8640_Txn9Overlap_MASK 0x80000 |
| 8694 | #define SMUx0B_x8640_Txn9Spare_OFFSET 20 |
| 8695 | #define SMUx0B_x8640_Txn9Spare_WIDTH 4 |
| 8696 | #define SMUx0B_x8640_Txn9Spare_MASK 0xf00000 |
| 8697 | #define SMUx0B_x8640_Txn9TransferLength138_OFFSET 24 |
| 8698 | #define SMUx0B_x8640_Txn9TransferLength138_WIDTH 6 |
| 8699 | #define SMUx0B_x8640_Txn9TransferLength138_MASK 0x3f000000 |
| 8700 | #define SMUx0B_x8640_Txn9Tsize_OFFSET 30 |
| 8701 | #define SMUx0B_x8640_Txn9Tsize_WIDTH 2 |
| 8702 | #define SMUx0B_x8640_Txn9Tsize_MASK 0xc0000000 |
| 8703 | |
| 8704 | /// SMUx0B_x8640 |
| 8705 | typedef union { |
| 8706 | struct { ///< |
| 8707 | UINT32 Txn10MBusAddr158:8 ; ///< |
| 8708 | UINT32 Txn10MBusAddr70:8 ; ///< |
| 8709 | UINT32 Txn9Mode:2 ; ///< |
| 8710 | UINT32 Txn9Static:1 ; ///< |
| 8711 | UINT32 Txn9Overlap:1 ; ///< |
| 8712 | UINT32 Txn9Spare:4 ; ///< |
| 8713 | UINT32 Txn9TransferLength138:6 ; ///< |
| 8714 | UINT32 Txn9Tsize:2 ; ///< |
| 8715 | } Field; ///< |
| 8716 | UINT32 Value; ///< |
| 8717 | } SMUx0B_x8640_STRUCT; |
| 8718 | |
| 8719 | // **** SMUx0B_x8650 Register Definition **** |
| 8720 | // Address |
| 8721 | #define SMUx0B_x8650_ADDRESS 0x8650 |
| 8722 | |
| 8723 | // Type |
| 8724 | #define SMUx0B_x8650_TYPE TYPE_SMUx0B |
| 8725 | // Field Data |
| 8726 | #define SMUx0B_x8650_Data_OFFSET 0 |
| 8727 | #define SMUx0B_x8650_Data_WIDTH 32 |
| 8728 | #define SMUx0B_x8650_Data_MASK 0xffffffff |
| 8729 | |
| 8730 | /// SMUx0B_x8650 |
| 8731 | typedef union { |
| 8732 | struct { ///< |
| 8733 | UINT32 Data:32; ///< |
| 8734 | } Field; ///< |
| 8735 | UINT32 Value; ///< |
| 8736 | } SMUx0B_x8650_STRUCT; |
| 8737 | |
| 8738 | // **** SMUx0B_x8654 Register Definition **** |
| 8739 | // Address |
| 8740 | #define SMUx0B_x8654_ADDRESS 0x8654 |
| 8741 | |
| 8742 | // Type |
| 8743 | #define SMUx0B_x8654_TYPE TYPE_SMUx0B |
| 8744 | // Field Data |
| 8745 | #define SMUx0B_x8654_Data_OFFSET 0 |
| 8746 | #define SMUx0B_x8654_Data_WIDTH 32 |
| 8747 | #define SMUx0B_x8654_Data_MASK 0xffffffff |
| 8748 | |
| 8749 | /// SMUx0B_x8654 |
| 8750 | typedef union { |
| 8751 | struct { ///< |
| 8752 | UINT32 Data:32; ///< |
| 8753 | } Field; ///< |
| 8754 | UINT32 Value; ///< |
| 8755 | } SMUx0B_x8654_STRUCT; |
| 8756 | |
| 8757 | // **** SMUx0B_x8658 Register Definition **** |
| 8758 | // Address |
| 8759 | #define SMUx0B_x8658_ADDRESS 0x8658 |
| 8760 | |
| 8761 | // Type |
| 8762 | #define SMUx0B_x8658_TYPE TYPE_SMUx0B |
| 8763 | // Field Data |
| 8764 | #define SMUx0B_x8658_Data_OFFSET 0 |
| 8765 | #define SMUx0B_x8658_Data_WIDTH 32 |
| 8766 | #define SMUx0B_x8658_Data_MASK 0xffffffff |
| 8767 | |
| 8768 | /// SMUx0B_x8658 |
| 8769 | typedef union { |
| 8770 | struct { ///< |
| 8771 | UINT32 Data:32; ///< |
| 8772 | } Field; ///< |
| 8773 | UINT32 Value; ///< |
| 8774 | } SMUx0B_x8658_STRUCT; |
| 8775 | |
| 8776 | // **** SMUx0B_x865C Register Definition **** |
| 8777 | // Address |
| 8778 | #define SMUx0B_x865C_ADDRESS 0x865c |
| 8779 | |
| 8780 | // Type |
| 8781 | #define SMUx0B_x865C_TYPE TYPE_SMUx0B |
| 8782 | // Field Data |
| 8783 | #define SMUx0B_x865C_Data_OFFSET 0 |
| 8784 | #define SMUx0B_x865C_Data_WIDTH 32 |
| 8785 | #define SMUx0B_x865C_Data_MASK 0xffffffff |
| 8786 | |
| 8787 | /// SMUx0B_x865C |
| 8788 | typedef union { |
| 8789 | struct { ///< |
| 8790 | UINT32 Data:32; ///< |
| 8791 | } Field; ///< |
| 8792 | UINT32 Value; ///< |
| 8793 | } SMUx0B_x865C_STRUCT; |
| 8794 | |
| 8795 | // **** SMUx0B_x8660 Register Definition **** |
| 8796 | // Address |
| 8797 | #define SMUx0B_x8660_ADDRESS 0x8660 |
| 8798 | |
| 8799 | // Type |
| 8800 | #define SMUx0B_x8660_TYPE TYPE_SMUx0B |
| 8801 | // Field Data |
| 8802 | #define SMUx0B_x8660_Data_OFFSET 0 |
| 8803 | #define SMUx0B_x8660_Data_WIDTH 32 |
| 8804 | #define SMUx0B_x8660_Data_MASK 0xffffffff |
| 8805 | |
| 8806 | /// SMUx0B_x8660 |
| 8807 | typedef union { |
| 8808 | struct { ///< |
| 8809 | UINT32 Data:32; ///< |
| 8810 | } Field; ///< |
| 8811 | UINT32 Value; ///< |
| 8812 | } SMUx0B_x8660_STRUCT; |
| 8813 | |
| 8814 | // **** SMUx0B_x8664 Register Definition **** |
| 8815 | // Address |
| 8816 | #define SMUx0B_x8664_ADDRESS 0x8664 |
| 8817 | |
| 8818 | // Type |
| 8819 | #define SMUx0B_x8664_TYPE TYPE_SMUx0B |
| 8820 | // Field Data |
| 8821 | #define SMUx0B_x8664_Data_OFFSET 0 |
| 8822 | #define SMUx0B_x8664_Data_WIDTH 32 |
| 8823 | #define SMUx0B_x8664_Data_MASK 0xffffffff |
| 8824 | |
| 8825 | /// SMUx0B_x8664 |
| 8826 | typedef union { |
| 8827 | struct { ///< |
| 8828 | UINT32 Data:32; ///< |
| 8829 | } Field; ///< |
| 8830 | UINT32 Value; ///< |
| 8831 | } SMUx0B_x8664_STRUCT; |
| 8832 | |
| 8833 | // **** SMUx0B_x8668 Register Definition **** |
| 8834 | // Address |
| 8835 | #define SMUx0B_x8668_ADDRESS 0x8668 |
| 8836 | |
| 8837 | // Type |
| 8838 | #define SMUx0B_x8668_TYPE TYPE_SMUx0B |
| 8839 | // Field Data |
| 8840 | #define SMUx0B_x8668_Data_OFFSET 0 |
| 8841 | #define SMUx0B_x8668_Data_WIDTH 32 |
| 8842 | #define SMUx0B_x8668_Data_MASK 0xffffffff |
| 8843 | |
| 8844 | /// SMUx0B_x8668 |
| 8845 | typedef union { |
| 8846 | struct { ///< |
| 8847 | UINT32 Data:32; ///< |
| 8848 | } Field; ///< |
| 8849 | UINT32 Value; ///< |
| 8850 | } SMUx0B_x8668_STRUCT; |
| 8851 | |
| 8852 | // **** SMUx0B_x866C Register Definition **** |
| 8853 | // Address |
| 8854 | #define SMUx0B_x866C_ADDRESS 0x866c |
| 8855 | |
| 8856 | // Type |
| 8857 | #define SMUx0B_x866C_TYPE TYPE_SMUx0B |
| 8858 | // Field Data |
| 8859 | #define SMUx0B_x866C_Data_OFFSET 0 |
| 8860 | #define SMUx0B_x866C_Data_WIDTH 32 |
| 8861 | #define SMUx0B_x866C_Data_MASK 0xffffffff |
| 8862 | |
| 8863 | /// SMUx0B_x866C |
| 8864 | typedef union { |
| 8865 | struct { ///< |
| 8866 | UINT32 Data:32; ///< |
| 8867 | } Field; ///< |
| 8868 | UINT32 Value; ///< |
| 8869 | } SMUx0B_x866C_STRUCT; |
| 8870 | |
| 8871 | // **** SMUx0B_x8670 Register Definition **** |
| 8872 | // Address |
| 8873 | #define SMUx0B_x8670_ADDRESS 0x8670 |
| 8874 | |
| 8875 | // Type |
| 8876 | #define SMUx0B_x8670_TYPE TYPE_SMUx0B |
| 8877 | // Field Data |
| 8878 | #define SMUx0B_x8670_Data_OFFSET 0 |
| 8879 | #define SMUx0B_x8670_Data_WIDTH 32 |
| 8880 | #define SMUx0B_x8670_Data_MASK 0xffffffff |
| 8881 | |
| 8882 | /// SMUx0B_x8670 |
| 8883 | typedef union { |
| 8884 | struct { ///< |
| 8885 | UINT32 Data:32; ///< |
| 8886 | } Field; ///< |
| 8887 | UINT32 Value; ///< |
| 8888 | } SMUx0B_x8670_STRUCT; |
| 8889 | |
| 8890 | // **** SMUx0B_x8674 Register Definition **** |
| 8891 | // Address |
| 8892 | #define SMUx0B_x8674_ADDRESS 0x8674 |
| 8893 | |
| 8894 | // Type |
| 8895 | #define SMUx0B_x8674_TYPE TYPE_SMUx0B |
| 8896 | // Field Data |
| 8897 | #define SMUx0B_x8674_Data_OFFSET 0 |
| 8898 | #define SMUx0B_x8674_Data_WIDTH 32 |
| 8899 | #define SMUx0B_x8674_Data_MASK 0xffffffff |
| 8900 | |
| 8901 | /// SMUx0B_x8674 |
| 8902 | typedef union { |
| 8903 | struct { ///< |
| 8904 | UINT32 Data:32; ///< |
| 8905 | } Field; ///< |
| 8906 | UINT32 Value; ///< |
| 8907 | } SMUx0B_x8674_STRUCT; |
| 8908 | |
| 8909 | // **** SMUx0B_x8678 Register Definition **** |
| 8910 | // Address |
| 8911 | #define SMUx0B_x8678_ADDRESS 0x8678 |
| 8912 | |
| 8913 | // Type |
| 8914 | #define SMUx0B_x8678_TYPE TYPE_SMUx0B |
| 8915 | // Field Data |
| 8916 | #define SMUx0B_x8678_Data_OFFSET 0 |
| 8917 | #define SMUx0B_x8678_Data_WIDTH 32 |
| 8918 | #define SMUx0B_x8678_Data_MASK 0xffffffff |
| 8919 | |
| 8920 | /// SMUx0B_x8678 |
| 8921 | typedef union { |
| 8922 | struct { ///< |
| 8923 | UINT32 Data:32; ///< |
| 8924 | } Field; ///< |
| 8925 | UINT32 Value; ///< |
| 8926 | } SMUx0B_x8678_STRUCT; |
| 8927 | |
| 8928 | // **** SMUx0B_x867C Register Definition **** |
| 8929 | // Address |
| 8930 | #define SMUx0B_x867C_ADDRESS 0x867c |
| 8931 | |
| 8932 | // Type |
| 8933 | #define SMUx0B_x867C_TYPE TYPE_SMUx0B |
| 8934 | // Field Data |
| 8935 | #define SMUx0B_x867C_Data_OFFSET 0 |
| 8936 | #define SMUx0B_x867C_Data_WIDTH 32 |
| 8937 | #define SMUx0B_x867C_Data_MASK 0xffffffff |
| 8938 | |
| 8939 | /// SMUx0B_x867C |
| 8940 | typedef union { |
| 8941 | struct { ///< |
| 8942 | UINT32 Data:32; ///< |
| 8943 | } Field; ///< |
| 8944 | UINT32 Value; ///< |
| 8945 | } SMUx0B_x867C_STRUCT; |
| 8946 | |
| 8947 | // **** SMUx0B_x8680 Register Definition **** |
| 8948 | // Address |
| 8949 | #define SMUx0B_x8680_ADDRESS 0x8680 |
| 8950 | |
| 8951 | // Type |
| 8952 | #define SMUx0B_x8680_TYPE TYPE_SMUx0B |
| 8953 | // Field Data |
| 8954 | #define SMUx0B_x8680_Data_OFFSET 0 |
| 8955 | #define SMUx0B_x8680_Data_WIDTH 32 |
| 8956 | #define SMUx0B_x8680_Data_MASK 0xffffffff |
| 8957 | |
| 8958 | /// SMUx0B_x8680 |
| 8959 | typedef union { |
| 8960 | struct { ///< |
| 8961 | UINT32 Data:32; ///< |
| 8962 | } Field; ///< |
| 8963 | UINT32 Value; ///< |
| 8964 | } SMUx0B_x8680_STRUCT; |
| 8965 | |
| 8966 | // **** SMUx0B_x8684 Register Definition **** |
| 8967 | // Address |
| 8968 | #define SMUx0B_x8684_ADDRESS 0x8684 |
| 8969 | |
| 8970 | // Type |
| 8971 | #define SMUx0B_x8684_TYPE TYPE_SMUx0B |
| 8972 | // Field Data |
| 8973 | #define SMUx0B_x8684_Data_OFFSET 0 |
| 8974 | #define SMUx0B_x8684_Data_WIDTH 32 |
| 8975 | #define SMUx0B_x8684_Data_MASK 0xffffffff |
| 8976 | |
| 8977 | /// SMUx0B_x8684 |
| 8978 | typedef union { |
| 8979 | struct { ///< |
| 8980 | UINT32 Data:32; ///< |
| 8981 | } Field; ///< |
| 8982 | UINT32 Value; ///< |
| 8983 | } SMUx0B_x8684_STRUCT; |
| 8984 | |
| 8985 | // **** SMUx0B_x8688 Register Definition **** |
| 8986 | // Address |
| 8987 | #define SMUx0B_x8688_ADDRESS 0x8688 |
| 8988 | |
| 8989 | // Type |
| 8990 | #define SMUx0B_x8688_TYPE TYPE_SMUx0B |
| 8991 | // Field Data |
| 8992 | #define SMUx0B_x8688_Data_OFFSET 0 |
| 8993 | #define SMUx0B_x8688_Data_WIDTH 32 |
| 8994 | #define SMUx0B_x8688_Data_MASK 0xffffffff |
| 8995 | |
| 8996 | /// SMUx0B_x8688 |
| 8997 | typedef union { |
| 8998 | struct { ///< |
| 8999 | UINT32 Data:32; ///< |
| 9000 | } Field; ///< |
| 9001 | UINT32 Value; ///< |
| 9002 | } SMUx0B_x8688_STRUCT; |
| 9003 | |
| 9004 | // **** SMUx0B_x868C Register Definition **** |
| 9005 | // Address |
| 9006 | #define SMUx0B_x868C_ADDRESS 0x868c |
| 9007 | |
| 9008 | // Type |
| 9009 | #define SMUx0B_x868C_TYPE TYPE_SMUx0B |
| 9010 | // Field Data |
| 9011 | #define SMUx0B_x868C_Data_OFFSET 0 |
| 9012 | #define SMUx0B_x868C_Data_WIDTH 32 |
| 9013 | #define SMUx0B_x868C_Data_MASK 0xffffffff |
| 9014 | |
| 9015 | /// SMUx0B_x868C |
| 9016 | typedef union { |
| 9017 | struct { ///< |
| 9018 | UINT32 Data:32; ///< |
| 9019 | } Field; ///< |
| 9020 | UINT32 Value; ///< |
| 9021 | } SMUx0B_x868C_STRUCT; |
| 9022 | |
| 9023 | // **** SMUx0B_x8690 Register Definition **** |
| 9024 | // Address |
| 9025 | #define SMUx0B_x8690_ADDRESS 0x8690 |
| 9026 | |
| 9027 | // Type |
| 9028 | #define SMUx0B_x8690_TYPE TYPE_SMUx0B |
| 9029 | // Field Data |
| 9030 | #define SMUx0B_x8690_Data_OFFSET 0 |
| 9031 | #define SMUx0B_x8690_Data_WIDTH 32 |
| 9032 | #define SMUx0B_x8690_Data_MASK 0xffffffff |
| 9033 | |
| 9034 | /// SMUx0B_x8690 |
| 9035 | typedef union { |
| 9036 | struct { ///< |
| 9037 | UINT32 Data:32; ///< |
| 9038 | } Field; ///< |
| 9039 | UINT32 Value; ///< |
| 9040 | } SMUx0B_x8690_STRUCT; |
| 9041 | |
| 9042 | // **** SMUx0B_x8694 Register Definition **** |
| 9043 | // Address |
| 9044 | #define SMUx0B_x8694_ADDRESS 0x8694 |
| 9045 | |
| 9046 | // Type |
| 9047 | #define SMUx0B_x8694_TYPE TYPE_SMUx0B |
| 9048 | // Field Data |
| 9049 | #define SMUx0B_x8694_Data_OFFSET 0 |
| 9050 | #define SMUx0B_x8694_Data_WIDTH 32 |
| 9051 | #define SMUx0B_x8694_Data_MASK 0xffffffff |
| 9052 | |
| 9053 | /// SMUx0B_x8694 |
| 9054 | typedef union { |
| 9055 | struct { ///< |
| 9056 | UINT32 Data:32; ///< |
| 9057 | } Field; ///< |
| 9058 | UINT32 Value; ///< |
| 9059 | } SMUx0B_x8694_STRUCT; |
| 9060 | |
| 9061 | // **** SMUx0B_x8698 Register Definition **** |
| 9062 | // Address |
| 9063 | #define SMUx0B_x8698_ADDRESS 0x8698 |
| 9064 | |
| 9065 | // Type |
| 9066 | #define SMUx0B_x8698_TYPE TYPE_SMUx0B |
| 9067 | // Field Data |
| 9068 | #define SMUx0B_x8698_Data_OFFSET 0 |
| 9069 | #define SMUx0B_x8698_Data_WIDTH 32 |
| 9070 | #define SMUx0B_x8698_Data_MASK 0xffffffff |
| 9071 | |
| 9072 | /// SMUx0B_x8698 |
| 9073 | typedef union { |
| 9074 | struct { ///< |
| 9075 | UINT32 Data:32; ///< |
| 9076 | } Field; ///< |
| 9077 | UINT32 Value; ///< |
| 9078 | } SMUx0B_x8698_STRUCT; |
| 9079 | |
| 9080 | // **** SMUx0B_x869C Register Definition **** |
| 9081 | // Address |
| 9082 | #define SMUx0B_x869C_ADDRESS 0x869c |
| 9083 | |
| 9084 | // Type |
| 9085 | #define SMUx0B_x869C_TYPE TYPE_SMUx0B |
| 9086 | // Field Data |
| 9087 | #define SMUx0B_x869C_Data_OFFSET 0 |
| 9088 | #define SMUx0B_x869C_Data_WIDTH 32 |
| 9089 | #define SMUx0B_x869C_Data_MASK 0xffffffff |
| 9090 | |
| 9091 | /// SMUx0B_x869C |
| 9092 | typedef union { |
| 9093 | struct { ///< |
| 9094 | UINT32 Data:32; ///< |
| 9095 | } Field; ///< |
| 9096 | UINT32 Value; ///< |
| 9097 | } SMUx0B_x869C_STRUCT; |
| 9098 | |
| 9099 | // **** SMUx0B_x86A0 Register Definition **** |
| 9100 | // Address |
| 9101 | #define SMUx0B_x86A0_ADDRESS 0x86a0 |
| 9102 | |
| 9103 | // Type |
| 9104 | #define SMUx0B_x86A0_TYPE TYPE_SMUx0B |
| 9105 | // Field Data |
| 9106 | #define SMUx0B_x86A0_Data_OFFSET 0 |
| 9107 | #define SMUx0B_x86A0_Data_WIDTH 32 |
| 9108 | #define SMUx0B_x86A0_Data_MASK 0xffffffff |
| 9109 | |
| 9110 | /// SMUx0B_x86A0 |
| 9111 | typedef union { |
| 9112 | struct { ///< |
| 9113 | UINT32 Data:32; ///< |
| 9114 | } Field; ///< |
| 9115 | UINT32 Value; ///< |
| 9116 | } SMUx0B_x86A0_STRUCT; |
| 9117 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 9118 | // **** SMUx1B Register Definition **** |
| 9119 | // Address |
| 9120 | #define SMUx1B_ADDRESS 0x1b |
| 9121 | |
| 9122 | // Type |
| 9123 | #define SMUx1B_TYPE TYPE_SMU |
| 9124 | // Field Data |
| 9125 | #define SMUx1B_LclkDpSlpDiv_OFFSET 0 |
| 9126 | #define SMUx1B_LclkDpSlpDiv_WIDTH 3 |
| 9127 | #define SMUx1B_LclkDpSlpDiv_MASK 0x7 |
| 9128 | #define SMUx1B_RampDis_OFFSET 3 |
| 9129 | #define SMUx1B_RampDis_WIDTH 1 |
| 9130 | #define SMUx1B_RampDis_MASK 0x8 |
| 9131 | #define SMUx1B_Reserved_7_4_OFFSET 4 |
| 9132 | #define SMUx1B_Reserved_7_4_WIDTH 4 |
| 9133 | #define SMUx1B_Reserved_7_4_MASK 0xf0 |
| 9134 | #define SMUx1B_LclkDpSlpMask_OFFSET 8 |
| 9135 | #define SMUx1B_LclkDpSlpMask_WIDTH 8 |
| 9136 | #define SMUx1B_LclkDpSlpMask_MASK 0xff00 |
| 9137 | |
| 9138 | /// SMUx1B |
| 9139 | typedef union { |
| 9140 | struct { ///< |
| 9141 | UINT32 LclkDpSlpDiv:3 ; ///< |
| 9142 | UINT32 RampDis:1 ; ///< |
| 9143 | UINT32 Reserved_7_4:4 ; ///< |
| 9144 | UINT32 LclkDpSlpMask:8 ; ///< |
| 9145 | } Field; ///< |
| 9146 | UINT32 Value; ///< |
| 9147 | } SMUx1B_STRUCT; |
| 9148 | |
| 9149 | // **** SMUx1D Register Definition **** |
| 9150 | // Address |
| 9151 | #define SMUx1D_ADDRESS 0x1d |
| 9152 | |
| 9153 | // Type |
| 9154 | #define SMUx1D_TYPE TYPE_SMU |
| 9155 | // Field Data |
| 9156 | #define SMUx1D_LclkDpSlpHyst_OFFSET 0 |
| 9157 | #define SMUx1D_LclkDpSlpHyst_WIDTH 12 |
| 9158 | #define SMUx1D_LclkDpSlpHyst_MASK 0xfff |
| 9159 | #define SMUx1D_LclkDpSlpEn_OFFSET 12 |
| 9160 | #define SMUx1D_LclkDpSlpEn_WIDTH 1 |
| 9161 | #define SMUx1D_LclkDpSlpEn_MASK 0x1000 |
| 9162 | #define SMUx1D_Reserved_15_13_OFFSET 13 |
| 9163 | #define SMUx1D_Reserved_15_13_WIDTH 3 |
| 9164 | #define SMUx1D_Reserved_15_13_MASK 0xe000 |
| 9165 | |
| 9166 | /// SMUx1D |
| 9167 | typedef union { |
| 9168 | struct { ///< |
| 9169 | UINT32 LclkDpSlpHyst:12; ///< |
| 9170 | UINT32 LclkDpSlpEn:1 ; ///< |
| 9171 | UINT32 Reserved_15_13:3 ; ///< |
| 9172 | } Field; ///< |
| 9173 | UINT32 Value; ///< |
| 9174 | } SMUx1D_STRUCT; |
| 9175 | |
| 9176 | // **** SMUx6F Register Definition **** |
| 9177 | // Address |
| 9178 | #define SMUx6F_ADDRESS 0x6f |
| 9179 | |
| 9180 | // Type |
| 9181 | #define SMUx6F_TYPE TYPE_SMU |
| 9182 | // Field Data |
| 9183 | #define SMUx6F_OnDelay_OFFSET 0 |
| 9184 | #define SMUx6F_OnDelay_WIDTH 4 |
| 9185 | #define SMUx6F_OnDelay_MASK 0xf |
| 9186 | #define SMUx6F_OffDelay_OFFSET 4 |
| 9187 | #define SMUx6F_OffDelay_WIDTH 8 |
| 9188 | #define SMUx6F_OffDelay_MASK 0xff0 |
| 9189 | #define SMUx6F_Reserved_20_12_OFFSET 12 |
| 9190 | #define SMUx6F_Reserved_20_12_WIDTH 9 |
| 9191 | #define SMUx6F_Reserved_20_12_MASK 0x1ff000 |
| 9192 | #define SMUx6F_RampDis0_OFFSET 21 |
| 9193 | #define SMUx6F_RampDis0_WIDTH 1 |
| 9194 | #define SMUx6F_RampDis0_MASK 0x200000 |
| 9195 | #define SMUx6F_RampDisReg_OFFSET 22 |
| 9196 | #define SMUx6F_RampDisReg_WIDTH 1 |
| 9197 | #define SMUx6F_RampDisReg_MASK 0x400000 |
| 9198 | #define SMUx6F_Reserved_31_23_OFFSET 23 |
| 9199 | #define SMUx6F_Reserved_31_23_WIDTH 9 |
| 9200 | #define SMUx6F_Reserved_31_23_MASK 0xff800000 |
| 9201 | |
| 9202 | /// SMUx6F |
| 9203 | typedef union { |
| 9204 | struct { ///< |
| 9205 | UINT32 OnDelay:4 ; ///< |
| 9206 | UINT32 OffDelay:8 ; ///< |
| 9207 | UINT32 Reserved_20_12:9 ; ///< |
| 9208 | UINT32 RampDis0:1 ; ///< |
| 9209 | UINT32 RampDisReg:1 ; ///< |
| 9210 | UINT32 Reserved_31_23:9 ; ///< |
| 9211 | } Field; ///< |
| 9212 | UINT32 Value; ///< |
| 9213 | } SMUx6F_STRUCT; |
| 9214 | |
| 9215 | // **** SMUx71 Register Definition **** |
| 9216 | // Address |
| 9217 | #define SMUx71_ADDRESS 0x71 |
| 9218 | |
| 9219 | // Type |
| 9220 | #define SMUx71_TYPE TYPE_SMU |
| 9221 | // Field Data |
| 9222 | #define SMUx71_OnDelay_OFFSET 0 |
| 9223 | #define SMUx71_OnDelay_WIDTH 4 |
| 9224 | #define SMUx71_OnDelay_MASK 0xf |
| 9225 | #define SMUx71_OffDelay_OFFSET 4 |
| 9226 | #define SMUx71_OffDelay_WIDTH 8 |
| 9227 | #define SMUx71_OffDelay_MASK 0xff0 |
| 9228 | #define SMUx71_Reserved_19_12_OFFSET 12 |
| 9229 | #define SMUx71_Reserved_19_12_WIDTH 8 |
| 9230 | #define SMUx71_Reserved_19_12_MASK 0xff000 |
| 9231 | #define SMUx71_RampDis1_OFFSET 20 |
| 9232 | #define SMUx71_RampDis1_WIDTH 1 |
| 9233 | #define SMUx71_RampDis1_MASK 0x100000 |
| 9234 | #define SMUx71_RampDis0_OFFSET 21 |
| 9235 | #define SMUx71_RampDis0_WIDTH 1 |
| 9236 | #define SMUx71_RampDis0_MASK 0x200000 |
| 9237 | #define SMUx71_RampDisReg_OFFSET 22 |
| 9238 | #define SMUx71_RampDisReg_WIDTH 1 |
| 9239 | #define SMUx71_RampDisReg_MASK 0x400000 |
| 9240 | #define SMUx71_Reserved_31_23_OFFSET 23 |
| 9241 | #define SMUx71_Reserved_31_23_WIDTH 9 |
| 9242 | #define SMUx71_Reserved_31_23_MASK 0xff800000 |
| 9243 | |
| 9244 | /// SMUx71 |
| 9245 | typedef union { |
| 9246 | struct { ///< |
| 9247 | UINT32 OnDelay:4 ; ///< |
| 9248 | UINT32 OffDelay:8 ; ///< |
| 9249 | UINT32 Reserved_19_12:8 ; ///< |
| 9250 | UINT32 RampDis1:1 ; ///< |
| 9251 | UINT32 RampDis0:1 ; ///< |
| 9252 | UINT32 RampDisReg:1 ; ///< |
| 9253 | UINT32 Reserved_31_23:9 ; ///< |
| 9254 | } Field; ///< |
| 9255 | UINT32 Value; ///< |
| 9256 | } SMUx71_STRUCT; |
| 9257 | |
| 9258 | // **** SMUx73 Register Definition **** |
| 9259 | // Address |
| 9260 | #define SMUx73_ADDRESS 0x73 |
| 9261 | |
| 9262 | // Type |
| 9263 | #define SMUx73_TYPE TYPE_SMU |
| 9264 | // Field Data |
| 9265 | #define SMUx73_DisLclkGating_OFFSET 0 |
| 9266 | #define SMUx73_DisLclkGating_WIDTH 1 |
| 9267 | #define SMUx73_DisLclkGating_MASK 0x1 |
| 9268 | #define SMUx73_DisSclkGating_OFFSET 1 |
| 9269 | #define SMUx73_DisSclkGating_WIDTH 1 |
| 9270 | #define SMUx73_DisSclkGating_MASK 0x2 |
| 9271 | #define SMUx73_Reserved_15_2_OFFSET 2 |
| 9272 | #define SMUx73_Reserved_15_2_WIDTH 14 |
| 9273 | #define SMUx73_Reserved_15_2_MASK 0xfffc |
| 9274 | |
| 9275 | /// SMUx73 |
| 9276 | typedef union { |
| 9277 | struct { ///< |
| 9278 | UINT32 DisLclkGating:1 ; ///< |
| 9279 | UINT32 DisSclkGating:1 ; ///< |
| 9280 | UINT32 Reserved_15_2:14; ///< |
| 9281 | } Field; ///< |
| 9282 | UINT32 Value; ///< |
| 9283 | } SMUx73_STRUCT; |
| 9284 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 9285 | // **** GMMx00 Register Definition **** |
| 9286 | // Address |
| 9287 | #define GMMx00_ADDRESS 0x0 |
| 9288 | |
| 9289 | // Type |
| 9290 | #define GMMx00_TYPE TYPE_GMM |
| 9291 | // Field Data |
| 9292 | #define GMMx00_Offset_OFFSET 0 |
| 9293 | #define GMMx00_Offset_WIDTH 31 |
| 9294 | #define GMMx00_Offset_MASK 0x7fffffff |
| 9295 | #define GMMx00_Aper_OFFSET 31 |
| 9296 | #define GMMx00_Aper_WIDTH 1 |
| 9297 | #define GMMx00_Aper_MASK 0x80000000 |
| 9298 | |
| 9299 | /// GMMx00 |
| 9300 | typedef union { |
| 9301 | struct { ///< |
| 9302 | UINT32 Offset:31; ///< |
| 9303 | UINT32 Aper:1 ; ///< |
| 9304 | } Field; ///< |
| 9305 | UINT32 Value; ///< |
| 9306 | } GMMx00_STRUCT; |
| 9307 | |
| 9308 | // **** GMMx04 Register Definition **** |
| 9309 | // Address |
| 9310 | #define GMMx04_ADDRESS 0x4 |
| 9311 | |
| 9312 | // Type |
| 9313 | #define GMMx04_TYPE TYPE_GMM |
| 9314 | // Field Data |
| 9315 | #define GMMx04_Data_OFFSET 0 |
| 9316 | #define GMMx04_Data_WIDTH 32 |
| 9317 | #define GMMx04_Data_MASK 0xffffffff |
| 9318 | |
| 9319 | /// GMMx04 |
| 9320 | typedef union { |
| 9321 | struct { ///< |
| 9322 | UINT32 Data:32; ///< |
| 9323 | } Field; ///< |
| 9324 | UINT32 Value; ///< |
| 9325 | } GMMx04_STRUCT; |
| 9326 | |
| 9327 | // **** GMMx770 Register Definition **** |
| 9328 | // Address |
| 9329 | #define GMMx770_ADDRESS 0x770 |
| 9330 | |
| 9331 | // Type |
| 9332 | #define GMMx770_TYPE TYPE_GMM |
| 9333 | // Field Data |
| 9334 | #define GMMx770_VoltageChangeReq_OFFSET 0 |
| 9335 | #define GMMx770_VoltageChangeReq_WIDTH 1 |
| 9336 | #define GMMx770_VoltageChangeReq_MASK 0x1 |
| 9337 | #define GMMx770_VoltageLevel_OFFSET 1 |
| 9338 | #define GMMx770_VoltageLevel_WIDTH 2 |
| 9339 | #define GMMx770_VoltageLevel_MASK 0x6 |
| 9340 | #define GMMx770_VoltageChangeEn_OFFSET 3 |
| 9341 | #define GMMx770_VoltageChangeEn_WIDTH 1 |
| 9342 | #define GMMx770_VoltageChangeEn_MASK 0x8 |
| 9343 | #define GMMx770_VoltageForceEn_OFFSET 4 |
| 9344 | #define GMMx770_VoltageForceEn_WIDTH 1 |
| 9345 | #define GMMx770_VoltageForceEn_MASK 0x10 |
| 9346 | #define GMMx770_Reserved_31_5_OFFSET 5 |
| 9347 | #define GMMx770_Reserved_31_5_WIDTH 27 |
| 9348 | #define GMMx770_Reserved_31_5_MASK 0xffffffe0 |
| 9349 | |
| 9350 | /// GMMx770 |
| 9351 | typedef union { |
| 9352 | struct { ///< |
| 9353 | UINT32 VoltageChangeReq:1 ; ///< |
| 9354 | UINT32 VoltageLevel:2 ; ///< |
| 9355 | UINT32 VoltageChangeEn:1 ; ///< |
| 9356 | UINT32 VoltageForceEn:1 ; ///< |
| 9357 | UINT32 Reserved_31_5:27; ///< |
| 9358 | } Field; ///< |
| 9359 | UINT32 Value; ///< |
| 9360 | } GMMx770_STRUCT; |
| 9361 | |
| 9362 | // **** GMMx774 Register Definition **** |
| 9363 | // Address |
| 9364 | #define GMMx774_ADDRESS 0x774 |
| 9365 | |
| 9366 | // Type |
| 9367 | #define GMMx774_TYPE TYPE_GMM |
| 9368 | // Field Data |
| 9369 | #define GMMx774_VoltageChangeAck_OFFSET 0 |
| 9370 | #define GMMx774_VoltageChangeAck_WIDTH 1 |
| 9371 | #define GMMx774_VoltageChangeAck_MASK 0x1 |
| 9372 | #define GMMx774_CurrentVoltageLevel_OFFSET 1 |
| 9373 | #define GMMx774_CurrentVoltageLevel_WIDTH 2 |
| 9374 | #define GMMx774_CurrentVoltageLevel_MASK 0x6 |
| 9375 | #define GMMx774_Reserved_31_3_OFFSET 3 |
| 9376 | #define GMMx774_Reserved_31_3_WIDTH 29 |
| 9377 | #define GMMx774_Reserved_31_3_MASK 0xfffffff8 |
| 9378 | |
| 9379 | /// GMMx774 |
| 9380 | typedef union { |
| 9381 | struct { ///< |
| 9382 | UINT32 VoltageChangeAck:1 ; ///< |
| 9383 | UINT32 CurrentVoltageLevel:2 ; ///< |
| 9384 | UINT32 Reserved_31_3:29; ///< |
| 9385 | } Field; ///< |
| 9386 | UINT32 Value; ///< |
| 9387 | } GMMx774_STRUCT; |
| 9388 | |
| 9389 | // **** GMMx15C0 Register Definition **** |
| 9390 | // Address |
| 9391 | #define GMMx15C0_ADDRESS 0x15c0 |
| 9392 | |
| 9393 | // Type |
| 9394 | #define GMMx15C0_TYPE TYPE_GMM |
| 9395 | // Field Data |
| 9396 | #define GMMx15C0_Reserved_17_0_OFFSET 0 |
| 9397 | #define GMMx15C0_Reserved_17_0_WIDTH 18 |
| 9398 | #define GMMx15C0_Reserved_17_0_MASK 0x3ffff |
| 9399 | #define GMMx15C0_Enable_OFFSET 18 |
| 9400 | #define GMMx15C0_Enable_WIDTH 1 |
| 9401 | #define GMMx15C0_Enable_MASK 0x40000 |
| 9402 | #define GMMx15C0_Reserved_31_19_OFFSET 19 |
| 9403 | #define GMMx15C0_Reserved_31_19_WIDTH 13 |
| 9404 | #define GMMx15C0_Reserved_31_19_MASK 0xfff80000 |
| 9405 | |
| 9406 | /// GMMx15C0 |
| 9407 | typedef union { |
| 9408 | struct { ///< |
| 9409 | UINT32 Reserved_17_0:18; ///< |
| 9410 | UINT32 Enable:1 ; ///< |
| 9411 | UINT32 Reserved_31_19:13; ///< |
| 9412 | } Field; ///< |
| 9413 | UINT32 Value; ///< |
| 9414 | } GMMx15C0_STRUCT; |
| 9415 | |
| 9416 | // **** GMMx2014 Register Definition **** |
| 9417 | // Address |
| 9418 | #define GMMx2014_ADDRESS 0x2014 |
| 9419 | |
| 9420 | // Type |
| 9421 | #define GMMx2014_TYPE TYPE_GMM |
| 9422 | // Field Data |
| 9423 | #define GMMx2014_Rlc_OFFSET 0 |
| 9424 | #define GMMx2014_Rlc_WIDTH 4 |
| 9425 | #define GMMx2014_Rlc_MASK 0xf |
| 9426 | #define GMMx2014_Vmc_OFFSET 4 |
| 9427 | #define GMMx2014_Vmc_WIDTH 4 |
| 9428 | #define GMMx2014_Vmc_MASK 0xf0 |
| 9429 | #define GMMx2014_Dmif_OFFSET 8 |
| 9430 | #define GMMx2014_Dmif_WIDTH 4 |
| 9431 | #define GMMx2014_Dmif_MASK 0xf00 |
| 9432 | #define GMMx2014_Mcif_OFFSET 12 |
| 9433 | #define GMMx2014_Mcif_WIDTH 4 |
| 9434 | #define GMMx2014_Mcif_MASK 0xf000 |
| 9435 | #define GMMx2014_Reserved_31_16_OFFSET 16 |
| 9436 | #define GMMx2014_Reserved_31_16_WIDTH 16 |
| 9437 | #define GMMx2014_Reserved_31_16_MASK 0xffff0000 |
| 9438 | |
| 9439 | /// GMMx2014 |
| 9440 | typedef union { |
| 9441 | struct { ///< |
| 9442 | UINT32 Rlc:4 ; ///< |
| 9443 | UINT32 Vmc:4 ; ///< |
| 9444 | UINT32 Dmif:4 ; ///< |
| 9445 | UINT32 Mcif:4 ; ///< |
| 9446 | UINT32 Reserved_31_16:16; ///< |
| 9447 | } Field; ///< |
| 9448 | UINT32 Value; ///< |
| 9449 | } GMMx2014_STRUCT; |
| 9450 | |
| 9451 | // **** GMMx2018 Register Definition **** |
| 9452 | // Address |
| 9453 | #define GMMx2018_ADDRESS 0x2018 |
| 9454 | |
| 9455 | // Type |
| 9456 | #define GMMx2018_TYPE TYPE_GMM |
| 9457 | // Field Data |
| 9458 | #define GMMx2018_Ih_OFFSET 0 |
| 9459 | #define GMMx2018_Ih_WIDTH 4 |
| 9460 | #define GMMx2018_Ih_MASK 0xf |
| 9461 | #define GMMx2018_Mcif_OFFSET 4 |
| 9462 | #define GMMx2018_Mcif_WIDTH 4 |
| 9463 | #define GMMx2018_Mcif_MASK 0xf0 |
| 9464 | #define GMMx2018_Rlc_OFFSET 8 |
| 9465 | #define GMMx2018_Rlc_WIDTH 4 |
| 9466 | #define GMMx2018_Rlc_MASK 0xf00 |
| 9467 | #define GMMx2018_Vip_OFFSET 12 |
| 9468 | #define GMMx2018_Vip_WIDTH 4 |
| 9469 | #define GMMx2018_Vip_MASK 0xf000 |
| 9470 | #define GMMx2018_Reserved_31_16_OFFSET 16 |
| 9471 | #define GMMx2018_Reserved_31_16_WIDTH 16 |
| 9472 | #define GMMx2018_Reserved_31_16_MASK 0xffff0000 |
| 9473 | |
| 9474 | /// GMMx2018 |
| 9475 | typedef union { |
| 9476 | struct { ///< |
| 9477 | UINT32 Ih:4 ; ///< |
| 9478 | UINT32 Mcif:4 ; ///< |
| 9479 | UINT32 Rlc:4 ; ///< |
| 9480 | UINT32 Vip:4 ; ///< |
| 9481 | UINT32 Reserved_31_16:16; ///< |
| 9482 | } Field; ///< |
| 9483 | UINT32 Value; ///< |
| 9484 | } GMMx2018_STRUCT; |
| 9485 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 9486 | // **** GMMx201C Register Definition **** |
| 9487 | // Address |
| 9488 | #define GMMx201C_ADDRESS 0x201c |
| 9489 | |
| 9490 | // Type |
| 9491 | #define GMMx201C_TYPE TYPE_GMM |
| 9492 | // Field Data |
| 9493 | #define GMMx201C_UvdExt0_OFFSET 0 |
| 9494 | #define GMMx201C_UvdExt0_WIDTH 4 |
| 9495 | #define GMMx201C_UvdExt0_MASK 0xf |
| 9496 | #define GMMx201C_DrmDma_OFFSET 4 |
| 9497 | #define GMMx201C_DrmDma_WIDTH 4 |
| 9498 | #define GMMx201C_DrmDma_MASK 0xf0 |
| 9499 | #define GMMx201C_Hdp_OFFSET 8 |
| 9500 | #define GMMx201C_Hdp_WIDTH 4 |
| 9501 | #define GMMx201C_Hdp_MASK 0xf00 |
| 9502 | #define GMMx201C_Sem_OFFSET 12 |
| 9503 | #define GMMx201C_Sem_WIDTH 4 |
| 9504 | #define GMMx201C_Sem_MASK 0xf000 |
| 9505 | #define GMMx201C_Umc_OFFSET 16 |
| 9506 | #define GMMx201C_Umc_WIDTH 4 |
| 9507 | #define GMMx201C_Umc_MASK 0xf0000 |
| 9508 | #define GMMx201C_Uvd_OFFSET 20 |
| 9509 | #define GMMx201C_Uvd_WIDTH 4 |
| 9510 | #define GMMx201C_Uvd_MASK 0xf00000 |
| 9511 | #define GMMx201C_UvdExt1_OFFSET 24 |
| 9512 | #define GMMx201C_UvdExt1_WIDTH 4 |
| 9513 | #define GMMx201C_UvdExt1_MASK 0xf000000 |
| 9514 | #define GMMx201C_Reserved_31_28_OFFSET 28 |
| 9515 | #define GMMx201C_Reserved_31_28_WIDTH 4 |
| 9516 | #define GMMx201C_Reserved_31_28_MASK 0xf0000000 |
| 9517 | |
| 9518 | /// GMMx201C |
| 9519 | typedef union { |
| 9520 | struct { ///< |
| 9521 | UINT32 UvdExt0:4 ; ///< |
| 9522 | UINT32 DrmDma:4 ; ///< |
| 9523 | UINT32 Hdp:4 ; ///< |
| 9524 | UINT32 Sem:4 ; ///< |
| 9525 | UINT32 Umc:4 ; ///< |
| 9526 | UINT32 Uvd:4 ; ///< |
| 9527 | UINT32 UvdExt1:4 ; ///< |
| 9528 | UINT32 Reserved_31_28:4 ; ///< |
| 9529 | } Field; ///< |
| 9530 | UINT32 Value; ///< |
| 9531 | } GMMx201C_STRUCT; |
| 9532 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 9533 | // **** GMMx2020 Register Definition **** |
| 9534 | // Address |
| 9535 | #define GMMx2020_ADDRESS 0x2020 |
| 9536 | |
| 9537 | // Type |
| 9538 | #define GMMx2020_TYPE TYPE_GMM |
| 9539 | // Field Data |
| 9540 | #define GMMx2020_UvdExt0_OFFSET 0 |
| 9541 | #define GMMx2020_UvdExt0_WIDTH 4 |
| 9542 | #define GMMx2020_UvdExt0_MASK 0xf |
| 9543 | #define GMMx2020_DrmDma_OFFSET 4 |
| 9544 | #define GMMx2020_DrmDma_WIDTH 4 |
| 9545 | #define GMMx2020_DrmDma_MASK 0xf0 |
| 9546 | #define GMMx2020_Hdp_OFFSET 8 |
| 9547 | #define GMMx2020_Hdp_WIDTH 4 |
| 9548 | #define GMMx2020_Hdp_MASK 0xf00 |
| 9549 | #define GMMx2020_Sem_OFFSET 12 |
| 9550 | #define GMMx2020_Sem_WIDTH 4 |
| 9551 | #define GMMx2020_Sem_MASK 0xf000 |
| 9552 | #define GMMx2020_Umc_OFFSET 16 |
| 9553 | #define GMMx2020_Umc_WIDTH 4 |
| 9554 | #define GMMx2020_Umc_MASK 0xf0000 |
| 9555 | #define GMMx2020_Uvd_OFFSET 20 |
| 9556 | #define GMMx2020_Uvd_WIDTH 4 |
| 9557 | #define GMMx2020_Uvd_MASK 0xf00000 |
| 9558 | #define GMMx2020_Xdp_OFFSET 24 |
| 9559 | #define GMMx2020_Xdp_WIDTH 4 |
| 9560 | #define GMMx2020_Xdp_MASK 0xf000000 |
| 9561 | #define GMMx2020_UvdExt1_OFFSET 28 |
| 9562 | #define GMMx2020_UvdExt1_WIDTH 4 |
| 9563 | #define GMMx2020_UvdExt1_MASK 0xf0000000 |
| 9564 | |
| 9565 | /// GMMx2020 |
| 9566 | typedef union { |
| 9567 | struct { ///< |
| 9568 | UINT32 UvdExt0:4 ; ///< |
| 9569 | UINT32 DrmDma:4 ; ///< |
| 9570 | UINT32 Hdp:4 ; ///< |
| 9571 | UINT32 Sem:4 ; ///< |
| 9572 | UINT32 Umc:4 ; ///< |
| 9573 | UINT32 Uvd:4 ; ///< |
| 9574 | UINT32 Xdp:4 ; ///< |
| 9575 | UINT32 UvdExt1:4 ; ///< |
| 9576 | } Field; ///< |
| 9577 | UINT32 Value; ///< |
| 9578 | } GMMx2020_STRUCT; |
| 9579 | |
| 9580 | // **** GMMx2024 Register Definition **** |
| 9581 | // Address |
| 9582 | #define GMMx2024_ADDRESS 0x2024 |
| 9583 | |
| 9584 | // Type |
| 9585 | #define GMMx2024_TYPE TYPE_GMM |
| 9586 | // Field Data |
| 9587 | #define GMMx2024_Base_OFFSET 0 |
| 9588 | #define GMMx2024_Base_WIDTH 16 |
| 9589 | #define GMMx2024_Base_MASK 0xffff |
| 9590 | #define GMMx2024_Top_OFFSET 16 |
| 9591 | #define GMMx2024_Top_WIDTH 16 |
| 9592 | #define GMMx2024_Top_MASK 0xffff0000 |
| 9593 | |
| 9594 | /// GMMx2024 |
| 9595 | typedef union { |
| 9596 | struct { ///< |
| 9597 | UINT32 Base:16; ///< |
| 9598 | UINT32 Top:16; ///< |
| 9599 | } Field; ///< |
| 9600 | UINT32 Value; ///< |
| 9601 | } GMMx2024_STRUCT; |
| 9602 | |
| 9603 | // **** GMMx2028 Register Definition **** |
| 9604 | // Address |
| 9605 | #define GMMx2028_ADDRESS 0x2028 |
| 9606 | |
| 9607 | // Type |
| 9608 | #define GMMx2028_TYPE TYPE_GMM |
| 9609 | // Field Data |
| 9610 | #define GMMx2028_SysTop_39_22__OFFSET 0 |
| 9611 | #define GMMx2028_SysTop_39_22__WIDTH 18 |
| 9612 | #define GMMx2028_SysTop_39_22__MASK 0x3ffff |
| 9613 | #define GMMx2028_Reserved_31_18_OFFSET 18 |
| 9614 | #define GMMx2028_Reserved_31_18_WIDTH 14 |
| 9615 | #define GMMx2028_Reserved_31_18_MASK 0xfffc0000 |
| 9616 | |
| 9617 | /// GMMx2028 |
| 9618 | typedef union { |
| 9619 | struct { ///< |
| 9620 | UINT32 SysTop_39_22_:18; ///< |
| 9621 | UINT32 Reserved_31_18:14; ///< |
| 9622 | } Field; ///< |
| 9623 | UINT32 Value; ///< |
| 9624 | } GMMx2028_STRUCT; |
| 9625 | |
| 9626 | // **** GMMx202C Register Definition **** |
| 9627 | // Address |
| 9628 | #define GMMx202C_ADDRESS 0x202c |
| 9629 | |
| 9630 | // Type |
| 9631 | #define GMMx202C_TYPE TYPE_GMM |
| 9632 | // Field Data |
| 9633 | #define GMMx202C_SysBot_39_22__OFFSET 0 |
| 9634 | #define GMMx202C_SysBot_39_22__WIDTH 18 |
| 9635 | #define GMMx202C_SysBot_39_22__MASK 0x3ffff |
| 9636 | #define GMMx202C_Reserved_31_18_OFFSET 18 |
| 9637 | #define GMMx202C_Reserved_31_18_WIDTH 14 |
| 9638 | #define GMMx202C_Reserved_31_18_MASK 0xfffc0000 |
| 9639 | |
| 9640 | /// GMMx202C |
| 9641 | typedef union { |
| 9642 | struct { ///< |
| 9643 | UINT32 SysBot_39_22_:18; ///< |
| 9644 | UINT32 Reserved_31_18:14; ///< |
| 9645 | } Field; ///< |
| 9646 | UINT32 Value; ///< |
| 9647 | } GMMx202C_STRUCT; |
| 9648 | |
| 9649 | // **** GMMx20B4 Register Definition **** |
| 9650 | // Address |
| 9651 | #define GMMx20B4_ADDRESS 0x20b4 |
| 9652 | |
| 9653 | // Type |
| 9654 | #define GMMx20B4_TYPE TYPE_GMM |
| 9655 | // Field Data |
| 9656 | #define GMMx20B4_StutterMode_OFFSET 0 |
| 9657 | #define GMMx20B4_StutterMode_WIDTH 2 |
| 9658 | #define GMMx20B4_StutterMode_MASK 0x3 |
| 9659 | #define GMMx20B4_GateOverride_OFFSET 2 |
| 9660 | #define GMMx20B4_GateOverride_WIDTH 1 |
| 9661 | #define GMMx20B4_GateOverride_MASK 0x4 |
| 9662 | #define GMMx20B4_Reserved_31_3_OFFSET 3 |
| 9663 | #define GMMx20B4_Reserved_31_3_WIDTH 29 |
| 9664 | #define GMMx20B4_Reserved_31_3_MASK 0xfffffff8 |
| 9665 | |
| 9666 | /// GMMx20B4 |
| 9667 | typedef union { |
| 9668 | struct { ///< |
| 9669 | UINT32 StutterMode:2 ; ///< |
| 9670 | UINT32 GateOverride:1 ; ///< |
| 9671 | UINT32 Reserved_31_3:29; ///< |
| 9672 | } Field; ///< |
| 9673 | UINT32 Value; ///< |
| 9674 | } GMMx20B4_STRUCT; |
| 9675 | |
| 9676 | // **** GMMx20B8 Register Definition **** |
| 9677 | // Address |
| 9678 | #define GMMx20B8_ADDRESS 0x20b8 |
| 9679 | |
| 9680 | // Type |
| 9681 | #define GMMx20B8_TYPE TYPE_GMM |
| 9682 | // Field Data |
| 9683 | #define GMMx20B8_Reserved_17_0_OFFSET 0 |
| 9684 | #define GMMx20B8_Reserved_17_0_WIDTH 18 |
| 9685 | #define GMMx20B8_Reserved_17_0_MASK 0x3ffff |
| 9686 | #define GMMx20B8_Enable_OFFSET 18 |
| 9687 | #define GMMx20B8_Enable_WIDTH 1 |
| 9688 | #define GMMx20B8_Enable_MASK 0x40000 |
| 9689 | #define GMMx20B8_Reserved_31_19_OFFSET 19 |
| 9690 | #define GMMx20B8_Reserved_31_19_WIDTH 13 |
| 9691 | #define GMMx20B8_Reserved_31_19_MASK 0xfff80000 |
| 9692 | |
| 9693 | /// GMMx20B8 |
| 9694 | typedef union { |
| 9695 | struct { ///< |
| 9696 | UINT32 Reserved_17_0:18; ///< |
| 9697 | UINT32 Enable:1 ; ///< |
| 9698 | UINT32 Reserved_31_19:13; ///< |
| 9699 | } Field; ///< |
| 9700 | UINT32 Value; ///< |
| 9701 | } GMMx20B8_STRUCT; |
| 9702 | |
| 9703 | // **** GMMx20BC Register Definition **** |
| 9704 | // Address |
| 9705 | #define GMMx20BC_ADDRESS 0x20bc |
| 9706 | |
| 9707 | // Type |
| 9708 | #define GMMx20BC_TYPE TYPE_GMM |
| 9709 | // Field Data |
| 9710 | #define GMMx20BC_Reserved_17_0_OFFSET 0 |
| 9711 | #define GMMx20BC_Reserved_17_0_WIDTH 18 |
| 9712 | #define GMMx20BC_Reserved_17_0_MASK 0x3ffff |
| 9713 | #define GMMx20BC_Enable_OFFSET 18 |
| 9714 | #define GMMx20BC_Enable_WIDTH 1 |
| 9715 | #define GMMx20BC_Enable_MASK 0x40000 |
| 9716 | #define GMMx20BC_Reserved_31_19_OFFSET 19 |
| 9717 | #define GMMx20BC_Reserved_31_19_WIDTH 13 |
| 9718 | #define GMMx20BC_Reserved_31_19_MASK 0xfff80000 |
| 9719 | |
| 9720 | /// GMMx20BC |
| 9721 | typedef union { |
| 9722 | struct { ///< |
| 9723 | UINT32 Reserved_17_0:18; ///< |
| 9724 | UINT32 Enable:1 ; ///< |
| 9725 | UINT32 Reserved_31_19:13; ///< |
| 9726 | } Field; ///< |
| 9727 | UINT32 Value; ///< |
| 9728 | } GMMx20BC_STRUCT; |
| 9729 | |
| 9730 | // **** GMMx20C0 Register Definition **** |
| 9731 | // Address |
| 9732 | #define GMMx20C0_ADDRESS 0x20c0 |
| 9733 | |
| 9734 | // Type |
| 9735 | #define GMMx20C0_TYPE TYPE_GMM |
| 9736 | // Field Data |
| 9737 | #define GMMx20C0_Reserved_17_0_OFFSET 0 |
| 9738 | #define GMMx20C0_Reserved_17_0_WIDTH 18 |
| 9739 | #define GMMx20C0_Reserved_17_0_MASK 0x3ffff |
| 9740 | #define GMMx20C0_Enable_OFFSET 18 |
| 9741 | #define GMMx20C0_Enable_WIDTH 1 |
| 9742 | #define GMMx20C0_Enable_MASK 0x40000 |
| 9743 | #define GMMx20C0_Reserved_31_19_OFFSET 19 |
| 9744 | #define GMMx20C0_Reserved_31_19_WIDTH 13 |
| 9745 | #define GMMx20C0_Reserved_31_19_MASK 0xfff80000 |
| 9746 | |
| 9747 | /// GMMx20C0 |
| 9748 | typedef union { |
| 9749 | struct { ///< |
| 9750 | UINT32 Reserved_17_0:18; ///< |
| 9751 | UINT32 Enable:1 ; ///< |
| 9752 | UINT32 Reserved_31_19:13; ///< |
| 9753 | } Field; ///< |
| 9754 | UINT32 Value; ///< |
| 9755 | } GMMx20C0_STRUCT; |
| 9756 | |
| 9757 | // **** GMMx20D4 Register Definition **** |
| 9758 | // Address |
| 9759 | #define GMMx20D4_ADDRESS 0x20d4 |
| 9760 | |
| 9761 | // Type |
| 9762 | #define GMMx20D4_TYPE TYPE_GMM |
| 9763 | // Field Data |
| 9764 | #define GMMx20D4_LocalBlackout_OFFSET 0 |
| 9765 | #define GMMx20D4_LocalBlackout_WIDTH 1 |
| 9766 | #define GMMx20D4_LocalBlackout_MASK 0x1 |
| 9767 | #define GMMx20D4_Reserved_31_1_OFFSET 1 |
| 9768 | #define GMMx20D4_Reserved_31_1_WIDTH 31 |
| 9769 | #define GMMx20D4_Reserved_31_1_MASK 0xfffffffe |
| 9770 | |
| 9771 | /// GMMx20D4 |
| 9772 | typedef union { |
| 9773 | struct { ///< |
| 9774 | UINT32 LocalBlackout:1 ; ///< |
| 9775 | UINT32 Reserved_31_1:31; ///< |
| 9776 | } Field; ///< |
| 9777 | UINT32 Value; ///< |
| 9778 | } GMMx20D4_STRUCT; |
| 9779 | |
| 9780 | // **** GMMx20EC Register Definition **** |
| 9781 | // Address |
| 9782 | #define GMMx20EC_ADDRESS 0x20ec |
| 9783 | |
| 9784 | // Type |
| 9785 | #define GMMx20EC_TYPE TYPE_GMM |
| 9786 | // Field Data |
| 9787 | #define GMMx20EC_RemoteBlackout_OFFSET 0 |
| 9788 | #define GMMx20EC_RemoteBlackout_WIDTH 1 |
| 9789 | #define GMMx20EC_RemoteBlackout_MASK 0x1 |
| 9790 | #define GMMx20EC_LocalBlackout_OFFSET 1 |
| 9791 | #define GMMx20EC_LocalBlackout_WIDTH 1 |
| 9792 | #define GMMx20EC_LocalBlackout_MASK 0x2 |
| 9793 | #define GMMx20EC_Reserved_31_2_OFFSET 2 |
| 9794 | #define GMMx20EC_Reserved_31_2_WIDTH 30 |
| 9795 | #define GMMx20EC_Reserved_31_2_MASK 0xfffffffc |
| 9796 | |
| 9797 | /// GMMx20EC |
| 9798 | typedef union { |
| 9799 | struct { ///< |
| 9800 | UINT32 RemoteBlackout:1 ; ///< |
| 9801 | UINT32 LocalBlackout:1 ; ///< |
| 9802 | UINT32 Reserved_31_2:30; ///< |
| 9803 | } Field; ///< |
| 9804 | UINT32 Value; ///< |
| 9805 | } GMMx20EC_STRUCT; |
| 9806 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 9807 | // **** GMMx2160 Register Definition **** |
| 9808 | // Address |
| 9809 | #define GMMx2160_ADDRESS 0x2160 |
| 9810 | |
| 9811 | // Type |
| 9812 | #define GMMx2160_TYPE TYPE_GMM |
| 9813 | // Field Data |
| 9814 | #define GMMx2160_Enable_OFFSET 0 |
| 9815 | #define GMMx2160_Enable_WIDTH 1 |
| 9816 | #define GMMx2160_Enable_MASK 0x1 |
| 9817 | #define GMMx2160_Prescale_OFFSET 1 |
| 9818 | #define GMMx2160_Prescale_WIDTH 2 |
| 9819 | #define GMMx2160_Prescale_MASK 0x6 |
| 9820 | #define GMMx2160_BlackoutExempt_OFFSET 3 |
| 9821 | #define GMMx2160_BlackoutExempt_WIDTH 1 |
| 9822 | #define GMMx2160_BlackoutExempt_MASK 0x8 |
| 9823 | #define GMMx2160_StallMode_OFFSET 4 |
| 9824 | #define GMMx2160_StallMode_WIDTH 2 |
| 9825 | #define GMMx2160_StallMode_MASK 0x30 |
| 9826 | #define GMMx2160_StallOverride_OFFSET 6 |
| 9827 | #define GMMx2160_StallOverride_WIDTH 1 |
| 9828 | #define GMMx2160_StallOverride_MASK 0x40 |
| 9829 | #define GMMx2160_MaxBurst_OFFSET 7 |
| 9830 | #define GMMx2160_MaxBurst_WIDTH 4 |
| 9831 | #define GMMx2160_MaxBurst_MASK 0x780 |
| 9832 | #define GMMx2160_LazyTimer_OFFSET 11 |
| 9833 | #define GMMx2160_LazyTimer_WIDTH 4 |
| 9834 | #define GMMx2160_LazyTimer_MASK 0x7800 |
| 9835 | #define GMMx2160_StallOverrideWtm_OFFSET 15 |
| 9836 | #define GMMx2160_StallOverrideWtm_WIDTH 1 |
| 9837 | #define GMMx2160_StallOverrideWtm_MASK 0x8000 |
| 9838 | #define GMMx2160_Reserved_19_16_OFFSET 16 |
| 9839 | #define GMMx2160_Reserved_19_16_WIDTH 4 |
| 9840 | #define GMMx2160_Reserved_19_16_MASK 0xf0000 |
| 9841 | #define GMMx2160_Reserved_31_20_OFFSET 20 |
| 9842 | #define GMMx2160_Reserved_31_20_WIDTH 12 |
| 9843 | #define GMMx2160_Reserved_31_20_MASK 0xfff00000 |
| 9844 | |
| 9845 | /// GMMx2160 |
| 9846 | typedef union { |
| 9847 | struct { ///< |
| 9848 | UINT32 Enable:1 ; ///< |
| 9849 | UINT32 Prescale:2 ; ///< |
| 9850 | UINT32 BlackoutExempt:1 ; ///< |
| 9851 | UINT32 StallMode:2 ; ///< |
| 9852 | UINT32 StallOverride:1 ; ///< |
| 9853 | UINT32 MaxBurst:4 ; ///< |
| 9854 | UINT32 LazyTimer:4 ; ///< |
| 9855 | UINT32 StallOverrideWtm:1 ; ///< |
| 9856 | UINT32 Reserved_19_16:4 ; ///< |
| 9857 | UINT32 Reserved_31_20:12; ///< |
| 9858 | } Field; ///< |
| 9859 | UINT32 Value; ///< |
| 9860 | } GMMx2160_STRUCT; |
| 9861 | |
| 9862 | // **** GMMx2164 Register Definition **** |
| 9863 | // Address |
| 9864 | #define GMMx2164_ADDRESS 0x2164 |
| 9865 | |
| 9866 | // Type |
| 9867 | #define GMMx2164_TYPE TYPE_GMM |
| 9868 | // Field Data |
| 9869 | #define GMMx2164_Enable_OFFSET 0 |
| 9870 | #define GMMx2164_Enable_WIDTH 1 |
| 9871 | #define GMMx2164_Enable_MASK 0x1 |
| 9872 | #define GMMx2164_Prescale_OFFSET 1 |
| 9873 | #define GMMx2164_Prescale_WIDTH 2 |
| 9874 | #define GMMx2164_Prescale_MASK 0x6 |
| 9875 | #define GMMx2164_BlackoutExempt_OFFSET 3 |
| 9876 | #define GMMx2164_BlackoutExempt_WIDTH 1 |
| 9877 | #define GMMx2164_BlackoutExempt_MASK 0x8 |
| 9878 | #define GMMx2164_StallMode_OFFSET 4 |
| 9879 | #define GMMx2164_StallMode_WIDTH 2 |
| 9880 | #define GMMx2164_StallMode_MASK 0x30 |
| 9881 | #define GMMx2164_StallOverride_OFFSET 6 |
| 9882 | #define GMMx2164_StallOverride_WIDTH 1 |
| 9883 | #define GMMx2164_StallOverride_MASK 0x40 |
| 9884 | #define GMMx2164_MaxBurst_OFFSET 7 |
| 9885 | #define GMMx2164_MaxBurst_WIDTH 4 |
| 9886 | #define GMMx2164_MaxBurst_MASK 0x780 |
| 9887 | #define GMMx2164_LazyTimer_OFFSET 11 |
| 9888 | #define GMMx2164_LazyTimer_WIDTH 4 |
| 9889 | #define GMMx2164_LazyTimer_MASK 0x7800 |
| 9890 | #define GMMx2164_StallOverrideWtm_OFFSET 15 |
| 9891 | #define GMMx2164_StallOverrideWtm_WIDTH 1 |
| 9892 | #define GMMx2164_StallOverrideWtm_MASK 0x8000 |
| 9893 | #define GMMx2164_Reserved_19_16_OFFSET 16 |
| 9894 | #define GMMx2164_Reserved_19_16_WIDTH 4 |
| 9895 | #define GMMx2164_Reserved_19_16_MASK 0xf0000 |
| 9896 | #define GMMx2164_Reserved_31_20_OFFSET 20 |
| 9897 | #define GMMx2164_Reserved_31_20_WIDTH 12 |
| 9898 | #define GMMx2164_Reserved_31_20_MASK 0xfff00000 |
| 9899 | |
| 9900 | /// GMMx2164 |
| 9901 | typedef union { |
| 9902 | struct { ///< |
| 9903 | UINT32 Enable:1 ; ///< |
| 9904 | UINT32 Prescale:2 ; ///< |
| 9905 | UINT32 BlackoutExempt:1 ; ///< |
| 9906 | UINT32 StallMode:2 ; ///< |
| 9907 | UINT32 StallOverride:1 ; ///< |
| 9908 | UINT32 MaxBurst:4 ; ///< |
| 9909 | UINT32 LazyTimer:4 ; ///< |
| 9910 | UINT32 StallOverrideWtm:1 ; ///< |
| 9911 | UINT32 Reserved_19_16:4 ; ///< |
| 9912 | UINT32 Reserved_31_20:12; ///< |
| 9913 | } Field; ///< |
| 9914 | UINT32 Value; ///< |
| 9915 | } GMMx2164_STRUCT; |
| 9916 | |
| 9917 | // **** GMMx2168 Register Definition **** |
| 9918 | // Address |
| 9919 | #define GMMx2168_ADDRESS 0x2168 |
| 9920 | |
| 9921 | // Type |
| 9922 | #define GMMx2168_TYPE TYPE_GMM |
| 9923 | // Field Data |
| 9924 | #define GMMx2168_Enable_OFFSET 0 |
| 9925 | #define GMMx2168_Enable_WIDTH 1 |
| 9926 | #define GMMx2168_Enable_MASK 0x1 |
| 9927 | #define GMMx2168_Prescale_OFFSET 1 |
| 9928 | #define GMMx2168_Prescale_WIDTH 2 |
| 9929 | #define GMMx2168_Prescale_MASK 0x6 |
| 9930 | #define GMMx2168_BlackoutExempt_OFFSET 3 |
| 9931 | #define GMMx2168_BlackoutExempt_WIDTH 1 |
| 9932 | #define GMMx2168_BlackoutExempt_MASK 0x8 |
| 9933 | #define GMMx2168_StallMode_OFFSET 4 |
| 9934 | #define GMMx2168_StallMode_WIDTH 2 |
| 9935 | #define GMMx2168_StallMode_MASK 0x30 |
| 9936 | #define GMMx2168_StallOverride_OFFSET 6 |
| 9937 | #define GMMx2168_StallOverride_WIDTH 1 |
| 9938 | #define GMMx2168_StallOverride_MASK 0x40 |
| 9939 | #define GMMx2168_MaxBurst_OFFSET 7 |
| 9940 | #define GMMx2168_MaxBurst_WIDTH 4 |
| 9941 | #define GMMx2168_MaxBurst_MASK 0x780 |
| 9942 | #define GMMx2168_LazyTimer_OFFSET 11 |
| 9943 | #define GMMx2168_LazyTimer_WIDTH 4 |
| 9944 | #define GMMx2168_LazyTimer_MASK 0x7800 |
| 9945 | #define GMMx2168_StallOverrideWtm_OFFSET 15 |
| 9946 | #define GMMx2168_StallOverrideWtm_WIDTH 1 |
| 9947 | #define GMMx2168_StallOverrideWtm_MASK 0x8000 |
| 9948 | #define GMMx2168_Reserved_19_16_OFFSET 16 |
| 9949 | #define GMMx2168_Reserved_19_16_WIDTH 4 |
| 9950 | #define GMMx2168_Reserved_19_16_MASK 0xf0000 |
| 9951 | #define GMMx2168_Reserved_31_20_OFFSET 20 |
| 9952 | #define GMMx2168_Reserved_31_20_WIDTH 12 |
| 9953 | #define GMMx2168_Reserved_31_20_MASK 0xfff00000 |
| 9954 | |
| 9955 | /// GMMx2168 |
| 9956 | typedef union { |
| 9957 | struct { ///< |
| 9958 | UINT32 Enable:1 ; ///< |
| 9959 | UINT32 Prescale:2 ; ///< |
| 9960 | UINT32 BlackoutExempt:1 ; ///< |
| 9961 | UINT32 StallMode:2 ; ///< |
| 9962 | UINT32 StallOverride:1 ; ///< |
| 9963 | UINT32 MaxBurst:4 ; ///< |
| 9964 | UINT32 LazyTimer:4 ; ///< |
| 9965 | UINT32 StallOverrideWtm:1 ; ///< |
| 9966 | UINT32 Reserved_19_16:4 ; ///< |
| 9967 | UINT32 Reserved_31_20:12; ///< |
| 9968 | } Field; ///< |
| 9969 | UINT32 Value; ///< |
| 9970 | } GMMx2168_STRUCT; |
| 9971 | |
| 9972 | // **** GMMx216C Register Definition **** |
| 9973 | // Address |
| 9974 | #define GMMx216C_ADDRESS 0x216c |
| 9975 | |
| 9976 | // Type |
| 9977 | #define GMMx216C_TYPE TYPE_GMM |
| 9978 | // Field Data |
| 9979 | #define GMMx216C_Enable_OFFSET 0 |
| 9980 | #define GMMx216C_Enable_WIDTH 1 |
| 9981 | #define GMMx216C_Enable_MASK 0x1 |
| 9982 | #define GMMx216C_Prescale_OFFSET 1 |
| 9983 | #define GMMx216C_Prescale_WIDTH 2 |
| 9984 | #define GMMx216C_Prescale_MASK 0x6 |
| 9985 | #define GMMx216C_BlackoutExempt_OFFSET 3 |
| 9986 | #define GMMx216C_BlackoutExempt_WIDTH 1 |
| 9987 | #define GMMx216C_BlackoutExempt_MASK 0x8 |
| 9988 | #define GMMx216C_StallMode_OFFSET 4 |
| 9989 | #define GMMx216C_StallMode_WIDTH 2 |
| 9990 | #define GMMx216C_StallMode_MASK 0x30 |
| 9991 | #define GMMx216C_StallOverride_OFFSET 6 |
| 9992 | #define GMMx216C_StallOverride_WIDTH 1 |
| 9993 | #define GMMx216C_StallOverride_MASK 0x40 |
| 9994 | #define GMMx216C_MaxBurst_OFFSET 7 |
| 9995 | #define GMMx216C_MaxBurst_WIDTH 4 |
| 9996 | #define GMMx216C_MaxBurst_MASK 0x780 |
| 9997 | #define GMMx216C_LazyTimer_OFFSET 11 |
| 9998 | #define GMMx216C_LazyTimer_WIDTH 4 |
| 9999 | #define GMMx216C_LazyTimer_MASK 0x7800 |
| 10000 | #define GMMx216C_StallOverrideWtm_OFFSET 15 |
| 10001 | #define GMMx216C_StallOverrideWtm_WIDTH 1 |
| 10002 | #define GMMx216C_StallOverrideWtm_MASK 0x8000 |
| 10003 | #define GMMx216C_Reserved_19_16_OFFSET 16 |
| 10004 | #define GMMx216C_Reserved_19_16_WIDTH 4 |
| 10005 | #define GMMx216C_Reserved_19_16_MASK 0xf0000 |
| 10006 | #define GMMx216C_Reserved_31_20_OFFSET 20 |
| 10007 | #define GMMx216C_Reserved_31_20_WIDTH 12 |
| 10008 | #define GMMx216C_Reserved_31_20_MASK 0xfff00000 |
| 10009 | |
| 10010 | /// GMMx216C |
| 10011 | typedef union { |
| 10012 | struct { ///< |
| 10013 | UINT32 Enable:1 ; ///< |
| 10014 | UINT32 Prescale:2 ; ///< |
| 10015 | UINT32 BlackoutExempt:1 ; ///< |
| 10016 | UINT32 StallMode:2 ; ///< |
| 10017 | UINT32 StallOverride:1 ; ///< |
| 10018 | UINT32 MaxBurst:4 ; ///< |
| 10019 | UINT32 LazyTimer:4 ; ///< |
| 10020 | UINT32 StallOverrideWtm:1 ; ///< |
| 10021 | UINT32 Reserved_19_16:4 ; ///< |
| 10022 | UINT32 Reserved_31_20:12; ///< |
| 10023 | } Field; ///< |
| 10024 | UINT32 Value; ///< |
| 10025 | } GMMx216C_STRUCT; |
| 10026 | |
| 10027 | // **** GMMx2170 Register Definition **** |
| 10028 | // Address |
| 10029 | #define GMMx2170_ADDRESS 0x2170 |
| 10030 | |
| 10031 | // Type |
| 10032 | #define GMMx2170_TYPE TYPE_GMM |
| 10033 | // Field Data |
| 10034 | #define GMMx2170_Enable_OFFSET 0 |
| 10035 | #define GMMx2170_Enable_WIDTH 1 |
| 10036 | #define GMMx2170_Enable_MASK 0x1 |
| 10037 | #define GMMx2170_Prescale_OFFSET 1 |
| 10038 | #define GMMx2170_Prescale_WIDTH 2 |
| 10039 | #define GMMx2170_Prescale_MASK 0x6 |
| 10040 | #define GMMx2170_BlackoutExempt_OFFSET 3 |
| 10041 | #define GMMx2170_BlackoutExempt_WIDTH 1 |
| 10042 | #define GMMx2170_BlackoutExempt_MASK 0x8 |
| 10043 | #define GMMx2170_StallMode_OFFSET 4 |
| 10044 | #define GMMx2170_StallMode_WIDTH 2 |
| 10045 | #define GMMx2170_StallMode_MASK 0x30 |
| 10046 | #define GMMx2170_StallOverride_OFFSET 6 |
| 10047 | #define GMMx2170_StallOverride_WIDTH 1 |
| 10048 | #define GMMx2170_StallOverride_MASK 0x40 |
| 10049 | #define GMMx2170_MaxBurst_OFFSET 7 |
| 10050 | #define GMMx2170_MaxBurst_WIDTH 4 |
| 10051 | #define GMMx2170_MaxBurst_MASK 0x780 |
| 10052 | #define GMMx2170_LazyTimer_OFFSET 11 |
| 10053 | #define GMMx2170_LazyTimer_WIDTH 4 |
| 10054 | #define GMMx2170_LazyTimer_MASK 0x7800 |
| 10055 | #define GMMx2170_StallOverrideWtm_OFFSET 15 |
| 10056 | #define GMMx2170_StallOverrideWtm_WIDTH 1 |
| 10057 | #define GMMx2170_StallOverrideWtm_MASK 0x8000 |
| 10058 | #define GMMx2170_Reserved_19_16_OFFSET 16 |
| 10059 | #define GMMx2170_Reserved_19_16_WIDTH 4 |
| 10060 | #define GMMx2170_Reserved_19_16_MASK 0xf0000 |
| 10061 | #define GMMx2170_Reserved_31_20_OFFSET 20 |
| 10062 | #define GMMx2170_Reserved_31_20_WIDTH 12 |
| 10063 | #define GMMx2170_Reserved_31_20_MASK 0xfff00000 |
| 10064 | |
| 10065 | /// GMMx2170 |
| 10066 | typedef union { |
| 10067 | struct { ///< |
| 10068 | UINT32 Enable:1 ; ///< |
| 10069 | UINT32 Prescale:2 ; ///< |
| 10070 | UINT32 BlackoutExempt:1 ; ///< |
| 10071 | UINT32 StallMode:2 ; ///< |
| 10072 | UINT32 StallOverride:1 ; ///< |
| 10073 | UINT32 MaxBurst:4 ; ///< |
| 10074 | UINT32 LazyTimer:4 ; ///< |
| 10075 | UINT32 StallOverrideWtm:1 ; ///< |
| 10076 | UINT32 Reserved_19_16:4 ; ///< |
| 10077 | UINT32 Reserved_31_20:12; ///< |
| 10078 | } Field; ///< |
| 10079 | UINT32 Value; ///< |
| 10080 | } GMMx2170_STRUCT; |
| 10081 | |
| 10082 | // **** GMMx2174 Register Definition **** |
| 10083 | // Address |
| 10084 | #define GMMx2174_ADDRESS 0x2174 |
| 10085 | |
| 10086 | // Type |
| 10087 | #define GMMx2174_TYPE TYPE_GMM |
| 10088 | // Field Data |
| 10089 | #define GMMx2174_Enable_OFFSET 0 |
| 10090 | #define GMMx2174_Enable_WIDTH 1 |
| 10091 | #define GMMx2174_Enable_MASK 0x1 |
| 10092 | #define GMMx2174_Prescale_OFFSET 1 |
| 10093 | #define GMMx2174_Prescale_WIDTH 2 |
| 10094 | #define GMMx2174_Prescale_MASK 0x6 |
| 10095 | #define GMMx2174_BlackoutExempt_OFFSET 3 |
| 10096 | #define GMMx2174_BlackoutExempt_WIDTH 1 |
| 10097 | #define GMMx2174_BlackoutExempt_MASK 0x8 |
| 10098 | #define GMMx2174_StallMode_OFFSET 4 |
| 10099 | #define GMMx2174_StallMode_WIDTH 2 |
| 10100 | #define GMMx2174_StallMode_MASK 0x30 |
| 10101 | #define GMMx2174_StallOverride_OFFSET 6 |
| 10102 | #define GMMx2174_StallOverride_WIDTH 1 |
| 10103 | #define GMMx2174_StallOverride_MASK 0x40 |
| 10104 | #define GMMx2174_MaxBurst_OFFSET 7 |
| 10105 | #define GMMx2174_MaxBurst_WIDTH 4 |
| 10106 | #define GMMx2174_MaxBurst_MASK 0x780 |
| 10107 | #define GMMx2174_LazyTimer_OFFSET 11 |
| 10108 | #define GMMx2174_LazyTimer_WIDTH 4 |
| 10109 | #define GMMx2174_LazyTimer_MASK 0x7800 |
| 10110 | #define GMMx2174_StallOverrideWtm_OFFSET 15 |
| 10111 | #define GMMx2174_StallOverrideWtm_WIDTH 1 |
| 10112 | #define GMMx2174_StallOverrideWtm_MASK 0x8000 |
| 10113 | #define GMMx2174_Reserved_19_16_OFFSET 16 |
| 10114 | #define GMMx2174_Reserved_19_16_WIDTH 4 |
| 10115 | #define GMMx2174_Reserved_19_16_MASK 0xf0000 |
| 10116 | #define GMMx2174_Reserved_31_20_OFFSET 20 |
| 10117 | #define GMMx2174_Reserved_31_20_WIDTH 12 |
| 10118 | #define GMMx2174_Reserved_31_20_MASK 0xfff00000 |
| 10119 | |
| 10120 | /// GMMx2174 |
| 10121 | typedef union { |
| 10122 | struct { ///< |
| 10123 | UINT32 Enable:1 ; ///< |
| 10124 | UINT32 Prescale:2 ; ///< |
| 10125 | UINT32 BlackoutExempt:1 ; ///< |
| 10126 | UINT32 StallMode:2 ; ///< |
| 10127 | UINT32 StallOverride:1 ; ///< |
| 10128 | UINT32 MaxBurst:4 ; ///< |
| 10129 | UINT32 LazyTimer:4 ; ///< |
| 10130 | UINT32 StallOverrideWtm:1 ; ///< |
| 10131 | UINT32 Reserved_19_16:4 ; ///< |
| 10132 | UINT32 Reserved_31_20:12; ///< |
| 10133 | } Field; ///< |
| 10134 | UINT32 Value; ///< |
| 10135 | } GMMx2174_STRUCT; |
| 10136 | |
| 10137 | // **** GMMx2178 Register Definition **** |
| 10138 | // Address |
| 10139 | #define GMMx2178_ADDRESS 0x2178 |
| 10140 | |
| 10141 | // Type |
| 10142 | #define GMMx2178_TYPE TYPE_GMM |
| 10143 | // Field Data |
| 10144 | #define GMMx2178_Enable_OFFSET 0 |
| 10145 | #define GMMx2178_Enable_WIDTH 1 |
| 10146 | #define GMMx2178_Enable_MASK 0x1 |
| 10147 | #define GMMx2178_Prescale_OFFSET 1 |
| 10148 | #define GMMx2178_Prescale_WIDTH 2 |
| 10149 | #define GMMx2178_Prescale_MASK 0x6 |
| 10150 | #define GMMx2178_BlackoutExempt_OFFSET 3 |
| 10151 | #define GMMx2178_BlackoutExempt_WIDTH 1 |
| 10152 | #define GMMx2178_BlackoutExempt_MASK 0x8 |
| 10153 | #define GMMx2178_StallMode_OFFSET 4 |
| 10154 | #define GMMx2178_StallMode_WIDTH 2 |
| 10155 | #define GMMx2178_StallMode_MASK 0x30 |
| 10156 | #define GMMx2178_StallOverride_OFFSET 6 |
| 10157 | #define GMMx2178_StallOverride_WIDTH 1 |
| 10158 | #define GMMx2178_StallOverride_MASK 0x40 |
| 10159 | #define GMMx2178_MaxBurst_OFFSET 7 |
| 10160 | #define GMMx2178_MaxBurst_WIDTH 4 |
| 10161 | #define GMMx2178_MaxBurst_MASK 0x780 |
| 10162 | #define GMMx2178_LazyTimer_OFFSET 11 |
| 10163 | #define GMMx2178_LazyTimer_WIDTH 4 |
| 10164 | #define GMMx2178_LazyTimer_MASK 0x7800 |
| 10165 | #define GMMx2178_StallOverrideWtm_OFFSET 15 |
| 10166 | #define GMMx2178_StallOverrideWtm_WIDTH 1 |
| 10167 | #define GMMx2178_StallOverrideWtm_MASK 0x8000 |
| 10168 | #define GMMx2178_Reserved_19_16_OFFSET 16 |
| 10169 | #define GMMx2178_Reserved_19_16_WIDTH 4 |
| 10170 | #define GMMx2178_Reserved_19_16_MASK 0xf0000 |
| 10171 | #define GMMx2178_Reserved_31_20_OFFSET 20 |
| 10172 | #define GMMx2178_Reserved_31_20_WIDTH 12 |
| 10173 | #define GMMx2178_Reserved_31_20_MASK 0xfff00000 |
| 10174 | |
| 10175 | /// GMMx2178 |
| 10176 | typedef union { |
| 10177 | struct { ///< |
| 10178 | UINT32 Enable:1 ; ///< |
| 10179 | UINT32 Prescale:2 ; ///< |
| 10180 | UINT32 BlackoutExempt:1 ; ///< |
| 10181 | UINT32 StallMode:2 ; ///< |
| 10182 | UINT32 StallOverride:1 ; ///< |
| 10183 | UINT32 MaxBurst:4 ; ///< |
| 10184 | UINT32 LazyTimer:4 ; ///< |
| 10185 | UINT32 StallOverrideWtm:1 ; ///< |
| 10186 | UINT32 Reserved_19_16:4 ; ///< |
| 10187 | UINT32 Reserved_31_20:12; ///< |
| 10188 | } Field; ///< |
| 10189 | UINT32 Value; ///< |
| 10190 | } GMMx2178_STRUCT; |
| 10191 | |
| 10192 | // **** GMMx217C Register Definition **** |
| 10193 | // Address |
| 10194 | #define GMMx217C_ADDRESS 0x217c |
| 10195 | |
| 10196 | // Type |
| 10197 | #define GMMx217C_TYPE TYPE_GMM |
| 10198 | // Field Data |
| 10199 | #define GMMx217C_Enable_OFFSET 0 |
| 10200 | #define GMMx217C_Enable_WIDTH 1 |
| 10201 | #define GMMx217C_Enable_MASK 0x1 |
| 10202 | #define GMMx217C_Prescale_OFFSET 1 |
| 10203 | #define GMMx217C_Prescale_WIDTH 2 |
| 10204 | #define GMMx217C_Prescale_MASK 0x6 |
| 10205 | #define GMMx217C_BlackoutExempt_OFFSET 3 |
| 10206 | #define GMMx217C_BlackoutExempt_WIDTH 1 |
| 10207 | #define GMMx217C_BlackoutExempt_MASK 0x8 |
| 10208 | #define GMMx217C_StallMode_OFFSET 4 |
| 10209 | #define GMMx217C_StallMode_WIDTH 2 |
| 10210 | #define GMMx217C_StallMode_MASK 0x30 |
| 10211 | #define GMMx217C_StallOverride_OFFSET 6 |
| 10212 | #define GMMx217C_StallOverride_WIDTH 1 |
| 10213 | #define GMMx217C_StallOverride_MASK 0x40 |
| 10214 | #define GMMx217C_MaxBurst_OFFSET 7 |
| 10215 | #define GMMx217C_MaxBurst_WIDTH 4 |
| 10216 | #define GMMx217C_MaxBurst_MASK 0x780 |
| 10217 | #define GMMx217C_LazyTimer_OFFSET 11 |
| 10218 | #define GMMx217C_LazyTimer_WIDTH 4 |
| 10219 | #define GMMx217C_LazyTimer_MASK 0x7800 |
| 10220 | #define GMMx217C_StallOverrideWtm_OFFSET 15 |
| 10221 | #define GMMx217C_StallOverrideWtm_WIDTH 1 |
| 10222 | #define GMMx217C_StallOverrideWtm_MASK 0x8000 |
| 10223 | #define GMMx217C_Reserved_19_16_OFFSET 16 |
| 10224 | #define GMMx217C_Reserved_19_16_WIDTH 4 |
| 10225 | #define GMMx217C_Reserved_19_16_MASK 0xf0000 |
| 10226 | #define GMMx217C_Reserved_31_20_OFFSET 20 |
| 10227 | #define GMMx217C_Reserved_31_20_WIDTH 12 |
| 10228 | #define GMMx217C_Reserved_31_20_MASK 0xfff00000 |
| 10229 | |
| 10230 | /// GMMx217C |
| 10231 | typedef union { |
| 10232 | struct { ///< |
| 10233 | UINT32 Enable:1 ; ///< |
| 10234 | UINT32 Prescale:2 ; ///< |
| 10235 | UINT32 BlackoutExempt:1 ; ///< |
| 10236 | UINT32 StallMode:2 ; ///< |
| 10237 | UINT32 StallOverride:1 ; ///< |
| 10238 | UINT32 MaxBurst:4 ; ///< |
| 10239 | UINT32 LazyTimer:4 ; ///< |
| 10240 | UINT32 StallOverrideWtm:1 ; ///< |
| 10241 | UINT32 Reserved_19_16:4 ; ///< |
| 10242 | UINT32 Reserved_31_20:12; ///< |
| 10243 | } Field; ///< |
| 10244 | UINT32 Value; ///< |
| 10245 | } GMMx217C_STRUCT; |
| 10246 | |
| 10247 | // **** GMMx2180 Register Definition **** |
| 10248 | // Address |
| 10249 | #define GMMx2180_ADDRESS 0x2180 |
| 10250 | |
| 10251 | // Type |
| 10252 | #define GMMx2180_TYPE TYPE_GMM |
| 10253 | // Field Data |
| 10254 | #define GMMx2180_Enable_OFFSET 0 |
| 10255 | #define GMMx2180_Enable_WIDTH 1 |
| 10256 | #define GMMx2180_Enable_MASK 0x1 |
| 10257 | #define GMMx2180_Prescale_OFFSET 1 |
| 10258 | #define GMMx2180_Prescale_WIDTH 2 |
| 10259 | #define GMMx2180_Prescale_MASK 0x6 |
| 10260 | #define GMMx2180_BlackoutExempt_OFFSET 3 |
| 10261 | #define GMMx2180_BlackoutExempt_WIDTH 1 |
| 10262 | #define GMMx2180_BlackoutExempt_MASK 0x8 |
| 10263 | #define GMMx2180_StallMode_OFFSET 4 |
| 10264 | #define GMMx2180_StallMode_WIDTH 2 |
| 10265 | #define GMMx2180_StallMode_MASK 0x30 |
| 10266 | #define GMMx2180_StallOverride_OFFSET 6 |
| 10267 | #define GMMx2180_StallOverride_WIDTH 1 |
| 10268 | #define GMMx2180_StallOverride_MASK 0x40 |
| 10269 | #define GMMx2180_MaxBurst_OFFSET 7 |
| 10270 | #define GMMx2180_MaxBurst_WIDTH 4 |
| 10271 | #define GMMx2180_MaxBurst_MASK 0x780 |
| 10272 | #define GMMx2180_LazyTimer_OFFSET 11 |
| 10273 | #define GMMx2180_LazyTimer_WIDTH 4 |
| 10274 | #define GMMx2180_LazyTimer_MASK 0x7800 |
| 10275 | #define GMMx2180_StallOverrideWtm_OFFSET 15 |
| 10276 | #define GMMx2180_StallOverrideWtm_WIDTH 1 |
| 10277 | #define GMMx2180_StallOverrideWtm_MASK 0x8000 |
| 10278 | #define GMMx2180_Reserved_19_16_OFFSET 16 |
| 10279 | #define GMMx2180_Reserved_19_16_WIDTH 4 |
| 10280 | #define GMMx2180_Reserved_19_16_MASK 0xf0000 |
| 10281 | #define GMMx2180_Reserved_31_20_OFFSET 20 |
| 10282 | #define GMMx2180_Reserved_31_20_WIDTH 12 |
| 10283 | #define GMMx2180_Reserved_31_20_MASK 0xfff00000 |
| 10284 | |
| 10285 | /// GMMx2180 |
| 10286 | typedef union { |
| 10287 | struct { ///< |
| 10288 | UINT32 Enable:1 ; ///< |
| 10289 | UINT32 Prescale:2 ; ///< |
| 10290 | UINT32 BlackoutExempt:1 ; ///< |
| 10291 | UINT32 StallMode:2 ; ///< |
| 10292 | UINT32 StallOverride:1 ; ///< |
| 10293 | UINT32 MaxBurst:4 ; ///< |
| 10294 | UINT32 LazyTimer:4 ; ///< |
| 10295 | UINT32 StallOverrideWtm:1 ; ///< |
| 10296 | UINT32 Reserved_19_16:4 ; ///< |
| 10297 | UINT32 Reserved_31_20:12; ///< |
| 10298 | } Field; ///< |
| 10299 | UINT32 Value; ///< |
| 10300 | } GMMx2180_STRUCT; |
| 10301 | |
| 10302 | // **** GMMx2184 Register Definition **** |
| 10303 | // Address |
| 10304 | #define GMMx2184_ADDRESS 0x2184 |
| 10305 | |
| 10306 | // Type |
| 10307 | #define GMMx2184_TYPE TYPE_GMM |
| 10308 | // Field Data |
| 10309 | #define GMMx2184_Enable_OFFSET 0 |
| 10310 | #define GMMx2184_Enable_WIDTH 1 |
| 10311 | #define GMMx2184_Enable_MASK 0x1 |
| 10312 | #define GMMx2184_Prescale_OFFSET 1 |
| 10313 | #define GMMx2184_Prescale_WIDTH 2 |
| 10314 | #define GMMx2184_Prescale_MASK 0x6 |
| 10315 | #define GMMx2184_BlackoutExempt_OFFSET 3 |
| 10316 | #define GMMx2184_BlackoutExempt_WIDTH 1 |
| 10317 | #define GMMx2184_BlackoutExempt_MASK 0x8 |
| 10318 | #define GMMx2184_StallMode_OFFSET 4 |
| 10319 | #define GMMx2184_StallMode_WIDTH 2 |
| 10320 | #define GMMx2184_StallMode_MASK 0x30 |
| 10321 | #define GMMx2184_StallOverride_OFFSET 6 |
| 10322 | #define GMMx2184_StallOverride_WIDTH 1 |
| 10323 | #define GMMx2184_StallOverride_MASK 0x40 |
| 10324 | #define GMMx2184_MaxBurst_OFFSET 7 |
| 10325 | #define GMMx2184_MaxBurst_WIDTH 4 |
| 10326 | #define GMMx2184_MaxBurst_MASK 0x780 |
| 10327 | #define GMMx2184_LazyTimer_OFFSET 11 |
| 10328 | #define GMMx2184_LazyTimer_WIDTH 4 |
| 10329 | #define GMMx2184_LazyTimer_MASK 0x7800 |
| 10330 | #define GMMx2184_StallOverrideWtm_OFFSET 15 |
| 10331 | #define GMMx2184_StallOverrideWtm_WIDTH 1 |
| 10332 | #define GMMx2184_StallOverrideWtm_MASK 0x8000 |
| 10333 | #define GMMx2184_Reserved_19_16_OFFSET 16 |
| 10334 | #define GMMx2184_Reserved_19_16_WIDTH 4 |
| 10335 | #define GMMx2184_Reserved_19_16_MASK 0xf0000 |
| 10336 | #define GMMx2184_Reserved_31_20_OFFSET 20 |
| 10337 | #define GMMx2184_Reserved_31_20_WIDTH 12 |
| 10338 | #define GMMx2184_Reserved_31_20_MASK 0xfff00000 |
| 10339 | |
| 10340 | /// GMMx2184 |
| 10341 | typedef union { |
| 10342 | struct { ///< |
| 10343 | UINT32 Enable:1 ; ///< |
| 10344 | UINT32 Prescale:2 ; ///< |
| 10345 | UINT32 BlackoutExempt:1 ; ///< |
| 10346 | UINT32 StallMode:2 ; ///< |
| 10347 | UINT32 StallOverride:1 ; ///< |
| 10348 | UINT32 MaxBurst:4 ; ///< |
| 10349 | UINT32 LazyTimer:4 ; ///< |
| 10350 | UINT32 StallOverrideWtm:1 ; ///< |
| 10351 | UINT32 Reserved_19_16:4 ; ///< |
| 10352 | UINT32 Reserved_31_20:12; ///< |
| 10353 | } Field; ///< |
| 10354 | UINT32 Value; ///< |
| 10355 | } GMMx2184_STRUCT; |
| 10356 | |
| 10357 | // **** GMMx2188 Register Definition **** |
| 10358 | // Address |
| 10359 | #define GMMx2188_ADDRESS 0x2188 |
| 10360 | |
| 10361 | // Type |
| 10362 | #define GMMx2188_TYPE TYPE_GMM |
| 10363 | // Field Data |
| 10364 | #define GMMx2188_Enable_OFFSET 0 |
| 10365 | #define GMMx2188_Enable_WIDTH 1 |
| 10366 | #define GMMx2188_Enable_MASK 0x1 |
| 10367 | #define GMMx2188_Prescale_OFFSET 1 |
| 10368 | #define GMMx2188_Prescale_WIDTH 2 |
| 10369 | #define GMMx2188_Prescale_MASK 0x6 |
| 10370 | #define GMMx2188_BlackoutExempt_OFFSET 3 |
| 10371 | #define GMMx2188_BlackoutExempt_WIDTH 1 |
| 10372 | #define GMMx2188_BlackoutExempt_MASK 0x8 |
| 10373 | #define GMMx2188_StallMode_OFFSET 4 |
| 10374 | #define GMMx2188_StallMode_WIDTH 2 |
| 10375 | #define GMMx2188_StallMode_MASK 0x30 |
| 10376 | #define GMMx2188_StallOverride_OFFSET 6 |
| 10377 | #define GMMx2188_StallOverride_WIDTH 1 |
| 10378 | #define GMMx2188_StallOverride_MASK 0x40 |
| 10379 | #define GMMx2188_MaxBurst_OFFSET 7 |
| 10380 | #define GMMx2188_MaxBurst_WIDTH 4 |
| 10381 | #define GMMx2188_MaxBurst_MASK 0x780 |
| 10382 | #define GMMx2188_LazyTimer_OFFSET 11 |
| 10383 | #define GMMx2188_LazyTimer_WIDTH 4 |
| 10384 | #define GMMx2188_LazyTimer_MASK 0x7800 |
| 10385 | #define GMMx2188_StallOverrideWtm_OFFSET 15 |
| 10386 | #define GMMx2188_StallOverrideWtm_WIDTH 1 |
| 10387 | #define GMMx2188_StallOverrideWtm_MASK 0x8000 |
| 10388 | #define GMMx2188_ReqLimit_OFFSET 16 |
| 10389 | #define GMMx2188_ReqLimit_WIDTH 4 |
| 10390 | #define GMMx2188_ReqLimit_MASK 0xf0000 |
| 10391 | #define GMMx2188_Reserved_31_20_OFFSET 20 |
| 10392 | #define GMMx2188_Reserved_31_20_WIDTH 12 |
| 10393 | #define GMMx2188_Reserved_31_20_MASK 0xfff00000 |
| 10394 | |
| 10395 | /// GMMx2188 |
| 10396 | typedef union { |
| 10397 | struct { ///< |
| 10398 | UINT32 Enable:1 ; ///< |
| 10399 | UINT32 Prescale:2 ; ///< |
| 10400 | UINT32 BlackoutExempt:1 ; ///< |
| 10401 | UINT32 StallMode:2 ; ///< |
| 10402 | UINT32 StallOverride:1 ; ///< |
| 10403 | UINT32 MaxBurst:4 ; ///< |
| 10404 | UINT32 LazyTimer:4 ; ///< |
| 10405 | UINT32 StallOverrideWtm:1 ; ///< |
| 10406 | UINT32 ReqLimit:4 ; ///< |
| 10407 | UINT32 Reserved_31_20:12; ///< |
| 10408 | } Field; ///< |
| 10409 | UINT32 Value; ///< |
| 10410 | } GMMx2188_STRUCT; |
| 10411 | |
| 10412 | // **** GMMx218C Register Definition **** |
| 10413 | // Address |
| 10414 | #define GMMx218C_ADDRESS 0x218c |
| 10415 | |
| 10416 | // Type |
| 10417 | #define GMMx218C_TYPE TYPE_GMM |
| 10418 | // Field Data |
| 10419 | #define GMMx218C_Enable_OFFSET 0 |
| 10420 | #define GMMx218C_Enable_WIDTH 1 |
| 10421 | #define GMMx218C_Enable_MASK 0x1 |
| 10422 | #define GMMx218C_Prescale_OFFSET 1 |
| 10423 | #define GMMx218C_Prescale_WIDTH 2 |
| 10424 | #define GMMx218C_Prescale_MASK 0x6 |
| 10425 | #define GMMx218C_BlackoutExempt_OFFSET 3 |
| 10426 | #define GMMx218C_BlackoutExempt_WIDTH 1 |
| 10427 | #define GMMx218C_BlackoutExempt_MASK 0x8 |
| 10428 | #define GMMx218C_StallMode_OFFSET 4 |
| 10429 | #define GMMx218C_StallMode_WIDTH 2 |
| 10430 | #define GMMx218C_StallMode_MASK 0x30 |
| 10431 | #define GMMx218C_StallOverride_OFFSET 6 |
| 10432 | #define GMMx218C_StallOverride_WIDTH 1 |
| 10433 | #define GMMx218C_StallOverride_MASK 0x40 |
| 10434 | #define GMMx218C_MaxBurst_OFFSET 7 |
| 10435 | #define GMMx218C_MaxBurst_WIDTH 4 |
| 10436 | #define GMMx218C_MaxBurst_MASK 0x780 |
| 10437 | #define GMMx218C_LazyTimer_OFFSET 11 |
| 10438 | #define GMMx218C_LazyTimer_WIDTH 4 |
| 10439 | #define GMMx218C_LazyTimer_MASK 0x7800 |
| 10440 | #define GMMx218C_StallOverrideWtm_OFFSET 15 |
| 10441 | #define GMMx218C_StallOverrideWtm_WIDTH 1 |
| 10442 | #define GMMx218C_StallOverrideWtm_MASK 0x8000 |
| 10443 | #define GMMx218C_Reserved_19_16_OFFSET 16 |
| 10444 | #define GMMx218C_Reserved_19_16_WIDTH 4 |
| 10445 | #define GMMx218C_Reserved_19_16_MASK 0xf0000 |
| 10446 | #define GMMx218C_Reserved_31_20_OFFSET 20 |
| 10447 | #define GMMx218C_Reserved_31_20_WIDTH 12 |
| 10448 | #define GMMx218C_Reserved_31_20_MASK 0xfff00000 |
| 10449 | |
| 10450 | /// GMMx218C |
| 10451 | typedef union { |
| 10452 | struct { ///< |
| 10453 | UINT32 Enable:1 ; ///< |
| 10454 | UINT32 Prescale:2 ; ///< |
| 10455 | UINT32 BlackoutExempt:1 ; ///< |
| 10456 | UINT32 StallMode:2 ; ///< |
| 10457 | UINT32 StallOverride:1 ; ///< |
| 10458 | UINT32 MaxBurst:4 ; ///< |
| 10459 | UINT32 LazyTimer:4 ; ///< |
| 10460 | UINT32 StallOverrideWtm:1 ; ///< |
| 10461 | UINT32 Reserved_19_16:4 ; ///< |
| 10462 | UINT32 Reserved_31_20:12; ///< |
| 10463 | } Field; ///< |
| 10464 | UINT32 Value; ///< |
| 10465 | } GMMx218C_STRUCT; |
| 10466 | |
| 10467 | // **** GMMx2190 Register Definition **** |
| 10468 | // Address |
| 10469 | #define GMMx2190_ADDRESS 0x2190 |
| 10470 | |
| 10471 | // Type |
| 10472 | #define GMMx2190_TYPE TYPE_GMM |
| 10473 | // Field Data |
| 10474 | #define GMMx2190_Enable_OFFSET 0 |
| 10475 | #define GMMx2190_Enable_WIDTH 1 |
| 10476 | #define GMMx2190_Enable_MASK 0x1 |
| 10477 | #define GMMx2190_Reserved_1_1_OFFSET 1 |
| 10478 | #define GMMx2190_Reserved_1_1_WIDTH 1 |
| 10479 | #define GMMx2190_Reserved_1_1_MASK 0x2 |
| 10480 | #define GMMx2190_StallMode_OFFSET 2 |
| 10481 | #define GMMx2190_StallMode_WIDTH 1 |
| 10482 | #define GMMx2190_StallMode_MASK 0x4 |
| 10483 | #define GMMx2190_MaxBurst_OFFSET 3 |
| 10484 | #define GMMx2190_MaxBurst_WIDTH 4 |
| 10485 | #define GMMx2190_MaxBurst_MASK 0x78 |
| 10486 | #define GMMx2190_AskCredits_OFFSET 7 |
| 10487 | #define GMMx2190_AskCredits_WIDTH 6 |
| 10488 | #define GMMx2190_AskCredits_MASK 0x1f80 |
| 10489 | #define GMMx2190_LazyTimer_OFFSET 13 |
| 10490 | #define GMMx2190_LazyTimer_WIDTH 4 |
| 10491 | #define GMMx2190_LazyTimer_MASK 0x1e000 |
| 10492 | #define GMMx2190_StallThreshold_OFFSET 17 |
| 10493 | #define GMMx2190_StallThreshold_WIDTH 6 |
| 10494 | #define GMMx2190_StallThreshold_MASK 0x7e0000 |
| 10495 | #define GMMx2190_Reserved_31_23_OFFSET 23 |
| 10496 | #define GMMx2190_Reserved_31_23_WIDTH 9 |
| 10497 | #define GMMx2190_Reserved_31_23_MASK 0xff800000 |
| 10498 | |
| 10499 | /// GMMx2190 |
| 10500 | typedef union { |
| 10501 | struct { ///< |
| 10502 | UINT32 Enable:1 ; ///< |
| 10503 | UINT32 Reserved_1_1:1 ; ///< |
| 10504 | UINT32 StallMode:1 ; ///< |
| 10505 | UINT32 MaxBurst:4 ; ///< |
| 10506 | UINT32 AskCredits:6 ; ///< |
| 10507 | UINT32 LazyTimer:4 ; ///< |
| 10508 | UINT32 StallThreshold:6 ; ///< |
| 10509 | UINT32 Reserved_31_23:9 ; ///< |
| 10510 | } Field; ///< |
| 10511 | UINT32 Value; ///< |
| 10512 | } GMMx2190_STRUCT; |
| 10513 | |
| 10514 | // **** GMMx2194 Register Definition **** |
| 10515 | // Address |
| 10516 | #define GMMx2194_ADDRESS 0x2194 |
| 10517 | |
| 10518 | // Type |
| 10519 | #define GMMx2194_TYPE TYPE_GMM |
| 10520 | // Field Data |
| 10521 | #define GMMx2194_Enable_OFFSET 0 |
| 10522 | #define GMMx2194_Enable_WIDTH 1 |
| 10523 | #define GMMx2194_Enable_MASK 0x1 |
| 10524 | #define GMMx2194_Reserved_1_1_OFFSET 1 |
| 10525 | #define GMMx2194_Reserved_1_1_WIDTH 1 |
| 10526 | #define GMMx2194_Reserved_1_1_MASK 0x2 |
| 10527 | #define GMMx2194_StallMode_OFFSET 2 |
| 10528 | #define GMMx2194_StallMode_WIDTH 1 |
| 10529 | #define GMMx2194_StallMode_MASK 0x4 |
| 10530 | #define GMMx2194_MaxBurst_OFFSET 3 |
| 10531 | #define GMMx2194_MaxBurst_WIDTH 4 |
| 10532 | #define GMMx2194_MaxBurst_MASK 0x78 |
| 10533 | #define GMMx2194_AskCredits_OFFSET 7 |
| 10534 | #define GMMx2194_AskCredits_WIDTH 6 |
| 10535 | #define GMMx2194_AskCredits_MASK 0x1f80 |
| 10536 | #define GMMx2194_LazyTimer_OFFSET 13 |
| 10537 | #define GMMx2194_LazyTimer_WIDTH 4 |
| 10538 | #define GMMx2194_LazyTimer_MASK 0x1e000 |
| 10539 | #define GMMx2194_StallThreshold_OFFSET 17 |
| 10540 | #define GMMx2194_StallThreshold_WIDTH 6 |
| 10541 | #define GMMx2194_StallThreshold_MASK 0x7e0000 |
| 10542 | #define GMMx2194_Reserved_31_23_OFFSET 23 |
| 10543 | #define GMMx2194_Reserved_31_23_WIDTH 9 |
| 10544 | #define GMMx2194_Reserved_31_23_MASK 0xff800000 |
| 10545 | |
| 10546 | /// GMMx2194 |
| 10547 | typedef union { |
| 10548 | struct { ///< |
| 10549 | UINT32 Enable:1 ; ///< |
| 10550 | UINT32 Reserved_1_1:1 ; ///< |
| 10551 | UINT32 StallMode:1 ; ///< |
| 10552 | UINT32 MaxBurst:4 ; ///< |
| 10553 | UINT32 AskCredits:6 ; ///< |
| 10554 | UINT32 LazyTimer:4 ; ///< |
| 10555 | UINT32 StallThreshold:6 ; ///< |
| 10556 | UINT32 Reserved_31_23:9 ; ///< |
| 10557 | } Field; ///< |
| 10558 | UINT32 Value; ///< |
| 10559 | } GMMx2194_STRUCT; |
| 10560 | |
| 10561 | // **** GMMx2198 Register Definition **** |
| 10562 | // Address |
| 10563 | #define GMMx2198_ADDRESS 0x2198 |
| 10564 | |
| 10565 | // Type |
| 10566 | #define GMMx2198_TYPE TYPE_GMM |
| 10567 | // Field Data |
| 10568 | #define GMMx2198_Enable_OFFSET 0 |
| 10569 | #define GMMx2198_Enable_WIDTH 1 |
| 10570 | #define GMMx2198_Enable_MASK 0x1 |
| 10571 | #define GMMx2198_Reserved_1_1_OFFSET 1 |
| 10572 | #define GMMx2198_Reserved_1_1_WIDTH 1 |
| 10573 | #define GMMx2198_Reserved_1_1_MASK 0x2 |
| 10574 | #define GMMx2198_StallMode_OFFSET 2 |
| 10575 | #define GMMx2198_StallMode_WIDTH 1 |
| 10576 | #define GMMx2198_StallMode_MASK 0x4 |
| 10577 | #define GMMx2198_MaxBurst_OFFSET 3 |
| 10578 | #define GMMx2198_MaxBurst_WIDTH 4 |
| 10579 | #define GMMx2198_MaxBurst_MASK 0x78 |
| 10580 | #define GMMx2198_AskCredits_OFFSET 7 |
| 10581 | #define GMMx2198_AskCredits_WIDTH 6 |
| 10582 | #define GMMx2198_AskCredits_MASK 0x1f80 |
| 10583 | #define GMMx2198_LazyTimer_OFFSET 13 |
| 10584 | #define GMMx2198_LazyTimer_WIDTH 4 |
| 10585 | #define GMMx2198_LazyTimer_MASK 0x1e000 |
| 10586 | #define GMMx2198_StallThreshold_OFFSET 17 |
| 10587 | #define GMMx2198_StallThreshold_WIDTH 6 |
| 10588 | #define GMMx2198_StallThreshold_MASK 0x7e0000 |
| 10589 | #define GMMx2198_Reserved_31_23_OFFSET 23 |
| 10590 | #define GMMx2198_Reserved_31_23_WIDTH 9 |
| 10591 | #define GMMx2198_Reserved_31_23_MASK 0xff800000 |
| 10592 | |
| 10593 | /// GMMx2198 |
| 10594 | typedef union { |
| 10595 | struct { ///< |
| 10596 | UINT32 Enable:1 ; ///< |
| 10597 | UINT32 Reserved_1_1:1 ; ///< |
| 10598 | UINT32 StallMode:1 ; ///< |
| 10599 | UINT32 MaxBurst:4 ; ///< |
| 10600 | UINT32 AskCredits:6 ; ///< |
| 10601 | UINT32 LazyTimer:4 ; ///< |
| 10602 | UINT32 StallThreshold:6 ; ///< |
| 10603 | UINT32 Reserved_31_23:9 ; ///< |
| 10604 | } Field; ///< |
| 10605 | UINT32 Value; ///< |
| 10606 | } GMMx2198_STRUCT; |
| 10607 | |
| 10608 | // **** GMMx219C Register Definition **** |
| 10609 | // Address |
| 10610 | #define GMMx219C_ADDRESS 0x219c |
| 10611 | |
| 10612 | // Type |
| 10613 | #define GMMx219C_TYPE TYPE_GMM |
| 10614 | // Field Data |
| 10615 | #define GMMx219C_Enable_OFFSET 0 |
| 10616 | #define GMMx219C_Enable_WIDTH 1 |
| 10617 | #define GMMx219C_Enable_MASK 0x1 |
| 10618 | #define GMMx219C_Reserved_1_1_OFFSET 1 |
| 10619 | #define GMMx219C_Reserved_1_1_WIDTH 1 |
| 10620 | #define GMMx219C_Reserved_1_1_MASK 0x2 |
| 10621 | #define GMMx219C_StallMode_OFFSET 2 |
| 10622 | #define GMMx219C_StallMode_WIDTH 1 |
| 10623 | #define GMMx219C_StallMode_MASK 0x4 |
| 10624 | #define GMMx219C_MaxBurst_OFFSET 3 |
| 10625 | #define GMMx219C_MaxBurst_WIDTH 4 |
| 10626 | #define GMMx219C_MaxBurst_MASK 0x78 |
| 10627 | #define GMMx219C_AskCredits_OFFSET 7 |
| 10628 | #define GMMx219C_AskCredits_WIDTH 6 |
| 10629 | #define GMMx219C_AskCredits_MASK 0x1f80 |
| 10630 | #define GMMx219C_LazyTimer_OFFSET 13 |
| 10631 | #define GMMx219C_LazyTimer_WIDTH 4 |
| 10632 | #define GMMx219C_LazyTimer_MASK 0x1e000 |
| 10633 | #define GMMx219C_StallThreshold_OFFSET 17 |
| 10634 | #define GMMx219C_StallThreshold_WIDTH 6 |
| 10635 | #define GMMx219C_StallThreshold_MASK 0x7e0000 |
| 10636 | #define GMMx219C_Reserved_31_23_OFFSET 23 |
| 10637 | #define GMMx219C_Reserved_31_23_WIDTH 9 |
| 10638 | #define GMMx219C_Reserved_31_23_MASK 0xff800000 |
| 10639 | |
| 10640 | /// GMMx219C |
| 10641 | typedef union { |
| 10642 | struct { ///< |
| 10643 | UINT32 Enable:1 ; ///< |
| 10644 | UINT32 Reserved_1_1:1 ; ///< |
| 10645 | UINT32 StallMode:1 ; ///< |
| 10646 | UINT32 MaxBurst:4 ; ///< |
| 10647 | UINT32 AskCredits:6 ; ///< |
| 10648 | UINT32 LazyTimer:4 ; ///< |
| 10649 | UINT32 StallThreshold:6 ; ///< |
| 10650 | UINT32 Reserved_31_23:9 ; ///< |
| 10651 | } Field; ///< |
| 10652 | UINT32 Value; ///< |
| 10653 | } GMMx219C_STRUCT; |
| 10654 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 10655 | // **** GMMx21A4 Register Definition **** |
| 10656 | // Address |
| 10657 | #define GMMx21A4_ADDRESS 0x21a4 |
| 10658 | |
| 10659 | // Type |
| 10660 | #define GMMx21A4_TYPE TYPE_GMM |
| 10661 | // Field Data |
| 10662 | #define GMMx21A4_Enable_OFFSET 0 |
| 10663 | #define GMMx21A4_Enable_WIDTH 1 |
| 10664 | #define GMMx21A4_Enable_MASK 0x1 |
| 10665 | #define GMMx21A4_Prescale_OFFSET 1 |
| 10666 | #define GMMx21A4_Prescale_WIDTH 2 |
| 10667 | #define GMMx21A4_Prescale_MASK 0x6 |
| 10668 | #define GMMx21A4_BlackoutExempt_OFFSET 3 |
| 10669 | #define GMMx21A4_BlackoutExempt_WIDTH 1 |
| 10670 | #define GMMx21A4_BlackoutExempt_MASK 0x8 |
| 10671 | #define GMMx21A4_StallMode_OFFSET 4 |
| 10672 | #define GMMx21A4_StallMode_WIDTH 2 |
| 10673 | #define GMMx21A4_StallMode_MASK 0x30 |
| 10674 | #define GMMx21A4_StallOverride_OFFSET 6 |
| 10675 | #define GMMx21A4_StallOverride_WIDTH 1 |
| 10676 | #define GMMx21A4_StallOverride_MASK 0x40 |
| 10677 | #define GMMx21A4_MaxBurst_OFFSET 7 |
| 10678 | #define GMMx21A4_MaxBurst_WIDTH 4 |
| 10679 | #define GMMx21A4_MaxBurst_MASK 0x780 |
| 10680 | #define GMMx21A4_LazyTimer_OFFSET 11 |
| 10681 | #define GMMx21A4_LazyTimer_WIDTH 4 |
| 10682 | #define GMMx21A4_LazyTimer_MASK 0x7800 |
| 10683 | #define GMMx21A4_StallOverrideWtm_OFFSET 15 |
| 10684 | #define GMMx21A4_StallOverrideWtm_WIDTH 1 |
| 10685 | #define GMMx21A4_StallOverrideWtm_MASK 0x8000 |
| 10686 | #define GMMx21A4_Reserved_31_16_OFFSET 16 |
| 10687 | #define GMMx21A4_Reserved_31_16_WIDTH 16 |
| 10688 | #define GMMx21A4_Reserved_31_16_MASK 0xffff0000 |
| 10689 | |
| 10690 | /// GMMx21A4 |
| 10691 | typedef union { |
| 10692 | struct { ///< |
| 10693 | UINT32 Enable:1 ; ///< |
| 10694 | UINT32 Prescale:2 ; ///< |
| 10695 | UINT32 BlackoutExempt:1 ; ///< |
| 10696 | UINT32 StallMode:2 ; ///< |
| 10697 | UINT32 StallOverride:1 ; ///< |
| 10698 | UINT32 MaxBurst:4 ; ///< |
| 10699 | UINT32 LazyTimer:4 ; ///< |
| 10700 | UINT32 StallOverrideWtm:1 ; ///< |
| 10701 | UINT32 Reserved_31_16:16; ///< |
| 10702 | } Field; ///< |
| 10703 | UINT32 Value; ///< |
| 10704 | } GMMx21A4_STRUCT; |
| 10705 | |
| 10706 | // **** GMMx21A8 Register Definition **** |
| 10707 | // Address |
| 10708 | #define GMMx21A8_ADDRESS 0x21a8 |
| 10709 | |
| 10710 | // Type |
| 10711 | #define GMMx21A8_TYPE TYPE_GMM |
| 10712 | // Field Data |
| 10713 | #define GMMx21A8_Enable_OFFSET 0 |
| 10714 | #define GMMx21A8_Enable_WIDTH 1 |
| 10715 | #define GMMx21A8_Enable_MASK 0x1 |
| 10716 | #define GMMx21A8_Prescale_OFFSET 1 |
| 10717 | #define GMMx21A8_Prescale_WIDTH 2 |
| 10718 | #define GMMx21A8_Prescale_MASK 0x6 |
| 10719 | #define GMMx21A8_BlackoutExempt_OFFSET 3 |
| 10720 | #define GMMx21A8_BlackoutExempt_WIDTH 1 |
| 10721 | #define GMMx21A8_BlackoutExempt_MASK 0x8 |
| 10722 | #define GMMx21A8_StallMode_OFFSET 4 |
| 10723 | #define GMMx21A8_StallMode_WIDTH 2 |
| 10724 | #define GMMx21A8_StallMode_MASK 0x30 |
| 10725 | #define GMMx21A8_StallOverride_OFFSET 6 |
| 10726 | #define GMMx21A8_StallOverride_WIDTH 1 |
| 10727 | #define GMMx21A8_StallOverride_MASK 0x40 |
| 10728 | #define GMMx21A8_MaxBurst_OFFSET 7 |
| 10729 | #define GMMx21A8_MaxBurst_WIDTH 4 |
| 10730 | #define GMMx21A8_MaxBurst_MASK 0x780 |
| 10731 | #define GMMx21A8_LazyTimer_OFFSET 11 |
| 10732 | #define GMMx21A8_LazyTimer_WIDTH 4 |
| 10733 | #define GMMx21A8_LazyTimer_MASK 0x7800 |
| 10734 | #define GMMx21A8_StallOverrideWtm_OFFSET 15 |
| 10735 | #define GMMx21A8_StallOverrideWtm_WIDTH 1 |
| 10736 | #define GMMx21A8_StallOverrideWtm_MASK 0x8000 |
| 10737 | #define GMMx21A8_Reserved_31_16_OFFSET 16 |
| 10738 | #define GMMx21A8_Reserved_31_16_WIDTH 16 |
| 10739 | #define GMMx21A8_Reserved_31_16_MASK 0xffff0000 |
| 10740 | |
| 10741 | /// GMMx21A8 |
| 10742 | typedef union { |
| 10743 | struct { ///< |
| 10744 | UINT32 Enable:1 ; ///< |
| 10745 | UINT32 Prescale:2 ; ///< |
| 10746 | UINT32 BlackoutExempt:1 ; ///< |
| 10747 | UINT32 StallMode:2 ; ///< |
| 10748 | UINT32 StallOverride:1 ; ///< |
| 10749 | UINT32 MaxBurst:4 ; ///< |
| 10750 | UINT32 LazyTimer:4 ; ///< |
| 10751 | UINT32 StallOverrideWtm:1 ; ///< |
| 10752 | UINT32 Reserved_31_16:16; ///< |
| 10753 | } Field; ///< |
| 10754 | UINT32 Value; ///< |
| 10755 | } GMMx21A8_STRUCT; |
| 10756 | |
| 10757 | // **** GMMx21AC Register Definition **** |
| 10758 | // Address |
| 10759 | #define GMMx21AC_ADDRESS 0x21ac |
| 10760 | |
| 10761 | // Type |
| 10762 | #define GMMx21AC_TYPE TYPE_GMM |
| 10763 | // Field Data |
| 10764 | #define GMMx21AC_Enable_OFFSET 0 |
| 10765 | #define GMMx21AC_Enable_WIDTH 1 |
| 10766 | #define GMMx21AC_Enable_MASK 0x1 |
| 10767 | #define GMMx21AC_Prescale_OFFSET 1 |
| 10768 | #define GMMx21AC_Prescale_WIDTH 2 |
| 10769 | #define GMMx21AC_Prescale_MASK 0x6 |
| 10770 | #define GMMx21AC_BlackoutExempt_OFFSET 3 |
| 10771 | #define GMMx21AC_BlackoutExempt_WIDTH 1 |
| 10772 | #define GMMx21AC_BlackoutExempt_MASK 0x8 |
| 10773 | #define GMMx21AC_StallMode_OFFSET 4 |
| 10774 | #define GMMx21AC_StallMode_WIDTH 2 |
| 10775 | #define GMMx21AC_StallMode_MASK 0x30 |
| 10776 | #define GMMx21AC_StallOverride_OFFSET 6 |
| 10777 | #define GMMx21AC_StallOverride_WIDTH 1 |
| 10778 | #define GMMx21AC_StallOverride_MASK 0x40 |
| 10779 | #define GMMx21AC_MaxBurst_OFFSET 7 |
| 10780 | #define GMMx21AC_MaxBurst_WIDTH 4 |
| 10781 | #define GMMx21AC_MaxBurst_MASK 0x780 |
| 10782 | #define GMMx21AC_LazyTimer_OFFSET 11 |
| 10783 | #define GMMx21AC_LazyTimer_WIDTH 4 |
| 10784 | #define GMMx21AC_LazyTimer_MASK 0x7800 |
| 10785 | #define GMMx21AC_StallOverrideWtm_OFFSET 15 |
| 10786 | #define GMMx21AC_StallOverrideWtm_WIDTH 1 |
| 10787 | #define GMMx21AC_StallOverrideWtm_MASK 0x8000 |
| 10788 | #define GMMx21AC_Reserved_31_16_OFFSET 16 |
| 10789 | #define GMMx21AC_Reserved_31_16_WIDTH 16 |
| 10790 | #define GMMx21AC_Reserved_31_16_MASK 0xffff0000 |
| 10791 | |
| 10792 | /// GMMx21AC |
| 10793 | typedef union { |
| 10794 | struct { ///< |
| 10795 | UINT32 Enable:1 ; ///< |
| 10796 | UINT32 Prescale:2 ; ///< |
| 10797 | UINT32 BlackoutExempt:1 ; ///< |
| 10798 | UINT32 StallMode:2 ; ///< |
| 10799 | UINT32 StallOverride:1 ; ///< |
| 10800 | UINT32 MaxBurst:4 ; ///< |
| 10801 | UINT32 LazyTimer:4 ; ///< |
| 10802 | UINT32 StallOverrideWtm:1 ; ///< |
| 10803 | UINT32 Reserved_31_16:16; ///< |
| 10804 | } Field; ///< |
| 10805 | UINT32 Value; ///< |
| 10806 | } GMMx21AC_STRUCT; |
| 10807 | |
| 10808 | // **** GMMx21B0 Register Definition **** |
| 10809 | // Address |
| 10810 | #define GMMx21B0_ADDRESS 0x21b0 |
| 10811 | |
| 10812 | // Type |
| 10813 | #define GMMx21B0_TYPE TYPE_GMM |
| 10814 | // Field Data |
| 10815 | #define GMMx21B0_Enable_OFFSET 0 |
| 10816 | #define GMMx21B0_Enable_WIDTH 1 |
| 10817 | #define GMMx21B0_Enable_MASK 0x1 |
| 10818 | #define GMMx21B0_Prescale_OFFSET 1 |
| 10819 | #define GMMx21B0_Prescale_WIDTH 2 |
| 10820 | #define GMMx21B0_Prescale_MASK 0x6 |
| 10821 | #define GMMx21B0_BlackoutExempt_OFFSET 3 |
| 10822 | #define GMMx21B0_BlackoutExempt_WIDTH 1 |
| 10823 | #define GMMx21B0_BlackoutExempt_MASK 0x8 |
| 10824 | #define GMMx21B0_StallMode_OFFSET 4 |
| 10825 | #define GMMx21B0_StallMode_WIDTH 2 |
| 10826 | #define GMMx21B0_StallMode_MASK 0x30 |
| 10827 | #define GMMx21B0_StallOverride_OFFSET 6 |
| 10828 | #define GMMx21B0_StallOverride_WIDTH 1 |
| 10829 | #define GMMx21B0_StallOverride_MASK 0x40 |
| 10830 | #define GMMx21B0_MaxBurst_OFFSET 7 |
| 10831 | #define GMMx21B0_MaxBurst_WIDTH 4 |
| 10832 | #define GMMx21B0_MaxBurst_MASK 0x780 |
| 10833 | #define GMMx21B0_LazyTimer_OFFSET 11 |
| 10834 | #define GMMx21B0_LazyTimer_WIDTH 4 |
| 10835 | #define GMMx21B0_LazyTimer_MASK 0x7800 |
| 10836 | #define GMMx21B0_StallOverrideWtm_OFFSET 15 |
| 10837 | #define GMMx21B0_StallOverrideWtm_WIDTH 1 |
| 10838 | #define GMMx21B0_StallOverrideWtm_MASK 0x8000 |
| 10839 | #define GMMx21B0_Reserved_31_16_OFFSET 16 |
| 10840 | #define GMMx21B0_Reserved_31_16_WIDTH 16 |
| 10841 | #define GMMx21B0_Reserved_31_16_MASK 0xffff0000 |
| 10842 | |
| 10843 | /// GMMx21B0 |
| 10844 | typedef union { |
| 10845 | struct { ///< |
| 10846 | UINT32 Enable:1 ; ///< |
| 10847 | UINT32 Prescale:2 ; ///< |
| 10848 | UINT32 BlackoutExempt:1 ; ///< |
| 10849 | UINT32 StallMode:2 ; ///< |
| 10850 | UINT32 StallOverride:1 ; ///< |
| 10851 | UINT32 MaxBurst:4 ; ///< |
| 10852 | UINT32 LazyTimer:4 ; ///< |
| 10853 | UINT32 StallOverrideWtm:1 ; ///< |
| 10854 | UINT32 Reserved_31_16:16; ///< |
| 10855 | } Field; ///< |
| 10856 | UINT32 Value; ///< |
| 10857 | } GMMx21B0_STRUCT; |
| 10858 | |
| 10859 | // **** GMMx21B4 Register Definition **** |
| 10860 | // Address |
| 10861 | #define GMMx21B4_ADDRESS 0x21b4 |
| 10862 | |
| 10863 | // Type |
| 10864 | #define GMMx21B4_TYPE TYPE_GMM |
| 10865 | // Field Data |
| 10866 | #define GMMx21B4_Enable_OFFSET 0 |
| 10867 | #define GMMx21B4_Enable_WIDTH 1 |
| 10868 | #define GMMx21B4_Enable_MASK 0x1 |
| 10869 | #define GMMx21B4_Prescale_OFFSET 1 |
| 10870 | #define GMMx21B4_Prescale_WIDTH 2 |
| 10871 | #define GMMx21B4_Prescale_MASK 0x6 |
| 10872 | #define GMMx21B4_BlackoutExempt_OFFSET 3 |
| 10873 | #define GMMx21B4_BlackoutExempt_WIDTH 1 |
| 10874 | #define GMMx21B4_BlackoutExempt_MASK 0x8 |
| 10875 | #define GMMx21B4_StallMode_OFFSET 4 |
| 10876 | #define GMMx21B4_StallMode_WIDTH 2 |
| 10877 | #define GMMx21B4_StallMode_MASK 0x30 |
| 10878 | #define GMMx21B4_StallOverride_OFFSET 6 |
| 10879 | #define GMMx21B4_StallOverride_WIDTH 1 |
| 10880 | #define GMMx21B4_StallOverride_MASK 0x40 |
| 10881 | #define GMMx21B4_MaxBurst_OFFSET 7 |
| 10882 | #define GMMx21B4_MaxBurst_WIDTH 4 |
| 10883 | #define GMMx21B4_MaxBurst_MASK 0x780 |
| 10884 | #define GMMx21B4_LazyTimer_OFFSET 11 |
| 10885 | #define GMMx21B4_LazyTimer_WIDTH 4 |
| 10886 | #define GMMx21B4_LazyTimer_MASK 0x7800 |
| 10887 | #define GMMx21B4_StallOverrideWtm_OFFSET 15 |
| 10888 | #define GMMx21B4_StallOverrideWtm_WIDTH 1 |
| 10889 | #define GMMx21B4_StallOverrideWtm_MASK 0x8000 |
| 10890 | #define GMMx21B4_Reserved_31_16_OFFSET 16 |
| 10891 | #define GMMx21B4_Reserved_31_16_WIDTH 16 |
| 10892 | #define GMMx21B4_Reserved_31_16_MASK 0xffff0000 |
| 10893 | |
| 10894 | /// GMMx21B4 |
| 10895 | typedef union { |
| 10896 | struct { ///< |
| 10897 | UINT32 Enable:1 ; ///< |
| 10898 | UINT32 Prescale:2 ; ///< |
| 10899 | UINT32 BlackoutExempt:1 ; ///< |
| 10900 | UINT32 StallMode:2 ; ///< |
| 10901 | UINT32 StallOverride:1 ; ///< |
| 10902 | UINT32 MaxBurst:4 ; ///< |
| 10903 | UINT32 LazyTimer:4 ; ///< |
| 10904 | UINT32 StallOverrideWtm:1 ; ///< |
| 10905 | UINT32 Reserved_31_16:16; ///< |
| 10906 | } Field; ///< |
| 10907 | UINT32 Value; ///< |
| 10908 | } GMMx21B4_STRUCT; |
| 10909 | |
| 10910 | // **** GMMx21B8 Register Definition **** |
| 10911 | // Address |
| 10912 | #define GMMx21B8_ADDRESS 0x21b8 |
| 10913 | |
| 10914 | // Type |
| 10915 | #define GMMx21B8_TYPE TYPE_GMM |
| 10916 | // Field Data |
| 10917 | #define GMMx21B8_Enable_OFFSET 0 |
| 10918 | #define GMMx21B8_Enable_WIDTH 1 |
| 10919 | #define GMMx21B8_Enable_MASK 0x1 |
| 10920 | #define GMMx21B8_Prescale_OFFSET 1 |
| 10921 | #define GMMx21B8_Prescale_WIDTH 2 |
| 10922 | #define GMMx21B8_Prescale_MASK 0x6 |
| 10923 | #define GMMx21B8_BlackoutExempt_OFFSET 3 |
| 10924 | #define GMMx21B8_BlackoutExempt_WIDTH 1 |
| 10925 | #define GMMx21B8_BlackoutExempt_MASK 0x8 |
| 10926 | #define GMMx21B8_StallMode_OFFSET 4 |
| 10927 | #define GMMx21B8_StallMode_WIDTH 2 |
| 10928 | #define GMMx21B8_StallMode_MASK 0x30 |
| 10929 | #define GMMx21B8_StallOverride_OFFSET 6 |
| 10930 | #define GMMx21B8_StallOverride_WIDTH 1 |
| 10931 | #define GMMx21B8_StallOverride_MASK 0x40 |
| 10932 | #define GMMx21B8_MaxBurst_OFFSET 7 |
| 10933 | #define GMMx21B8_MaxBurst_WIDTH 4 |
| 10934 | #define GMMx21B8_MaxBurst_MASK 0x780 |
| 10935 | #define GMMx21B8_LazyTimer_OFFSET 11 |
| 10936 | #define GMMx21B8_LazyTimer_WIDTH 4 |
| 10937 | #define GMMx21B8_LazyTimer_MASK 0x7800 |
| 10938 | #define GMMx21B8_StallOverrideWtm_OFFSET 15 |
| 10939 | #define GMMx21B8_StallOverrideWtm_WIDTH 1 |
| 10940 | #define GMMx21B8_StallOverrideWtm_MASK 0x8000 |
| 10941 | #define GMMx21B8_Reserved_31_16_OFFSET 16 |
| 10942 | #define GMMx21B8_Reserved_31_16_WIDTH 16 |
| 10943 | #define GMMx21B8_Reserved_31_16_MASK 0xffff0000 |
| 10944 | |
| 10945 | /// GMMx21B8 |
| 10946 | typedef union { |
| 10947 | struct { ///< |
| 10948 | UINT32 Enable:1 ; ///< |
| 10949 | UINT32 Prescale:2 ; ///< |
| 10950 | UINT32 BlackoutExempt:1 ; ///< |
| 10951 | UINT32 StallMode:2 ; ///< |
| 10952 | UINT32 StallOverride:1 ; ///< |
| 10953 | UINT32 MaxBurst:4 ; ///< |
| 10954 | UINT32 LazyTimer:4 ; ///< |
| 10955 | UINT32 StallOverrideWtm:1 ; ///< |
| 10956 | UINT32 Reserved_31_16:16; ///< |
| 10957 | } Field; ///< |
| 10958 | UINT32 Value; ///< |
| 10959 | } GMMx21B8_STRUCT; |
| 10960 | |
| 10961 | // **** GMMx21BC Register Definition **** |
| 10962 | // Address |
| 10963 | #define GMMx21BC_ADDRESS 0x21bc |
| 10964 | |
| 10965 | // Type |
| 10966 | #define GMMx21BC_TYPE TYPE_GMM |
| 10967 | // Field Data |
| 10968 | #define GMMx21BC_Enable_OFFSET 0 |
| 10969 | #define GMMx21BC_Enable_WIDTH 1 |
| 10970 | #define GMMx21BC_Enable_MASK 0x1 |
| 10971 | #define GMMx21BC_Prescale_OFFSET 1 |
| 10972 | #define GMMx21BC_Prescale_WIDTH 2 |
| 10973 | #define GMMx21BC_Prescale_MASK 0x6 |
| 10974 | #define GMMx21BC_BlackoutExempt_OFFSET 3 |
| 10975 | #define GMMx21BC_BlackoutExempt_WIDTH 1 |
| 10976 | #define GMMx21BC_BlackoutExempt_MASK 0x8 |
| 10977 | #define GMMx21BC_StallMode_OFFSET 4 |
| 10978 | #define GMMx21BC_StallMode_WIDTH 2 |
| 10979 | #define GMMx21BC_StallMode_MASK 0x30 |
| 10980 | #define GMMx21BC_StallOverride_OFFSET 6 |
| 10981 | #define GMMx21BC_StallOverride_WIDTH 1 |
| 10982 | #define GMMx21BC_StallOverride_MASK 0x40 |
| 10983 | #define GMMx21BC_MaxBurst_OFFSET 7 |
| 10984 | #define GMMx21BC_MaxBurst_WIDTH 4 |
| 10985 | #define GMMx21BC_MaxBurst_MASK 0x780 |
| 10986 | #define GMMx21BC_LazyTimer_OFFSET 11 |
| 10987 | #define GMMx21BC_LazyTimer_WIDTH 4 |
| 10988 | #define GMMx21BC_LazyTimer_MASK 0x7800 |
| 10989 | #define GMMx21BC_StallOverrideWtm_OFFSET 15 |
| 10990 | #define GMMx21BC_StallOverrideWtm_WIDTH 1 |
| 10991 | #define GMMx21BC_StallOverrideWtm_MASK 0x8000 |
| 10992 | #define GMMx21BC_Reserved_31_16_OFFSET 16 |
| 10993 | #define GMMx21BC_Reserved_31_16_WIDTH 16 |
| 10994 | #define GMMx21BC_Reserved_31_16_MASK 0xffff0000 |
| 10995 | |
| 10996 | /// GMMx21BC |
| 10997 | typedef union { |
| 10998 | struct { ///< |
| 10999 | UINT32 Enable:1 ; ///< |
| 11000 | UINT32 Prescale:2 ; ///< |
| 11001 | UINT32 BlackoutExempt:1 ; ///< |
| 11002 | UINT32 StallMode:2 ; ///< |
| 11003 | UINT32 StallOverride:1 ; ///< |
| 11004 | UINT32 MaxBurst:4 ; ///< |
| 11005 | UINT32 LazyTimer:4 ; ///< |
| 11006 | UINT32 StallOverrideWtm:1 ; ///< |
| 11007 | UINT32 Reserved_31_16:16; ///< |
| 11008 | } Field; ///< |
| 11009 | UINT32 Value; ///< |
| 11010 | } GMMx21BC_STRUCT; |
| 11011 | |
| 11012 | // **** GMMx21C0 Register Definition **** |
| 11013 | // Address |
| 11014 | #define GMMx21C0_ADDRESS 0x21c0 |
| 11015 | |
| 11016 | // Type |
| 11017 | #define GMMx21C0_TYPE TYPE_GMM |
| 11018 | // Field Data |
| 11019 | #define GMMx21C0_Enable_OFFSET 0 |
| 11020 | #define GMMx21C0_Enable_WIDTH 1 |
| 11021 | #define GMMx21C0_Enable_MASK 0x1 |
| 11022 | #define GMMx21C0_Prescale_OFFSET 1 |
| 11023 | #define GMMx21C0_Prescale_WIDTH 2 |
| 11024 | #define GMMx21C0_Prescale_MASK 0x6 |
| 11025 | #define GMMx21C0_BlackoutExempt_OFFSET 3 |
| 11026 | #define GMMx21C0_BlackoutExempt_WIDTH 1 |
| 11027 | #define GMMx21C0_BlackoutExempt_MASK 0x8 |
| 11028 | #define GMMx21C0_StallMode_OFFSET 4 |
| 11029 | #define GMMx21C0_StallMode_WIDTH 2 |
| 11030 | #define GMMx21C0_StallMode_MASK 0x30 |
| 11031 | #define GMMx21C0_StallOverride_OFFSET 6 |
| 11032 | #define GMMx21C0_StallOverride_WIDTH 1 |
| 11033 | #define GMMx21C0_StallOverride_MASK 0x40 |
| 11034 | #define GMMx21C0_MaxBurst_OFFSET 7 |
| 11035 | #define GMMx21C0_MaxBurst_WIDTH 4 |
| 11036 | #define GMMx21C0_MaxBurst_MASK 0x780 |
| 11037 | #define GMMx21C0_LazyTimer_OFFSET 11 |
| 11038 | #define GMMx21C0_LazyTimer_WIDTH 4 |
| 11039 | #define GMMx21C0_LazyTimer_MASK 0x7800 |
| 11040 | #define GMMx21C0_StallOverrideWtm_OFFSET 15 |
| 11041 | #define GMMx21C0_StallOverrideWtm_WIDTH 1 |
| 11042 | #define GMMx21C0_StallOverrideWtm_MASK 0x8000 |
| 11043 | #define GMMx21C0_Reserved_31_16_OFFSET 16 |
| 11044 | #define GMMx21C0_Reserved_31_16_WIDTH 16 |
| 11045 | #define GMMx21C0_Reserved_31_16_MASK 0xffff0000 |
| 11046 | |
| 11047 | /// GMMx21C0 |
| 11048 | typedef union { |
| 11049 | struct { ///< |
| 11050 | UINT32 Enable:1 ; ///< |
| 11051 | UINT32 Prescale:2 ; ///< |
| 11052 | UINT32 BlackoutExempt:1 ; ///< |
| 11053 | UINT32 StallMode:2 ; ///< |
| 11054 | UINT32 StallOverride:1 ; ///< |
| 11055 | UINT32 MaxBurst:4 ; ///< |
| 11056 | UINT32 LazyTimer:4 ; ///< |
| 11057 | UINT32 StallOverrideWtm:1 ; ///< |
| 11058 | UINT32 Reserved_31_16:16; ///< |
| 11059 | } Field; ///< |
| 11060 | UINT32 Value; ///< |
| 11061 | } GMMx21C0_STRUCT; |
| 11062 | |
| 11063 | // **** GMMx21C4 Register Definition **** |
| 11064 | // Address |
| 11065 | #define GMMx21C4_ADDRESS 0x21c4 |
| 11066 | |
| 11067 | // Type |
| 11068 | #define GMMx21C4_TYPE TYPE_GMM |
| 11069 | // Field Data |
| 11070 | #define GMMx21C4_Enable_OFFSET 0 |
| 11071 | #define GMMx21C4_Enable_WIDTH 1 |
| 11072 | #define GMMx21C4_Enable_MASK 0x1 |
| 11073 | #define GMMx21C4_Prescale_OFFSET 1 |
| 11074 | #define GMMx21C4_Prescale_WIDTH 2 |
| 11075 | #define GMMx21C4_Prescale_MASK 0x6 |
| 11076 | #define GMMx21C4_BlackoutExempt_OFFSET 3 |
| 11077 | #define GMMx21C4_BlackoutExempt_WIDTH 1 |
| 11078 | #define GMMx21C4_BlackoutExempt_MASK 0x8 |
| 11079 | #define GMMx21C4_StallMode_OFFSET 4 |
| 11080 | #define GMMx21C4_StallMode_WIDTH 2 |
| 11081 | #define GMMx21C4_StallMode_MASK 0x30 |
| 11082 | #define GMMx21C4_StallOverride_OFFSET 6 |
| 11083 | #define GMMx21C4_StallOverride_WIDTH 1 |
| 11084 | #define GMMx21C4_StallOverride_MASK 0x40 |
| 11085 | #define GMMx21C4_MaxBurst_OFFSET 7 |
| 11086 | #define GMMx21C4_MaxBurst_WIDTH 4 |
| 11087 | #define GMMx21C4_MaxBurst_MASK 0x780 |
| 11088 | #define GMMx21C4_LazyTimer_OFFSET 11 |
| 11089 | #define GMMx21C4_LazyTimer_WIDTH 4 |
| 11090 | #define GMMx21C4_LazyTimer_MASK 0x7800 |
| 11091 | #define GMMx21C4_StallOverrideWtm_OFFSET 15 |
| 11092 | #define GMMx21C4_StallOverrideWtm_WIDTH 1 |
| 11093 | #define GMMx21C4_StallOverrideWtm_MASK 0x8000 |
| 11094 | #define GMMx21C4_Reserved_31_16_OFFSET 16 |
| 11095 | #define GMMx21C4_Reserved_31_16_WIDTH 16 |
| 11096 | #define GMMx21C4_Reserved_31_16_MASK 0xffff0000 |
| 11097 | |
| 11098 | /// GMMx21C4 |
| 11099 | typedef union { |
| 11100 | struct { ///< |
| 11101 | UINT32 Enable:1 ; ///< |
| 11102 | UINT32 Prescale:2 ; ///< |
| 11103 | UINT32 BlackoutExempt:1 ; ///< |
| 11104 | UINT32 StallMode:2 ; ///< |
| 11105 | UINT32 StallOverride:1 ; ///< |
| 11106 | UINT32 MaxBurst:4 ; ///< |
| 11107 | UINT32 LazyTimer:4 ; ///< |
| 11108 | UINT32 StallOverrideWtm:1 ; ///< |
| 11109 | UINT32 Reserved_31_16:16; ///< |
| 11110 | } Field; ///< |
| 11111 | UINT32 Value; ///< |
| 11112 | } GMMx21C4_STRUCT; |
| 11113 | |
| 11114 | // **** GMMx21C8 Register Definition **** |
| 11115 | // Address |
| 11116 | #define GMMx21C8_ADDRESS 0x21c8 |
| 11117 | |
| 11118 | // Type |
| 11119 | #define GMMx21C8_TYPE TYPE_GMM |
| 11120 | // Field Data |
| 11121 | #define GMMx21C8_Enable_OFFSET 0 |
| 11122 | #define GMMx21C8_Enable_WIDTH 1 |
| 11123 | #define GMMx21C8_Enable_MASK 0x1 |
| 11124 | #define GMMx21C8_Prescale_OFFSET 1 |
| 11125 | #define GMMx21C8_Prescale_WIDTH 2 |
| 11126 | #define GMMx21C8_Prescale_MASK 0x6 |
| 11127 | #define GMMx21C8_BlackoutExempt_OFFSET 3 |
| 11128 | #define GMMx21C8_BlackoutExempt_WIDTH 1 |
| 11129 | #define GMMx21C8_BlackoutExempt_MASK 0x8 |
| 11130 | #define GMMx21C8_StallMode_OFFSET 4 |
| 11131 | #define GMMx21C8_StallMode_WIDTH 2 |
| 11132 | #define GMMx21C8_StallMode_MASK 0x30 |
| 11133 | #define GMMx21C8_StallOverride_OFFSET 6 |
| 11134 | #define GMMx21C8_StallOverride_WIDTH 1 |
| 11135 | #define GMMx21C8_StallOverride_MASK 0x40 |
| 11136 | #define GMMx21C8_MaxBurst_OFFSET 7 |
| 11137 | #define GMMx21C8_MaxBurst_WIDTH 4 |
| 11138 | #define GMMx21C8_MaxBurst_MASK 0x780 |
| 11139 | #define GMMx21C8_LazyTimer_OFFSET 11 |
| 11140 | #define GMMx21C8_LazyTimer_WIDTH 4 |
| 11141 | #define GMMx21C8_LazyTimer_MASK 0x7800 |
| 11142 | #define GMMx21C8_StallOverrideWtm_OFFSET 15 |
| 11143 | #define GMMx21C8_StallOverrideWtm_WIDTH 1 |
| 11144 | #define GMMx21C8_StallOverrideWtm_MASK 0x8000 |
| 11145 | #define GMMx21C8_Reserved_31_16_OFFSET 16 |
| 11146 | #define GMMx21C8_Reserved_31_16_WIDTH 16 |
| 11147 | #define GMMx21C8_Reserved_31_16_MASK 0xffff0000 |
| 11148 | |
| 11149 | /// GMMx21C8 |
| 11150 | typedef union { |
| 11151 | struct { ///< |
| 11152 | UINT32 Enable:1 ; ///< |
| 11153 | UINT32 Prescale:2 ; ///< |
| 11154 | UINT32 BlackoutExempt:1 ; ///< |
| 11155 | UINT32 StallMode:2 ; ///< |
| 11156 | UINT32 StallOverride:1 ; ///< |
| 11157 | UINT32 MaxBurst:4 ; ///< |
| 11158 | UINT32 LazyTimer:4 ; ///< |
| 11159 | UINT32 StallOverrideWtm:1 ; ///< |
| 11160 | UINT32 Reserved_31_16:16; ///< |
| 11161 | } Field; ///< |
| 11162 | UINT32 Value; ///< |
| 11163 | } GMMx21C8_STRUCT; |
| 11164 | |
| 11165 | // **** GMMx21CC Register Definition **** |
| 11166 | // Address |
| 11167 | #define GMMx21CC_ADDRESS 0x21cc |
| 11168 | |
| 11169 | // Type |
| 11170 | #define GMMx21CC_TYPE TYPE_GMM |
| 11171 | // Field Data |
| 11172 | #define GMMx21CC_Enable_OFFSET 0 |
| 11173 | #define GMMx21CC_Enable_WIDTH 1 |
| 11174 | #define GMMx21CC_Enable_MASK 0x1 |
| 11175 | #define GMMx21CC_Prescale_OFFSET 1 |
| 11176 | #define GMMx21CC_Prescale_WIDTH 2 |
| 11177 | #define GMMx21CC_Prescale_MASK 0x6 |
| 11178 | #define GMMx21CC_BlackoutExempt_OFFSET 3 |
| 11179 | #define GMMx21CC_BlackoutExempt_WIDTH 1 |
| 11180 | #define GMMx21CC_BlackoutExempt_MASK 0x8 |
| 11181 | #define GMMx21CC_StallMode_OFFSET 4 |
| 11182 | #define GMMx21CC_StallMode_WIDTH 2 |
| 11183 | #define GMMx21CC_StallMode_MASK 0x30 |
| 11184 | #define GMMx21CC_StallOverride_OFFSET 6 |
| 11185 | #define GMMx21CC_StallOverride_WIDTH 1 |
| 11186 | #define GMMx21CC_StallOverride_MASK 0x40 |
| 11187 | #define GMMx21CC_MaxBurst_OFFSET 7 |
| 11188 | #define GMMx21CC_MaxBurst_WIDTH 4 |
| 11189 | #define GMMx21CC_MaxBurst_MASK 0x780 |
| 11190 | #define GMMx21CC_LazyTimer_OFFSET 11 |
| 11191 | #define GMMx21CC_LazyTimer_WIDTH 4 |
| 11192 | #define GMMx21CC_LazyTimer_MASK 0x7800 |
| 11193 | #define GMMx21CC_StallOverrideWtm_OFFSET 15 |
| 11194 | #define GMMx21CC_StallOverrideWtm_WIDTH 1 |
| 11195 | #define GMMx21CC_StallOverrideWtm_MASK 0x8000 |
| 11196 | #define GMMx21CC_Reserved_31_16_OFFSET 16 |
| 11197 | #define GMMx21CC_Reserved_31_16_WIDTH 16 |
| 11198 | #define GMMx21CC_Reserved_31_16_MASK 0xffff0000 |
| 11199 | |
| 11200 | /// GMMx21CC |
| 11201 | typedef union { |
| 11202 | struct { ///< |
| 11203 | UINT32 Enable:1 ; ///< |
| 11204 | UINT32 Prescale:2 ; ///< |
| 11205 | UINT32 BlackoutExempt:1 ; ///< |
| 11206 | UINT32 StallMode:2 ; ///< |
| 11207 | UINT32 StallOverride:1 ; ///< |
| 11208 | UINT32 MaxBurst:4 ; ///< |
| 11209 | UINT32 LazyTimer:4 ; ///< |
| 11210 | UINT32 StallOverrideWtm:1 ; ///< |
| 11211 | UINT32 Reserved_31_16:16; ///< |
| 11212 | } Field; ///< |
| 11213 | UINT32 Value; ///< |
| 11214 | } GMMx21CC_STRUCT; |
| 11215 | |
| 11216 | // **** GMMx21D0 Register Definition **** |
| 11217 | // Address |
| 11218 | #define GMMx21D0_ADDRESS 0x21d0 |
| 11219 | |
| 11220 | // Type |
| 11221 | #define GMMx21D0_TYPE TYPE_GMM |
| 11222 | // Field Data |
| 11223 | #define GMMx21D0_Enable_OFFSET 0 |
| 11224 | #define GMMx21D0_Enable_WIDTH 1 |
| 11225 | #define GMMx21D0_Enable_MASK 0x1 |
| 11226 | #define GMMx21D0_Prescale_OFFSET 1 |
| 11227 | #define GMMx21D0_Prescale_WIDTH 2 |
| 11228 | #define GMMx21D0_Prescale_MASK 0x6 |
| 11229 | #define GMMx21D0_BlackoutExempt_OFFSET 3 |
| 11230 | #define GMMx21D0_BlackoutExempt_WIDTH 1 |
| 11231 | #define GMMx21D0_BlackoutExempt_MASK 0x8 |
| 11232 | #define GMMx21D0_StallMode_OFFSET 4 |
| 11233 | #define GMMx21D0_StallMode_WIDTH 2 |
| 11234 | #define GMMx21D0_StallMode_MASK 0x30 |
| 11235 | #define GMMx21D0_StallOverride_OFFSET 6 |
| 11236 | #define GMMx21D0_StallOverride_WIDTH 1 |
| 11237 | #define GMMx21D0_StallOverride_MASK 0x40 |
| 11238 | #define GMMx21D0_MaxBurst_OFFSET 7 |
| 11239 | #define GMMx21D0_MaxBurst_WIDTH 4 |
| 11240 | #define GMMx21D0_MaxBurst_MASK 0x780 |
| 11241 | #define GMMx21D0_LazyTimer_OFFSET 11 |
| 11242 | #define GMMx21D0_LazyTimer_WIDTH 4 |
| 11243 | #define GMMx21D0_LazyTimer_MASK 0x7800 |
| 11244 | #define GMMx21D0_StallOverrideWtm_OFFSET 15 |
| 11245 | #define GMMx21D0_StallOverrideWtm_WIDTH 1 |
| 11246 | #define GMMx21D0_StallOverrideWtm_MASK 0x8000 |
| 11247 | #define GMMx21D0_Reserved_31_16_OFFSET 16 |
| 11248 | #define GMMx21D0_Reserved_31_16_WIDTH 16 |
| 11249 | #define GMMx21D0_Reserved_31_16_MASK 0xffff0000 |
| 11250 | |
| 11251 | /// GMMx21D0 |
| 11252 | typedef union { |
| 11253 | struct { ///< |
| 11254 | UINT32 Enable:1 ; ///< |
| 11255 | UINT32 Prescale:2 ; ///< |
| 11256 | UINT32 BlackoutExempt:1 ; ///< |
| 11257 | UINT32 StallMode:2 ; ///< |
| 11258 | UINT32 StallOverride:1 ; ///< |
| 11259 | UINT32 MaxBurst:4 ; ///< |
| 11260 | UINT32 LazyTimer:4 ; ///< |
| 11261 | UINT32 StallOverrideWtm:1 ; ///< |
| 11262 | UINT32 Reserved_31_16:16; ///< |
| 11263 | } Field; ///< |
| 11264 | UINT32 Value; ///< |
| 11265 | } GMMx21D0_STRUCT; |
| 11266 | |
| 11267 | // **** GMMx25C0 Register Definition **** |
| 11268 | // Address |
| 11269 | #define GMMx25C0_ADDRESS 0x25c0 |
| 11270 | |
| 11271 | // Type |
| 11272 | #define GMMx25C0_TYPE TYPE_GMM |
| 11273 | // Field Data |
| 11274 | #define GMMx25C0_BlackoutRd_OFFSET 0 |
| 11275 | #define GMMx25C0_BlackoutRd_WIDTH 1 |
| 11276 | #define GMMx25C0_BlackoutRd_MASK 0x1 |
| 11277 | #define GMMx25C0_BlackoutWr_OFFSET 1 |
| 11278 | #define GMMx25C0_BlackoutWr_WIDTH 1 |
| 11279 | #define GMMx25C0_BlackoutWr_MASK 0x2 |
| 11280 | #define GMMx25C0_Reserved_31_2_OFFSET 2 |
| 11281 | #define GMMx25C0_Reserved_31_2_WIDTH 30 |
| 11282 | #define GMMx25C0_Reserved_31_2_MASK 0xfffffffc |
| 11283 | |
| 11284 | /// GMMx25C0 |
| 11285 | typedef union { |
| 11286 | struct { ///< |
| 11287 | UINT32 BlackoutRd:1 ; ///< |
| 11288 | UINT32 BlackoutWr:1 ; ///< |
| 11289 | UINT32 Reserved_31_2:30; ///< |
| 11290 | } Field; ///< |
| 11291 | UINT32 Value; ///< |
| 11292 | } GMMx25C0_STRUCT; |
| 11293 | |
| 11294 | // **** GMMx25C8 Register Definition **** |
| 11295 | // Address |
| 11296 | #define GMMx25C8_ADDRESS 0x25c8 |
| 11297 | |
| 11298 | // Type |
| 11299 | #define GMMx25C8_TYPE TYPE_GMM |
| 11300 | // Field Data |
| 11301 | #define GMMx25C8_ReadLcl_OFFSET 0 |
| 11302 | #define GMMx25C8_ReadLcl_WIDTH 8 |
| 11303 | #define GMMx25C8_ReadLcl_MASK 0xff |
| 11304 | #define GMMx25C8_ReadHub_OFFSET 8 |
| 11305 | #define GMMx25C8_ReadHub_WIDTH 8 |
| 11306 | #define GMMx25C8_ReadHub_MASK 0xff00 |
| 11307 | #define GMMx25C8_ReadPri_OFFSET 16 |
| 11308 | #define GMMx25C8_ReadPri_WIDTH 8 |
| 11309 | #define GMMx25C8_ReadPri_MASK 0xff0000 |
| 11310 | #define GMMx25C8_LclPri_OFFSET 24 |
| 11311 | #define GMMx25C8_LclPri_WIDTH 1 |
| 11312 | #define GMMx25C8_LclPri_MASK 0x1000000 |
| 11313 | #define GMMx25C8_HubPri_OFFSET 25 |
| 11314 | #define GMMx25C8_HubPri_WIDTH 1 |
| 11315 | #define GMMx25C8_HubPri_MASK 0x2000000 |
| 11316 | #define GMMx25C8_Reserved_31_26_OFFSET 26 |
| 11317 | #define GMMx25C8_Reserved_31_26_WIDTH 6 |
| 11318 | #define GMMx25C8_Reserved_31_26_MASK 0xfc000000 |
| 11319 | |
| 11320 | /// GMMx25C8 |
| 11321 | typedef union { |
| 11322 | struct { ///< |
| 11323 | UINT32 ReadLcl:8 ; ///< |
| 11324 | UINT32 ReadHub:8 ; ///< |
| 11325 | UINT32 ReadPri:8 ; ///< |
| 11326 | UINT32 LclPri:1 ; ///< |
| 11327 | UINT32 HubPri:1 ; ///< |
| 11328 | UINT32 Reserved_31_26:6 ; ///< |
| 11329 | } Field; ///< |
| 11330 | UINT32 Value; ///< |
| 11331 | } GMMx25C8_STRUCT; |
| 11332 | |
| 11333 | // **** GMMx25CC Register Definition **** |
| 11334 | // Address |
| 11335 | #define GMMx25CC_ADDRESS 0x25cc |
| 11336 | |
| 11337 | // Type |
| 11338 | #define GMMx25CC_TYPE TYPE_GMM |
| 11339 | // Field Data |
| 11340 | #define GMMx25CC_WriteLcl_OFFSET 0 |
| 11341 | #define GMMx25CC_WriteLcl_WIDTH 8 |
| 11342 | #define GMMx25CC_WriteLcl_MASK 0xff |
| 11343 | #define GMMx25CC_WriteHub_OFFSET 8 |
| 11344 | #define GMMx25CC_WriteHub_WIDTH 8 |
| 11345 | #define GMMx25CC_WriteHub_MASK 0xff00 |
| 11346 | #define GMMx25CC_HubPri_OFFSET 16 |
| 11347 | #define GMMx25CC_HubPri_WIDTH 1 |
| 11348 | #define GMMx25CC_HubPri_MASK 0x10000 |
| 11349 | #define GMMx25CC_Reserved_31_17_OFFSET 17 |
| 11350 | #define GMMx25CC_Reserved_31_17_WIDTH 15 |
| 11351 | #define GMMx25CC_Reserved_31_17_MASK 0xfffe0000 |
| 11352 | |
| 11353 | /// GMMx25CC |
| 11354 | typedef union { |
| 11355 | struct { ///< |
| 11356 | UINT32 WriteLcl:8 ; ///< |
| 11357 | UINT32 WriteHub:8 ; ///< |
| 11358 | UINT32 HubPri:1 ; ///< |
| 11359 | UINT32 Reserved_31_17:15; ///< |
| 11360 | } Field; ///< |
| 11361 | UINT32 Value; ///< |
| 11362 | } GMMx25CC_STRUCT; |
| 11363 | |
| 11364 | // **** GMMx2610 Register Definition **** |
| 11365 | // Address |
| 11366 | #define GMMx2610_ADDRESS 0x2610 |
| 11367 | |
| 11368 | // Type |
| 11369 | #define GMMx2610_TYPE TYPE_GMM |
| 11370 | // Field Data |
| 11371 | #define GMMx2610_TctFetch0_OFFSET 0 |
| 11372 | #define GMMx2610_TctFetch0_WIDTH 4 |
| 11373 | #define GMMx2610_TctFetch0_MASK 0xf |
| 11374 | #define GMMx2610_TcvFetch0_OFFSET 4 |
| 11375 | #define GMMx2610_TcvFetch0_WIDTH 4 |
| 11376 | #define GMMx2610_TcvFetch0_MASK 0xf0 |
| 11377 | #define GMMx2610_Vc0_OFFSET 8 |
| 11378 | #define GMMx2610_Vc0_WIDTH 4 |
| 11379 | #define GMMx2610_Vc0_MASK 0xf00 |
| 11380 | #define GMMx2610_Cb0_OFFSET 12 |
| 11381 | #define GMMx2610_Cb0_WIDTH 4 |
| 11382 | #define GMMx2610_Cb0_MASK 0xf000 |
| 11383 | #define GMMx2610_CbcMask0_OFFSET 16 |
| 11384 | #define GMMx2610_CbcMask0_WIDTH 4 |
| 11385 | #define GMMx2610_CbcMask0_MASK 0xf0000 |
| 11386 | #define GMMx2610_CbfMask0_OFFSET 20 |
| 11387 | #define GMMx2610_CbfMask0_WIDTH 4 |
| 11388 | #define GMMx2610_CbfMask0_MASK 0xf00000 |
| 11389 | #define GMMx2610_Db0_OFFSET 24 |
| 11390 | #define GMMx2610_Db0_WIDTH 4 |
| 11391 | #define GMMx2610_Db0_MASK 0xf000000 |
| 11392 | #define GMMx2610_DbhTile0_OFFSET 28 |
| 11393 | #define GMMx2610_DbhTile0_WIDTH 4 |
| 11394 | #define GMMx2610_DbhTile0_MASK 0xf0000000 |
| 11395 | |
| 11396 | /// GMMx2610 |
| 11397 | typedef union { |
| 11398 | struct { ///< |
| 11399 | UINT32 TctFetch0:4 ; ///< |
| 11400 | UINT32 TcvFetch0:4 ; ///< |
| 11401 | UINT32 Vc0:4 ; ///< |
| 11402 | UINT32 Cb0:4 ; ///< |
| 11403 | UINT32 CbcMask0:4 ; ///< |
| 11404 | UINT32 CbfMask0:4 ; ///< |
| 11405 | UINT32 Db0:4 ; ///< |
| 11406 | UINT32 DbhTile0:4 ; ///< |
| 11407 | } Field; ///< |
| 11408 | UINT32 Value; ///< |
| 11409 | } GMMx2610_STRUCT; |
| 11410 | |
| 11411 | // **** GMMx2614 Register Definition **** |
| 11412 | // Address |
| 11413 | #define GMMx2614_ADDRESS 0x2614 |
| 11414 | |
| 11415 | // Type |
| 11416 | #define GMMx2614_TYPE TYPE_GMM |
| 11417 | // Field Data |
| 11418 | #define GMMx2614_Cb0_OFFSET 0 |
| 11419 | #define GMMx2614_Cb0_WIDTH 4 |
| 11420 | #define GMMx2614_Cb0_MASK 0xf |
| 11421 | #define GMMx2614_CbcMask0_OFFSET 4 |
| 11422 | #define GMMx2614_CbcMask0_WIDTH 4 |
| 11423 | #define GMMx2614_CbcMask0_MASK 0xf0 |
| 11424 | #define GMMx2614_CbfMask0_OFFSET 8 |
| 11425 | #define GMMx2614_CbfMask0_WIDTH 4 |
| 11426 | #define GMMx2614_CbfMask0_MASK 0xf00 |
| 11427 | #define GMMx2614_Db0_OFFSET 12 |
| 11428 | #define GMMx2614_Db0_WIDTH 4 |
| 11429 | #define GMMx2614_Db0_MASK 0xf000 |
| 11430 | #define GMMx2614_DbhTile0_OFFSET 16 |
| 11431 | #define GMMx2614_DbhTile0_WIDTH 4 |
| 11432 | #define GMMx2614_DbhTile0_MASK 0xf0000 |
| 11433 | #define GMMx2614_Sx0_OFFSET 20 |
| 11434 | #define GMMx2614_Sx0_WIDTH 4 |
| 11435 | #define GMMx2614_Sx0_MASK 0xf00000 |
| 11436 | #define GMMx2614_Bcast0_OFFSET 24 |
| 11437 | #define GMMx2614_Bcast0_WIDTH 4 |
| 11438 | #define GMMx2614_Bcast0_MASK 0xf000000 |
| 11439 | #define GMMx2614_Cbimmed0_OFFSET 28 |
| 11440 | #define GMMx2614_Cbimmed0_WIDTH 4 |
| 11441 | #define GMMx2614_Cbimmed0_MASK 0xf0000000 |
| 11442 | |
| 11443 | /// GMMx2614 |
| 11444 | typedef union { |
| 11445 | struct { ///< |
| 11446 | UINT32 Cb0:4 ; ///< |
| 11447 | UINT32 CbcMask0:4 ; ///< |
| 11448 | UINT32 CbfMask0:4 ; ///< |
| 11449 | UINT32 Db0:4 ; ///< |
| 11450 | UINT32 DbhTile0:4 ; ///< |
| 11451 | UINT32 Sx0:4 ; ///< |
| 11452 | UINT32 Bcast0:4 ; ///< |
| 11453 | UINT32 Cbimmed0:4 ; ///< |
| 11454 | } Field; ///< |
| 11455 | UINT32 Value; ///< |
| 11456 | } GMMx2614_STRUCT; |
| 11457 | |
| 11458 | // **** GMMx2618 Register Definition **** |
| 11459 | // Address |
| 11460 | #define GMMx2618_ADDRESS 0x2618 |
| 11461 | |
| 11462 | // Type |
| 11463 | #define GMMx2618_TYPE TYPE_GMM |
| 11464 | // Field Data |
| 11465 | #define GMMx2618_DbstEn0_OFFSET 0 |
| 11466 | #define GMMx2618_DbstEn0_WIDTH 4 |
| 11467 | #define GMMx2618_DbstEn0_MASK 0xf |
| 11468 | #define GMMx2618_TcvFetch1_OFFSET 4 |
| 11469 | #define GMMx2618_TcvFetch1_WIDTH 4 |
| 11470 | #define GMMx2618_TcvFetch1_MASK 0xf0 |
| 11471 | #define GMMx2618_TctFetch1_OFFSET 8 |
| 11472 | #define GMMx2618_TctFetch1_WIDTH 4 |
| 11473 | #define GMMx2618_TctFetch1_MASK 0xf00 |
| 11474 | #define GMMx2618_Vc1_OFFSET 12 |
| 11475 | #define GMMx2618_Vc1_WIDTH 4 |
| 11476 | #define GMMx2618_Vc1_MASK 0xf000 |
| 11477 | #define GMMx2618_Reserved_31_16_OFFSET 16 |
| 11478 | #define GMMx2618_Reserved_31_16_WIDTH 16 |
| 11479 | #define GMMx2618_Reserved_31_16_MASK 0xffff0000 |
| 11480 | |
| 11481 | /// GMMx2618 |
| 11482 | typedef union { |
| 11483 | struct { ///< |
| 11484 | UINT32 DbstEn0:4 ; ///< |
| 11485 | UINT32 TcvFetch1:4 ; ///< |
| 11486 | UINT32 TctFetch1:4 ; ///< |
| 11487 | UINT32 Vc1:4 ; ///< |
| 11488 | UINT32 Reserved_31_16:16; ///< |
| 11489 | } Field; ///< |
| 11490 | UINT32 Value; ///< |
| 11491 | } GMMx2618_STRUCT; |
| 11492 | |
| 11493 | // **** GMMx261C Register Definition **** |
| 11494 | // Address |
| 11495 | #define GMMx261C_ADDRESS 0x261c |
| 11496 | |
| 11497 | // Type |
| 11498 | #define GMMx261C_TYPE TYPE_GMM |
| 11499 | // Field Data |
| 11500 | #define GMMx261C_DbstEn0_OFFSET 0 |
| 11501 | #define GMMx261C_DbstEn0_WIDTH 4 |
| 11502 | #define GMMx261C_DbstEn0_MASK 0xf |
| 11503 | #define GMMx261C_Reserved_31_4_OFFSET 4 |
| 11504 | #define GMMx261C_Reserved_31_4_WIDTH 28 |
| 11505 | #define GMMx261C_Reserved_31_4_MASK 0xfffffff0 |
| 11506 | |
| 11507 | /// GMMx261C |
| 11508 | typedef union { |
| 11509 | struct { ///< |
| 11510 | UINT32 DbstEn0:4 ; ///< |
| 11511 | UINT32 Reserved_31_4:28; ///< |
| 11512 | } Field; ///< |
| 11513 | UINT32 Value; ///< |
| 11514 | } GMMx261C_STRUCT; |
| 11515 | |
| 11516 | // **** GMMx2638 Register Definition **** |
| 11517 | // Address |
| 11518 | #define GMMx2638_ADDRESS 0x2638 |
| 11519 | |
| 11520 | // Type |
| 11521 | #define GMMx2638_TYPE TYPE_GMM |
| 11522 | // Field Data |
| 11523 | #define GMMx2638_Reserved_17_0_OFFSET 0 |
| 11524 | #define GMMx2638_Reserved_17_0_WIDTH 18 |
| 11525 | #define GMMx2638_Reserved_17_0_MASK 0x3ffff |
| 11526 | #define GMMx2638_Enable_OFFSET 18 |
| 11527 | #define GMMx2638_Enable_WIDTH 1 |
| 11528 | #define GMMx2638_Enable_MASK 0x40000 |
| 11529 | #define GMMx2638_Reserved_31_19_OFFSET 19 |
| 11530 | #define GMMx2638_Reserved_31_19_WIDTH 13 |
| 11531 | #define GMMx2638_Reserved_31_19_MASK 0xfff80000 |
| 11532 | |
| 11533 | /// GMMx2638 |
| 11534 | typedef union { |
| 11535 | struct { ///< |
| 11536 | UINT32 Reserved_17_0:18; ///< |
| 11537 | UINT32 Enable:1 ; ///< |
| 11538 | UINT32 Reserved_31_19:13; ///< |
| 11539 | } Field; ///< |
| 11540 | UINT32 Value; ///< |
| 11541 | } GMMx2638_STRUCT; |
| 11542 | |
| 11543 | // **** GMMx263C Register Definition **** |
| 11544 | // Address |
| 11545 | #define GMMx263C_ADDRESS 0x263c |
| 11546 | |
| 11547 | // Type |
| 11548 | #define GMMx263C_TYPE TYPE_GMM |
| 11549 | // Field Data |
| 11550 | #define GMMx263C_Reserved_17_0_OFFSET 0 |
| 11551 | #define GMMx263C_Reserved_17_0_WIDTH 18 |
| 11552 | #define GMMx263C_Reserved_17_0_MASK 0x3ffff |
| 11553 | #define GMMx263C_Enable_OFFSET 18 |
| 11554 | #define GMMx263C_Enable_WIDTH 1 |
| 11555 | #define GMMx263C_Enable_MASK 0x40000 |
| 11556 | #define GMMx263C_Reserved_31_19_OFFSET 19 |
| 11557 | #define GMMx263C_Reserved_31_19_WIDTH 13 |
| 11558 | #define GMMx263C_Reserved_31_19_MASK 0xfff80000 |
| 11559 | |
| 11560 | /// GMMx263C |
| 11561 | typedef union { |
| 11562 | struct { ///< |
| 11563 | UINT32 Reserved_17_0:18; ///< |
| 11564 | UINT32 Enable:1 ; ///< |
| 11565 | UINT32 Reserved_31_19:13; ///< |
| 11566 | } Field; ///< |
| 11567 | UINT32 Value; ///< |
| 11568 | } GMMx263C_STRUCT; |
| 11569 | |
| 11570 | // **** GMMx2640 Register Definition **** |
| 11571 | // Address |
| 11572 | #define GMMx2640_ADDRESS 0x2640 |
| 11573 | |
| 11574 | // Type |
| 11575 | #define GMMx2640_TYPE TYPE_GMM |
| 11576 | // Field Data |
| 11577 | #define GMMx2640_Reserved_17_0_OFFSET 0 |
| 11578 | #define GMMx2640_Reserved_17_0_WIDTH 18 |
| 11579 | #define GMMx2640_Reserved_17_0_MASK 0x3ffff |
| 11580 | #define GMMx2640_Enable_OFFSET 18 |
| 11581 | #define GMMx2640_Enable_WIDTH 1 |
| 11582 | #define GMMx2640_Enable_MASK 0x40000 |
| 11583 | #define GMMx2640_Reserved_31_19_OFFSET 19 |
| 11584 | #define GMMx2640_Reserved_31_19_WIDTH 13 |
| 11585 | #define GMMx2640_Reserved_31_19_MASK 0xfff80000 |
| 11586 | |
| 11587 | /// GMMx2640 |
| 11588 | typedef union { |
| 11589 | struct { ///< |
| 11590 | UINT32 Reserved_17_0:18; ///< |
| 11591 | UINT32 Enable:1 ; ///< |
| 11592 | UINT32 Reserved_31_19:13; ///< |
| 11593 | } Field; ///< |
| 11594 | UINT32 Value; ///< |
| 11595 | } GMMx2640_STRUCT; |
| 11596 | |
| 11597 | // **** GMMx277C Register Definition **** |
| 11598 | // Address |
| 11599 | #define GMMx277C_ADDRESS 0x277c |
| 11600 | |
| 11601 | // Type |
| 11602 | #define GMMx277C_TYPE TYPE_GMM |
| 11603 | // Field Data |
| 11604 | #define GMMx277C_ActRd_OFFSET 0 |
| 11605 | #define GMMx277C_ActRd_WIDTH 8 |
| 11606 | #define GMMx277C_ActRd_MASK 0xff |
| 11607 | #define GMMx277C_ActWr_OFFSET 8 |
| 11608 | #define GMMx277C_ActWr_WIDTH 8 |
| 11609 | #define GMMx277C_ActWr_MASK 0xff00 |
| 11610 | #define GMMx277C_RasMActRd_OFFSET 16 |
| 11611 | #define GMMx277C_RasMActRd_WIDTH 8 |
| 11612 | #define GMMx277C_RasMActRd_MASK 0xff0000 |
| 11613 | #define GMMx277C_RasMActWr_OFFSET 24 |
| 11614 | #define GMMx277C_RasMActWr_WIDTH 8 |
| 11615 | #define GMMx277C_RasMActWr_MASK 0xff000000 |
| 11616 | |
| 11617 | /// GMMx277C |
| 11618 | typedef union { |
| 11619 | struct { ///< |
| 11620 | UINT32 ActRd:8 ; ///< |
| 11621 | UINT32 ActWr:8 ; ///< |
| 11622 | UINT32 RasMActRd:8 ; ///< |
| 11623 | UINT32 RasMActWr:8 ; ///< |
| 11624 | } Field; ///< |
| 11625 | UINT32 Value; ///< |
| 11626 | } GMMx277C_STRUCT; |
| 11627 | |
| 11628 | // **** GMMx2780 Register Definition **** |
| 11629 | // Address |
| 11630 | #define GMMx2780_ADDRESS 0x2780 |
| 11631 | |
| 11632 | // Type |
| 11633 | #define GMMx2780_TYPE TYPE_GMM |
| 11634 | // Field Data |
| 11635 | #define GMMx2780_Ras2Ras_OFFSET 0 |
| 11636 | #define GMMx2780_Ras2Ras_WIDTH 8 |
| 11637 | #define GMMx2780_Ras2Ras_MASK 0xff |
| 11638 | #define GMMx2780_Rp_OFFSET 8 |
| 11639 | #define GMMx2780_Rp_WIDTH 8 |
| 11640 | #define GMMx2780_Rp_MASK 0xff00 |
| 11641 | #define GMMx2780_WrPlusRp_OFFSET 16 |
| 11642 | #define GMMx2780_WrPlusRp_WIDTH 8 |
| 11643 | #define GMMx2780_WrPlusRp_MASK 0xff0000 |
| 11644 | #define GMMx2780_BusTurn_OFFSET 24 |
| 11645 | #define GMMx2780_BusTurn_WIDTH 8 |
| 11646 | #define GMMx2780_BusTurn_MASK 0xff000000 |
| 11647 | |
| 11648 | /// GMMx2780 |
| 11649 | typedef union { |
| 11650 | struct { ///< |
| 11651 | UINT32 Ras2Ras:8 ; ///< |
| 11652 | UINT32 Rp:8 ; ///< |
| 11653 | UINT32 WrPlusRp:8 ; ///< |
| 11654 | UINT32 BusTurn:8 ; ///< |
| 11655 | } Field; ///< |
| 11656 | UINT32 Value; ///< |
| 11657 | } GMMx2780_STRUCT; |
| 11658 | |
| 11659 | // **** GMMx2784 Register Definition **** |
| 11660 | // Address |
| 11661 | #define GMMx2784_ADDRESS 0x2784 |
| 11662 | |
| 11663 | // Type |
| 11664 | #define GMMx2784_TYPE TYPE_GMM |
| 11665 | // Field Data |
| 11666 | #define GMMx2784_WtMode_OFFSET 0 |
| 11667 | #define GMMx2784_WtMode_WIDTH 2 |
| 11668 | #define GMMx2784_WtMode_MASK 0x3 |
| 11669 | #define GMMx2784_HarshPri_OFFSET 2 |
| 11670 | #define GMMx2784_HarshPri_WIDTH 1 |
| 11671 | #define GMMx2784_HarshPri_MASK 0x4 |
| 11672 | #define GMMx2784_Reserved_31_3_OFFSET 3 |
| 11673 | #define GMMx2784_Reserved_31_3_WIDTH 29 |
| 11674 | #define GMMx2784_Reserved_31_3_MASK 0xfffffff8 |
| 11675 | |
| 11676 | /// GMMx2784 |
| 11677 | typedef union { |
| 11678 | struct { ///< |
| 11679 | UINT32 WtMode:2 ; ///< |
| 11680 | UINT32 HarshPri:1 ; ///< |
| 11681 | UINT32 Reserved_31_3:29; ///< |
| 11682 | } Field; ///< |
| 11683 | UINT32 Value; ///< |
| 11684 | } GMMx2784_STRUCT; |
| 11685 | |
| 11686 | // **** GMMx2788 Register Definition **** |
| 11687 | // Address |
| 11688 | #define GMMx2788_ADDRESS 0x2788 |
| 11689 | |
| 11690 | // Type |
| 11691 | #define GMMx2788_TYPE TYPE_GMM |
| 11692 | // Field Data |
| 11693 | #define GMMx2788_WtMode_OFFSET 0 |
| 11694 | #define GMMx2788_WtMode_WIDTH 2 |
| 11695 | #define GMMx2788_WtMode_MASK 0x3 |
| 11696 | #define GMMx2788_HarshPri_OFFSET 2 |
| 11697 | #define GMMx2788_HarshPri_WIDTH 1 |
| 11698 | #define GMMx2788_HarshPri_MASK 0x4 |
| 11699 | #define GMMx2788_Reserved_31_3_OFFSET 3 |
| 11700 | #define GMMx2788_Reserved_31_3_WIDTH 29 |
| 11701 | #define GMMx2788_Reserved_31_3_MASK 0xfffffff8 |
| 11702 | |
| 11703 | /// GMMx2788 |
| 11704 | typedef union { |
| 11705 | struct { ///< |
| 11706 | UINT32 WtMode:2 ; ///< |
| 11707 | UINT32 HarshPri:1 ; ///< |
| 11708 | UINT32 Reserved_31_3:29; ///< |
| 11709 | } Field; ///< |
| 11710 | UINT32 Value; ///< |
| 11711 | } GMMx2788_STRUCT; |
| 11712 | |
| 11713 | // **** GMMx279C Register Definition **** |
| 11714 | // Address |
| 11715 | #define GMMx279C_ADDRESS 0x279c |
| 11716 | |
| 11717 | // Type |
| 11718 | #define GMMx279C_TYPE TYPE_GMM |
| 11719 | // Field Data |
| 11720 | #define GMMx279C_Group0_OFFSET 0 |
| 11721 | #define GMMx279C_Group0_WIDTH 8 |
| 11722 | #define GMMx279C_Group0_MASK 0xff |
| 11723 | #define GMMx279C_Group1_OFFSET 8 |
| 11724 | #define GMMx279C_Group1_WIDTH 8 |
| 11725 | #define GMMx279C_Group1_MASK 0xff00 |
| 11726 | #define GMMx279C_Group2_OFFSET 16 |
| 11727 | #define GMMx279C_Group2_WIDTH 8 |
| 11728 | #define GMMx279C_Group2_MASK 0xff0000 |
| 11729 | #define GMMx279C_Group3_OFFSET 24 |
| 11730 | #define GMMx279C_Group3_WIDTH 8 |
| 11731 | #define GMMx279C_Group3_MASK 0xff000000 |
| 11732 | |
| 11733 | /// GMMx279C |
| 11734 | typedef union { |
| 11735 | struct { ///< |
| 11736 | UINT32 Group0:8 ; ///< |
| 11737 | UINT32 Group1:8 ; ///< |
| 11738 | UINT32 Group2:8 ; ///< |
| 11739 | UINT32 Group3:8 ; ///< |
| 11740 | } Field; ///< |
| 11741 | UINT32 Value; ///< |
| 11742 | } GMMx279C_STRUCT; |
| 11743 | |
| 11744 | // **** GMMx27A0 Register Definition **** |
| 11745 | // Address |
| 11746 | #define GMMx27A0_ADDRESS 0x27a0 |
| 11747 | |
| 11748 | // Type |
| 11749 | #define GMMx27A0_TYPE TYPE_GMM |
| 11750 | // Field Data |
| 11751 | #define GMMx27A0_Group0_OFFSET 0 |
| 11752 | #define GMMx27A0_Group0_WIDTH 8 |
| 11753 | #define GMMx27A0_Group0_MASK 0xff |
| 11754 | #define GMMx27A0_Group1_OFFSET 8 |
| 11755 | #define GMMx27A0_Group1_WIDTH 8 |
| 11756 | #define GMMx27A0_Group1_MASK 0xff00 |
| 11757 | #define GMMx27A0_Group2_OFFSET 16 |
| 11758 | #define GMMx27A0_Group2_WIDTH 8 |
| 11759 | #define GMMx27A0_Group2_MASK 0xff0000 |
| 11760 | #define GMMx27A0_Group3_OFFSET 24 |
| 11761 | #define GMMx27A0_Group3_WIDTH 8 |
| 11762 | #define GMMx27A0_Group3_MASK 0xff000000 |
| 11763 | |
| 11764 | /// GMMx27A0 |
| 11765 | typedef union { |
| 11766 | struct { ///< |
| 11767 | UINT32 Group0:8 ; ///< |
| 11768 | UINT32 Group1:8 ; ///< |
| 11769 | UINT32 Group2:8 ; ///< |
| 11770 | UINT32 Group3:8 ; ///< |
| 11771 | } Field; ///< |
| 11772 | UINT32 Value; ///< |
| 11773 | } GMMx27A0_STRUCT; |
| 11774 | |
| 11775 | // **** GMMx27CC Register Definition **** |
| 11776 | // Address |
| 11777 | #define GMMx27CC_ADDRESS 0x27cc |
| 11778 | |
| 11779 | // Type |
| 11780 | #define GMMx27CC_TYPE TYPE_GMM |
| 11781 | // Field Data |
| 11782 | #define GMMx27CC_StreakLimit_OFFSET 0 |
| 11783 | #define GMMx27CC_StreakLimit_WIDTH 8 |
| 11784 | #define GMMx27CC_StreakLimit_MASK 0xff |
| 11785 | #define GMMx27CC_StreakLimitUber_OFFSET 8 |
| 11786 | #define GMMx27CC_StreakLimitUber_WIDTH 8 |
| 11787 | #define GMMx27CC_StreakLimitUber_MASK 0xff00 |
| 11788 | #define GMMx27CC_StreakBreak_OFFSET 16 |
| 11789 | #define GMMx27CC_StreakBreak_WIDTH 1 |
| 11790 | #define GMMx27CC_StreakBreak_MASK 0x10000 |
| 11791 | #define GMMx27CC_StreakUber_OFFSET 17 |
| 11792 | #define GMMx27CC_StreakUber_WIDTH 1 |
| 11793 | #define GMMx27CC_StreakUber_MASK 0x20000 |
| 11794 | #define GMMx27CC_Reserved_31_18_OFFSET 18 |
| 11795 | #define GMMx27CC_Reserved_31_18_WIDTH 14 |
| 11796 | #define GMMx27CC_Reserved_31_18_MASK 0xfffc0000 |
| 11797 | |
| 11798 | /// GMMx27CC |
| 11799 | typedef union { |
| 11800 | struct { ///< |
| 11801 | UINT32 StreakLimit:8 ; ///< |
| 11802 | UINT32 StreakLimitUber:8 ; ///< |
| 11803 | UINT32 StreakBreak:1 ; ///< |
| 11804 | UINT32 StreakUber:1 ; ///< |
| 11805 | UINT32 Reserved_31_18:14; ///< |
| 11806 | } Field; ///< |
| 11807 | UINT32 Value; ///< |
| 11808 | } GMMx27CC_STRUCT; |
| 11809 | |
| 11810 | // **** GMMx27D0 Register Definition **** |
| 11811 | // Address |
| 11812 | #define GMMx27D0_ADDRESS 0x27d0 |
| 11813 | |
| 11814 | // Type |
| 11815 | #define GMMx27D0_TYPE TYPE_GMM |
| 11816 | // Field Data |
| 11817 | #define GMMx27D0_StreakLimit_OFFSET 0 |
| 11818 | #define GMMx27D0_StreakLimit_WIDTH 8 |
| 11819 | #define GMMx27D0_StreakLimit_MASK 0xff |
| 11820 | #define GMMx27D0_StreakLimitUber_OFFSET 8 |
| 11821 | #define GMMx27D0_StreakLimitUber_WIDTH 8 |
| 11822 | #define GMMx27D0_StreakLimitUber_MASK 0xff00 |
| 11823 | #define GMMx27D0_StreakBreak_OFFSET 16 |
| 11824 | #define GMMx27D0_StreakBreak_WIDTH 1 |
| 11825 | #define GMMx27D0_StreakBreak_MASK 0x10000 |
| 11826 | #define GMMx27D0_StreakUber_OFFSET 17 |
| 11827 | #define GMMx27D0_StreakUber_WIDTH 1 |
| 11828 | #define GMMx27D0_StreakUber_MASK 0x20000 |
| 11829 | #define GMMx27D0_Reserved_31_18_OFFSET 18 |
| 11830 | #define GMMx27D0_Reserved_31_18_WIDTH 14 |
| 11831 | #define GMMx27D0_Reserved_31_18_MASK 0xfffc0000 |
| 11832 | |
| 11833 | /// GMMx27D0 |
| 11834 | typedef union { |
| 11835 | struct { ///< |
| 11836 | UINT32 StreakLimit:8 ; ///< |
| 11837 | UINT32 StreakLimitUber:8 ; ///< |
| 11838 | UINT32 StreakBreak:1 ; ///< |
| 11839 | UINT32 StreakUber:1 ; ///< |
| 11840 | UINT32 Reserved_31_18:14; ///< |
| 11841 | } Field; ///< |
| 11842 | UINT32 Value; ///< |
| 11843 | } GMMx27D0_STRUCT; |
| 11844 | |
| 11845 | // **** GMMx27DC Register Definition **** |
| 11846 | // Address |
| 11847 | #define GMMx27DC_ADDRESS 0x27dc |
| 11848 | |
| 11849 | // Type |
| 11850 | #define GMMx27DC_TYPE TYPE_GMM |
| 11851 | // Field Data |
| 11852 | #define GMMx27DC_Lcl_OFFSET 0 |
| 11853 | #define GMMx27DC_Lcl_WIDTH 8 |
| 11854 | #define GMMx27DC_Lcl_MASK 0xff |
| 11855 | #define GMMx27DC_Hub_OFFSET 8 |
| 11856 | #define GMMx27DC_Hub_WIDTH 8 |
| 11857 | #define GMMx27DC_Hub_MASK 0xff00 |
| 11858 | #define GMMx27DC_Disp_OFFSET 16 |
| 11859 | #define GMMx27DC_Disp_WIDTH 8 |
| 11860 | #define GMMx27DC_Disp_MASK 0xff0000 |
| 11861 | #define GMMx27DC_Reserved_31_24_OFFSET 24 |
| 11862 | #define GMMx27DC_Reserved_31_24_WIDTH 8 |
| 11863 | #define GMMx27DC_Reserved_31_24_MASK 0xff000000 |
| 11864 | |
| 11865 | /// GMMx27DC |
| 11866 | typedef union { |
| 11867 | struct { ///< |
| 11868 | UINT32 Lcl:8 ; ///< |
| 11869 | UINT32 Hub:8 ; ///< |
| 11870 | UINT32 Disp:8 ; ///< |
| 11871 | UINT32 Reserved_31_24:8 ; ///< |
| 11872 | } Field; ///< |
| 11873 | UINT32 Value; ///< |
| 11874 | } GMMx27DC_STRUCT; |
| 11875 | |
| 11876 | // **** GMMx27E0 Register Definition **** |
| 11877 | // Address |
| 11878 | #define GMMx27E0_ADDRESS 0x27e0 |
| 11879 | |
| 11880 | // Type |
| 11881 | #define GMMx27E0_TYPE TYPE_GMM |
| 11882 | // Field Data |
| 11883 | #define GMMx27E0_Lcl_OFFSET 0 |
| 11884 | #define GMMx27E0_Lcl_WIDTH 8 |
| 11885 | #define GMMx27E0_Lcl_MASK 0xff |
| 11886 | #define GMMx27E0_Hub_OFFSET 8 |
| 11887 | #define GMMx27E0_Hub_WIDTH 8 |
| 11888 | #define GMMx27E0_Hub_MASK 0xff00 |
| 11889 | #define GMMx27E0_Reserved_31_16_OFFSET 16 |
| 11890 | #define GMMx27E0_Reserved_31_16_WIDTH 16 |
| 11891 | #define GMMx27E0_Reserved_31_16_MASK 0xffff0000 |
| 11892 | |
| 11893 | /// GMMx27E0 |
| 11894 | typedef union { |
| 11895 | struct { ///< |
| 11896 | UINT32 Lcl:8 ; ///< |
| 11897 | UINT32 Hub:8 ; ///< |
| 11898 | UINT32 Reserved_31_16:16; ///< |
| 11899 | } Field; ///< |
| 11900 | UINT32 Value; ///< |
| 11901 | } GMMx27E0_STRUCT; |
| 11902 | |
| 11903 | // **** GMMx2814 Register Definition **** |
| 11904 | // Address |
| 11905 | #define GMMx2814_ADDRESS 0x2814 |
| 11906 | |
| 11907 | // Type |
| 11908 | #define GMMx2814_TYPE TYPE_GMM |
| 11909 | // Field Data |
| 11910 | #define GMMx2814_WriteClks_OFFSET 0 |
| 11911 | #define GMMx2814_WriteClks_WIDTH 9 |
| 11912 | #define GMMx2814_WriteClks_MASK 0x1ff |
| 11913 | #define GMMx2814_UvdHarshPriority_OFFSET 9 |
| 11914 | #define GMMx2814_UvdHarshPriority_WIDTH 1 |
| 11915 | #define GMMx2814_UvdHarshPriority_MASK 0x200 |
| 11916 | #define GMMx2814_Reserved_31_10_OFFSET 10 |
| 11917 | #define GMMx2814_Reserved_31_10_WIDTH 22 |
| 11918 | #define GMMx2814_Reserved_31_10_MASK 0xfffffc00 |
| 11919 | |
| 11920 | /// GMMx2814 |
| 11921 | typedef union { |
| 11922 | struct { ///< |
| 11923 | UINT32 WriteClks:9 ; ///< |
| 11924 | UINT32 UvdHarshPriority:1 ; ///< |
| 11925 | UINT32 Reserved_31_10:22; ///< |
| 11926 | } Field; ///< |
| 11927 | UINT32 Value; ///< |
| 11928 | } GMMx2814_STRUCT; |
| 11929 | |
| 11930 | // **** GMMx281C Register Definition **** |
| 11931 | // Address |
| 11932 | #define GMMx281C_ADDRESS 0x281c |
| 11933 | |
| 11934 | // Type |
| 11935 | #define GMMx281C_TYPE TYPE_GMM |
| 11936 | // Field Data |
| 11937 | #define GMMx281C_CSEnable_OFFSET 0 |
| 11938 | #define GMMx281C_CSEnable_WIDTH 1 |
| 11939 | #define GMMx281C_CSEnable_MASK 0x1 |
| 11940 | #define GMMx281C_Reserved_4_1_OFFSET 1 |
| 11941 | #define GMMx281C_Reserved_4_1_WIDTH 4 |
| 11942 | #define GMMx281C_Reserved_4_1_MASK 0x1e |
| 11943 | #define GMMx281C_BaseAddr_21_13__OFFSET 5 |
| 11944 | #define GMMx281C_BaseAddr_21_13__WIDTH 9 |
| 11945 | #define GMMx281C_BaseAddr_21_13__MASK 0x3fe0 |
| 11946 | #define GMMx281C_Reserved_18_14_OFFSET 14 |
| 11947 | #define GMMx281C_Reserved_18_14_WIDTH 5 |
| 11948 | #define GMMx281C_Reserved_18_14_MASK 0x7c000 |
| 11949 | #define GMMx281C_BaseAddr_35_27__OFFSET 19 |
| 11950 | #define GMMx281C_BaseAddr_35_27__WIDTH 9 |
| 11951 | #define GMMx281C_BaseAddr_35_27__MASK 0xff80000 |
| 11952 | #define GMMx281C_Reserved_31_28_OFFSET 28 |
| 11953 | #define GMMx281C_Reserved_31_28_WIDTH 4 |
| 11954 | #define GMMx281C_Reserved_31_28_MASK 0xf0000000 |
| 11955 | |
| 11956 | /// GMMx281C |
| 11957 | typedef union { |
| 11958 | struct { ///< |
| 11959 | UINT32 CSEnable:1 ; ///< |
| 11960 | UINT32 Reserved_4_1:4 ; ///< |
| 11961 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 11962 | UINT32 Reserved_18_14:5 ; ///< |
| 11963 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 11964 | UINT32 Reserved_31_28:4 ; ///< |
| 11965 | } Field; ///< |
| 11966 | UINT32 Value; ///< |
| 11967 | } GMMx281C_STRUCT; |
| 11968 | |
| 11969 | // **** GMMx2824 Register Definition **** |
| 11970 | // Address |
| 11971 | #define GMMx2824_ADDRESS 0x2824 |
| 11972 | |
| 11973 | // Type |
| 11974 | #define GMMx2824_TYPE TYPE_GMM |
| 11975 | // Field Data |
| 11976 | #define GMMx2824_CSEnable_OFFSET 0 |
| 11977 | #define GMMx2824_CSEnable_WIDTH 1 |
| 11978 | #define GMMx2824_CSEnable_MASK 0x1 |
| 11979 | #define GMMx2824_Reserved_4_1_OFFSET 1 |
| 11980 | #define GMMx2824_Reserved_4_1_WIDTH 4 |
| 11981 | #define GMMx2824_Reserved_4_1_MASK 0x1e |
| 11982 | #define GMMx2824_BaseAddr_21_13__OFFSET 5 |
| 11983 | #define GMMx2824_BaseAddr_21_13__WIDTH 9 |
| 11984 | #define GMMx2824_BaseAddr_21_13__MASK 0x3fe0 |
| 11985 | #define GMMx2824_Reserved_18_14_OFFSET 14 |
| 11986 | #define GMMx2824_Reserved_18_14_WIDTH 5 |
| 11987 | #define GMMx2824_Reserved_18_14_MASK 0x7c000 |
| 11988 | #define GMMx2824_BaseAddr_35_27__OFFSET 19 |
| 11989 | #define GMMx2824_BaseAddr_35_27__WIDTH 9 |
| 11990 | #define GMMx2824_BaseAddr_35_27__MASK 0xff80000 |
| 11991 | #define GMMx2824_Reserved_31_28_OFFSET 28 |
| 11992 | #define GMMx2824_Reserved_31_28_WIDTH 4 |
| 11993 | #define GMMx2824_Reserved_31_28_MASK 0xf0000000 |
| 11994 | |
| 11995 | /// GMMx2824 |
| 11996 | typedef union { |
| 11997 | struct { ///< |
| 11998 | UINT32 CSEnable:1 ; ///< |
| 11999 | UINT32 Reserved_4_1:4 ; ///< |
| 12000 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 12001 | UINT32 Reserved_18_14:5 ; ///< |
| 12002 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 12003 | UINT32 Reserved_31_28:4 ; ///< |
| 12004 | } Field; ///< |
| 12005 | UINT32 Value; ///< |
| 12006 | } GMMx2824_STRUCT; |
| 12007 | |
| 12008 | // **** GMMx282C Register Definition **** |
| 12009 | // Address |
| 12010 | #define GMMx282C_ADDRESS 0x282c |
| 12011 | |
| 12012 | // Type |
| 12013 | #define GMMx282C_TYPE TYPE_GMM |
| 12014 | // Field Data |
| 12015 | #define GMMx282C_CSEnable_OFFSET 0 |
| 12016 | #define GMMx282C_CSEnable_WIDTH 1 |
| 12017 | #define GMMx282C_CSEnable_MASK 0x1 |
| 12018 | #define GMMx282C_Reserved_4_1_OFFSET 1 |
| 12019 | #define GMMx282C_Reserved_4_1_WIDTH 4 |
| 12020 | #define GMMx282C_Reserved_4_1_MASK 0x1e |
| 12021 | #define GMMx282C_BaseAddr_21_13__OFFSET 5 |
| 12022 | #define GMMx282C_BaseAddr_21_13__WIDTH 9 |
| 12023 | #define GMMx282C_BaseAddr_21_13__MASK 0x3fe0 |
| 12024 | #define GMMx282C_Reserved_18_14_OFFSET 14 |
| 12025 | #define GMMx282C_Reserved_18_14_WIDTH 5 |
| 12026 | #define GMMx282C_Reserved_18_14_MASK 0x7c000 |
| 12027 | #define GMMx282C_BaseAddr_35_27__OFFSET 19 |
| 12028 | #define GMMx282C_BaseAddr_35_27__WIDTH 9 |
| 12029 | #define GMMx282C_BaseAddr_35_27__MASK 0xff80000 |
| 12030 | #define GMMx282C_Reserved_31_28_OFFSET 28 |
| 12031 | #define GMMx282C_Reserved_31_28_WIDTH 4 |
| 12032 | #define GMMx282C_Reserved_31_28_MASK 0xf0000000 |
| 12033 | |
| 12034 | /// GMMx282C |
| 12035 | typedef union { |
| 12036 | struct { ///< |
| 12037 | UINT32 CSEnable:1 ; ///< |
| 12038 | UINT32 Reserved_4_1:4 ; ///< |
| 12039 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 12040 | UINT32 Reserved_18_14:5 ; ///< |
| 12041 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 12042 | UINT32 Reserved_31_28:4 ; ///< |
| 12043 | } Field; ///< |
| 12044 | UINT32 Value; ///< |
| 12045 | } GMMx282C_STRUCT; |
| 12046 | |
| 12047 | // **** GMMx2834 Register Definition **** |
| 12048 | // Address |
| 12049 | #define GMMx2834_ADDRESS 0x2834 |
| 12050 | |
| 12051 | // Type |
| 12052 | #define GMMx2834_TYPE TYPE_GMM |
| 12053 | // Field Data |
| 12054 | #define GMMx2834_CSEnable_OFFSET 0 |
| 12055 | #define GMMx2834_CSEnable_WIDTH 1 |
| 12056 | #define GMMx2834_CSEnable_MASK 0x1 |
| 12057 | #define GMMx2834_Reserved_4_1_OFFSET 1 |
| 12058 | #define GMMx2834_Reserved_4_1_WIDTH 4 |
| 12059 | #define GMMx2834_Reserved_4_1_MASK 0x1e |
| 12060 | #define GMMx2834_BaseAddr_21_13__OFFSET 5 |
| 12061 | #define GMMx2834_BaseAddr_21_13__WIDTH 9 |
| 12062 | #define GMMx2834_BaseAddr_21_13__MASK 0x3fe0 |
| 12063 | #define GMMx2834_Reserved_18_14_OFFSET 14 |
| 12064 | #define GMMx2834_Reserved_18_14_WIDTH 5 |
| 12065 | #define GMMx2834_Reserved_18_14_MASK 0x7c000 |
| 12066 | #define GMMx2834_BaseAddr_35_27__OFFSET 19 |
| 12067 | #define GMMx2834_BaseAddr_35_27__WIDTH 9 |
| 12068 | #define GMMx2834_BaseAddr_35_27__MASK 0xff80000 |
| 12069 | #define GMMx2834_Reserved_31_28_OFFSET 28 |
| 12070 | #define GMMx2834_Reserved_31_28_WIDTH 4 |
| 12071 | #define GMMx2834_Reserved_31_28_MASK 0xf0000000 |
| 12072 | |
| 12073 | /// GMMx2834 |
| 12074 | typedef union { |
| 12075 | struct { ///< |
| 12076 | UINT32 CSEnable:1 ; ///< |
| 12077 | UINT32 Reserved_4_1:4 ; ///< |
| 12078 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 12079 | UINT32 Reserved_18_14:5 ; ///< |
| 12080 | UINT32 BaseAddr_35_27_:9 ; ///< |
| 12081 | UINT32 Reserved_31_28:4 ; ///< |
| 12082 | } Field; ///< |
| 12083 | UINT32 Value; ///< |
| 12084 | } GMMx2834_STRUCT; |
| 12085 | |
| 12086 | // **** GMMx283C Register Definition **** |
| 12087 | // Address |
| 12088 | #define GMMx283C_ADDRESS 0x283c |
| 12089 | |
| 12090 | // Type |
| 12091 | #define GMMx283C_TYPE TYPE_GMM |
| 12092 | // Field Data |
| 12093 | #define GMMx283C_Reserved_4_0_OFFSET 0 |
| 12094 | #define GMMx283C_Reserved_4_0_WIDTH 5 |
| 12095 | #define GMMx283C_Reserved_4_0_MASK 0x1f |
| 12096 | #define GMMx283C_AddrMask_21_13__OFFSET 5 |
| 12097 | #define GMMx283C_AddrMask_21_13__WIDTH 9 |
| 12098 | #define GMMx283C_AddrMask_21_13__MASK 0x3fe0 |
| 12099 | #define GMMx283C_Reserved_18_14_OFFSET 14 |
| 12100 | #define GMMx283C_Reserved_18_14_WIDTH 5 |
| 12101 | #define GMMx283C_Reserved_18_14_MASK 0x7c000 |
| 12102 | #define GMMx283C_AddrMask_35_27__OFFSET 19 |
| 12103 | #define GMMx283C_AddrMask_35_27__WIDTH 9 |
| 12104 | #define GMMx283C_AddrMask_35_27__MASK 0xff80000 |
| 12105 | #define GMMx283C_Reserved_28_28_OFFSET 28 |
| 12106 | #define GMMx283C_Reserved_28_28_WIDTH 1 |
| 12107 | #define GMMx283C_Reserved_28_28_MASK 0x10000000 |
| 12108 | #define GMMx283C_Reserved_31_29_OFFSET 29 |
| 12109 | #define GMMx283C_Reserved_31_29_WIDTH 3 |
| 12110 | #define GMMx283C_Reserved_31_29_MASK 0xe0000000 |
| 12111 | |
| 12112 | /// GMMx283C |
| 12113 | typedef union { |
| 12114 | struct { ///< |
| 12115 | UINT32 Reserved_4_0:5 ; ///< |
| 12116 | UINT32 AddrMask_21_13_:9 ; ///< |
| 12117 | UINT32 Reserved_18_14:5 ; ///< |
| 12118 | UINT32 AddrMask_35_27_:9 ; ///< |
| 12119 | UINT32 Reserved_28_28:1 ; ///< |
| 12120 | UINT32 Reserved_31_29:3 ; ///< |
| 12121 | } Field; ///< |
| 12122 | UINT32 Value; ///< |
| 12123 | } GMMx283C_STRUCT; |
| 12124 | |
| 12125 | // **** GMMx2840 Register Definition **** |
| 12126 | // Address |
| 12127 | #define GMMx2840_ADDRESS 0x2840 |
| 12128 | |
| 12129 | // Type |
| 12130 | #define GMMx2840_TYPE TYPE_GMM |
| 12131 | // Field Data |
| 12132 | #define GMMx2840_Reserved_4_0_OFFSET 0 |
| 12133 | #define GMMx2840_Reserved_4_0_WIDTH 5 |
| 12134 | #define GMMx2840_Reserved_4_0_MASK 0x1f |
| 12135 | #define GMMx2840_AddrMask_21_13__OFFSET 5 |
| 12136 | #define GMMx2840_AddrMask_21_13__WIDTH 9 |
| 12137 | #define GMMx2840_AddrMask_21_13__MASK 0x3fe0 |
| 12138 | #define GMMx2840_Reserved_18_14_OFFSET 14 |
| 12139 | #define GMMx2840_Reserved_18_14_WIDTH 5 |
| 12140 | #define GMMx2840_Reserved_18_14_MASK 0x7c000 |
| 12141 | #define GMMx2840_AddrMask_35_27__OFFSET 19 |
| 12142 | #define GMMx2840_AddrMask_35_27__WIDTH 9 |
| 12143 | #define GMMx2840_AddrMask_35_27__MASK 0xff80000 |
| 12144 | #define GMMx2840_Reserved_28_28_OFFSET 28 |
| 12145 | #define GMMx2840_Reserved_28_28_WIDTH 1 |
| 12146 | #define GMMx2840_Reserved_28_28_MASK 0x10000000 |
| 12147 | #define GMMx2840_Reserved_31_29_OFFSET 29 |
| 12148 | #define GMMx2840_Reserved_31_29_WIDTH 3 |
| 12149 | #define GMMx2840_Reserved_31_29_MASK 0xe0000000 |
| 12150 | |
| 12151 | /// GMMx2840 |
| 12152 | typedef union { |
| 12153 | struct { ///< |
| 12154 | UINT32 Reserved_4_0:5 ; ///< |
| 12155 | UINT32 AddrMask_21_13_:9 ; ///< |
| 12156 | UINT32 Reserved_18_14:5 ; ///< |
| 12157 | UINT32 AddrMask_35_27_:9 ; ///< |
| 12158 | UINT32 Reserved_28_28:1 ; ///< |
| 12159 | UINT32 Reserved_31_29:3 ; ///< |
| 12160 | } Field; ///< |
| 12161 | UINT32 Value; ///< |
| 12162 | } GMMx2840_STRUCT; |
| 12163 | |
| 12164 | // **** GMMx284C Register Definition **** |
| 12165 | // Address |
| 12166 | #define GMMx284C_ADDRESS 0x284c |
| 12167 | |
| 12168 | // Type |
| 12169 | #define GMMx284C_TYPE TYPE_GMM |
| 12170 | // Field Data |
| 12171 | #define GMMx284C_Dimm0AddrMap_OFFSET 0 |
| 12172 | #define GMMx284C_Dimm0AddrMap_WIDTH 4 |
| 12173 | #define GMMx284C_Dimm0AddrMap_MASK 0xf |
| 12174 | #define GMMx284C_Dimm1AddrMap_OFFSET 4 |
| 12175 | #define GMMx284C_Dimm1AddrMap_WIDTH 4 |
| 12176 | #define GMMx284C_Dimm1AddrMap_MASK 0xf0 |
| 12177 | #define GMMx284C_Reserved_15_8_OFFSET 8 |
| 12178 | #define GMMx284C_Reserved_15_8_WIDTH 8 |
| 12179 | #define GMMx284C_Reserved_15_8_MASK 0xff00 |
| 12180 | #define GMMx284C_BankSwizzleMode_OFFSET 16 |
| 12181 | #define GMMx284C_BankSwizzleMode_WIDTH 1 |
| 12182 | #define GMMx284C_BankSwizzleMode_MASK 0x10000 |
| 12183 | #define GMMx284C_Reserved_18_17_OFFSET 17 |
| 12184 | #define GMMx284C_Reserved_18_17_WIDTH 2 |
| 12185 | #define GMMx284C_Reserved_18_17_MASK 0x60000 |
| 12186 | #define GMMx284C_BankSwap_OFFSET 19 |
| 12187 | #define GMMx284C_BankSwap_WIDTH 1 |
| 12188 | #define GMMx284C_BankSwap_MASK 0x80000 |
| 12189 | #define GMMx284C_Reserved_31_20_OFFSET 20 |
| 12190 | #define GMMx284C_Reserved_31_20_WIDTH 12 |
| 12191 | #define GMMx284C_Reserved_31_20_MASK 0xfff00000 |
| 12192 | |
| 12193 | /// GMMx284C |
| 12194 | typedef union { |
| 12195 | struct { ///< |
| 12196 | UINT32 Dimm0AddrMap:4 ; ///< |
| 12197 | UINT32 Dimm1AddrMap:4 ; ///< |
| 12198 | UINT32 Reserved_15_8:8 ; ///< |
| 12199 | UINT32 BankSwizzleMode:1 ; ///< |
| 12200 | UINT32 Reserved_18_17:2 ; ///< |
| 12201 | UINT32 BankSwap:1 ; ///< |
| 12202 | UINT32 Reserved_31_20:12; ///< |
| 12203 | } Field; ///< |
| 12204 | UINT32 Value; ///< |
| 12205 | } GMMx284C_STRUCT; |
| 12206 | |
| 12207 | // **** GMMx2858 Register Definition **** |
| 12208 | // Address |
| 12209 | #define GMMx2858_ADDRESS 0x2858 |
| 12210 | |
| 12211 | // Type |
| 12212 | #define GMMx2858_TYPE TYPE_GMM |
| 12213 | // Field Data |
| 12214 | #define GMMx2858_Reserved_8_0_OFFSET 0 |
| 12215 | #define GMMx2858_Reserved_8_0_WIDTH 9 |
| 12216 | #define GMMx2858_Reserved_8_0_MASK 0x1ff |
| 12217 | #define GMMx2858_DctSelBankSwap_OFFSET 9 |
| 12218 | #define GMMx2858_DctSelBankSwap_WIDTH 1 |
| 12219 | #define GMMx2858_DctSelBankSwap_MASK 0x200 |
| 12220 | #define GMMx2858_Reserved_31_10_OFFSET 10 |
| 12221 | #define GMMx2858_Reserved_31_10_WIDTH 22 |
| 12222 | #define GMMx2858_Reserved_31_10_MASK 0xfffffc00 |
| 12223 | |
| 12224 | /// GMMx2858 |
| 12225 | typedef union { |
| 12226 | struct { ///< |
| 12227 | UINT32 Reserved_8_0:9 ; ///< |
| 12228 | UINT32 DctSelBankSwap:1 ; ///< |
| 12229 | UINT32 Reserved_31_10:22; ///< |
| 12230 | } Field; ///< |
| 12231 | UINT32 Value; ///< |
| 12232 | } GMMx2858_STRUCT; |
| 12233 | |
| 12234 | // **** GMMx285C Register Definition **** |
| 12235 | // Address |
| 12236 | #define GMMx285C_ADDRESS 0x285c |
| 12237 | |
| 12238 | // Type |
| 12239 | #define GMMx285C_TYPE TYPE_GMM |
| 12240 | // Field Data |
| 12241 | #define GMMx285C_DramHoleValid_OFFSET 0 |
| 12242 | #define GMMx285C_DramHoleValid_WIDTH 1 |
| 12243 | #define GMMx285C_DramHoleValid_MASK 0x1 |
| 12244 | #define GMMx285C_Reserved_6_1_OFFSET 1 |
| 12245 | #define GMMx285C_Reserved_6_1_WIDTH 6 |
| 12246 | #define GMMx285C_Reserved_6_1_MASK 0x7e |
| 12247 | #define GMMx285C_DramHoleOffset_31_23__OFFSET 7 |
| 12248 | #define GMMx285C_DramHoleOffset_31_23__WIDTH 9 |
| 12249 | #define GMMx285C_DramHoleOffset_31_23__MASK 0xff80 |
| 12250 | #define GMMx285C_Reserved_23_16_OFFSET 16 |
| 12251 | #define GMMx285C_Reserved_23_16_WIDTH 8 |
| 12252 | #define GMMx285C_Reserved_23_16_MASK 0xff0000 |
| 12253 | #define GMMx285C_DramHoleBase_31_24__OFFSET 24 |
| 12254 | #define GMMx285C_DramHoleBase_31_24__WIDTH 8 |
| 12255 | #define GMMx285C_DramHoleBase_31_24__MASK 0xff000000 |
| 12256 | |
| 12257 | /// GMMx285C |
| 12258 | typedef union { |
| 12259 | struct { ///< |
| 12260 | UINT32 DramHoleValid:1 ; ///< |
| 12261 | UINT32 Reserved_6_1:6 ; ///< |
| 12262 | UINT32 DramHoleOffset_31_23_:9 ; ///< |
| 12263 | UINT32 Reserved_23_16:8 ; ///< |
| 12264 | UINT32 DramHoleBase_31_24_:8 ; ///< |
| 12265 | } Field; ///< |
| 12266 | UINT32 Value; ///< |
| 12267 | } GMMx285C_STRUCT; |
| 12268 | |
| 12269 | // **** GMMx2864 Register Definition **** |
| 12270 | // Address |
| 12271 | #define GMMx2864_ADDRESS 0x2864 |
| 12272 | |
| 12273 | // Type |
| 12274 | #define GMMx2864_TYPE TYPE_GMM |
| 12275 | // Field Data |
| 12276 | #define GMMx2864_A8Map_OFFSET 0 |
| 12277 | #define GMMx2864_A8Map_WIDTH 4 |
| 12278 | #define GMMx2864_A8Map_MASK 0xf |
| 12279 | #define GMMx2864_A9Map_OFFSET 4 |
| 12280 | #define GMMx2864_A9Map_WIDTH 4 |
| 12281 | #define GMMx2864_A9Map_MASK 0xf0 |
| 12282 | #define GMMx2864_A10Map_OFFSET 8 |
| 12283 | #define GMMx2864_A10Map_WIDTH 4 |
| 12284 | #define GMMx2864_A10Map_MASK 0xf00 |
| 12285 | #define GMMx2864_A11Map_OFFSET 12 |
| 12286 | #define GMMx2864_A11Map_WIDTH 4 |
| 12287 | #define GMMx2864_A11Map_MASK 0xf000 |
| 12288 | #define GMMx2864_A12Map_OFFSET 16 |
| 12289 | #define GMMx2864_A12Map_WIDTH 4 |
| 12290 | #define GMMx2864_A12Map_MASK 0xf0000 |
| 12291 | #define GMMx2864_A13Map_OFFSET 20 |
| 12292 | #define GMMx2864_A13Map_WIDTH 4 |
| 12293 | #define GMMx2864_A13Map_MASK 0xf00000 |
| 12294 | #define GMMx2864_A14Map_OFFSET 24 |
| 12295 | #define GMMx2864_A14Map_WIDTH 4 |
| 12296 | #define GMMx2864_A14Map_MASK 0xf000000 |
| 12297 | #define GMMx2864_A15Map_OFFSET 28 |
| 12298 | #define GMMx2864_A15Map_WIDTH 4 |
| 12299 | #define GMMx2864_A15Map_MASK 0xf0000000 |
| 12300 | |
| 12301 | /// GMMx2864 |
| 12302 | typedef union { |
| 12303 | struct { ///< |
| 12304 | UINT32 A8Map:4 ; ///< |
| 12305 | UINT32 A9Map:4 ; ///< |
| 12306 | UINT32 A10Map:4 ; ///< |
| 12307 | UINT32 A11Map:4 ; ///< |
| 12308 | UINT32 A12Map:4 ; ///< |
| 12309 | UINT32 A13Map:4 ; ///< |
| 12310 | UINT32 A14Map:4 ; ///< |
| 12311 | UINT32 A15Map:4 ; ///< |
| 12312 | } Field; ///< |
| 12313 | UINT32 Value; ///< |
| 12314 | } GMMx2864_STRUCT; |
| 12315 | |
| 12316 | // **** GMMx286C Register Definition **** |
| 12317 | // Address |
| 12318 | #define GMMx286C_ADDRESS 0x286c |
| 12319 | |
| 12320 | // Type |
| 12321 | #define GMMx286C_TYPE TYPE_GMM |
| 12322 | // Field Data |
| 12323 | #define GMMx286C_Base_OFFSET 0 |
| 12324 | #define GMMx286C_Base_WIDTH 20 |
| 12325 | #define GMMx286C_Base_MASK 0xfffff |
| 12326 | #define GMMx286C_Reserved_31_20_OFFSET 20 |
| 12327 | #define GMMx286C_Reserved_31_20_WIDTH 12 |
| 12328 | #define GMMx286C_Reserved_31_20_MASK 0xfff00000 |
| 12329 | |
| 12330 | /// GMMx286C |
| 12331 | typedef union { |
| 12332 | struct { ///< |
| 12333 | UINT32 Base:20; ///< |
| 12334 | UINT32 Reserved_31_20:12; ///< |
| 12335 | } Field; ///< |
| 12336 | UINT32 Value; ///< |
| 12337 | } GMMx286C_STRUCT; |
| 12338 | |
| 12339 | // **** GMMx2870 Register Definition **** |
| 12340 | // Address |
| 12341 | #define GMMx2870_ADDRESS 0x2870 |
| 12342 | |
| 12343 | // Type |
| 12344 | #define GMMx2870_TYPE TYPE_GMM |
| 12345 | // Field Data |
| 12346 | #define GMMx2870_Base_OFFSET 0 |
| 12347 | #define GMMx2870_Base_WIDTH 20 |
| 12348 | #define GMMx2870_Base_MASK 0xfffff |
| 12349 | #define GMMx2870_Reserved_31_20_OFFSET 20 |
| 12350 | #define GMMx2870_Reserved_31_20_WIDTH 12 |
| 12351 | #define GMMx2870_Reserved_31_20_MASK 0xfff00000 |
| 12352 | |
| 12353 | /// GMMx2870 |
| 12354 | typedef union { |
| 12355 | struct { ///< |
| 12356 | UINT32 Base:20; ///< |
| 12357 | UINT32 Reserved_31_20:12; ///< |
| 12358 | } Field; ///< |
| 12359 | UINT32 Value; ///< |
| 12360 | } GMMx2870_STRUCT; |
| 12361 | |
| 12362 | // **** GMMx2874 Register Definition **** |
| 12363 | // Address |
| 12364 | #define GMMx2874_ADDRESS 0x2874 |
| 12365 | |
| 12366 | // Type |
| 12367 | #define GMMx2874_TYPE TYPE_GMM |
| 12368 | // Field Data |
| 12369 | #define GMMx2874_Base_OFFSET 0 |
| 12370 | #define GMMx2874_Base_WIDTH 20 |
| 12371 | #define GMMx2874_Base_MASK 0xfffff |
| 12372 | #define GMMx2874_Reserved_31_20_OFFSET 20 |
| 12373 | #define GMMx2874_Reserved_31_20_WIDTH 12 |
| 12374 | #define GMMx2874_Reserved_31_20_MASK 0xfff00000 |
| 12375 | |
| 12376 | /// GMMx2874 |
| 12377 | typedef union { |
| 12378 | struct { ///< |
| 12379 | UINT32 Base:20; ///< |
| 12380 | UINT32 Reserved_31_20:12; ///< |
| 12381 | } Field; ///< |
| 12382 | UINT32 Value; ///< |
| 12383 | } GMMx2874_STRUCT; |
| 12384 | |
| 12385 | // **** GMMx2878 Register Definition **** |
| 12386 | // Address |
| 12387 | #define GMMx2878_ADDRESS 0x2878 |
| 12388 | |
| 12389 | // Type |
| 12390 | #define GMMx2878_TYPE TYPE_GMM |
| 12391 | // Field Data |
| 12392 | #define GMMx2878_Base_OFFSET 0 |
| 12393 | #define GMMx2878_Base_WIDTH 20 |
| 12394 | #define GMMx2878_Base_MASK 0xfffff |
| 12395 | #define GMMx2878_Reserved_31_20_OFFSET 20 |
| 12396 | #define GMMx2878_Reserved_31_20_WIDTH 12 |
| 12397 | #define GMMx2878_Reserved_31_20_MASK 0xfff00000 |
| 12398 | |
| 12399 | /// GMMx2878 |
| 12400 | typedef union { |
| 12401 | struct { ///< |
| 12402 | UINT32 Base:20; ///< |
| 12403 | UINT32 Reserved_31_20:12; ///< |
| 12404 | } Field; ///< |
| 12405 | UINT32 Value; ///< |
| 12406 | } GMMx2878_STRUCT; |
| 12407 | |
| 12408 | // **** GMMx287C Register Definition **** |
| 12409 | // Address |
| 12410 | #define GMMx287C_ADDRESS 0x287c |
| 12411 | |
| 12412 | // Type |
| 12413 | #define GMMx287C_TYPE TYPE_GMM |
| 12414 | // Field Data |
| 12415 | #define GMMx287C_Top_OFFSET 0 |
| 12416 | #define GMMx287C_Top_WIDTH 20 |
| 12417 | #define GMMx287C_Top_MASK 0xfffff |
| 12418 | #define GMMx287C_Reserved_31_20_OFFSET 20 |
| 12419 | #define GMMx287C_Reserved_31_20_WIDTH 12 |
| 12420 | #define GMMx287C_Reserved_31_20_MASK 0xfff00000 |
| 12421 | |
| 12422 | /// GMMx287C |
| 12423 | typedef union { |
| 12424 | struct { ///< |
| 12425 | UINT32 Top:20; ///< |
| 12426 | UINT32 Reserved_31_20:12; ///< |
| 12427 | } Field; ///< |
| 12428 | UINT32 Value; ///< |
| 12429 | } GMMx287C_STRUCT; |
| 12430 | |
| 12431 | // **** GMMx2880 Register Definition **** |
| 12432 | // Address |
| 12433 | #define GMMx2880_ADDRESS 0x2880 |
| 12434 | |
| 12435 | // Type |
| 12436 | #define GMMx2880_TYPE TYPE_GMM |
| 12437 | // Field Data |
| 12438 | #define GMMx2880_Top_OFFSET 0 |
| 12439 | #define GMMx2880_Top_WIDTH 20 |
| 12440 | #define GMMx2880_Top_MASK 0xfffff |
| 12441 | #define GMMx2880_Reserved_31_20_OFFSET 20 |
| 12442 | #define GMMx2880_Reserved_31_20_WIDTH 12 |
| 12443 | #define GMMx2880_Reserved_31_20_MASK 0xfff00000 |
| 12444 | |
| 12445 | /// GMMx2880 |
| 12446 | typedef union { |
| 12447 | struct { ///< |
| 12448 | UINT32 Top:20; ///< |
| 12449 | UINT32 Reserved_31_20:12; ///< |
| 12450 | } Field; ///< |
| 12451 | UINT32 Value; ///< |
| 12452 | } GMMx2880_STRUCT; |
| 12453 | |
| 12454 | // **** GMMx2884 Register Definition **** |
| 12455 | // Address |
| 12456 | #define GMMx2884_ADDRESS 0x2884 |
| 12457 | |
| 12458 | // Type |
| 12459 | #define GMMx2884_TYPE TYPE_GMM |
| 12460 | // Field Data |
| 12461 | #define GMMx2884_Top_OFFSET 0 |
| 12462 | #define GMMx2884_Top_WIDTH 20 |
| 12463 | #define GMMx2884_Top_MASK 0xfffff |
| 12464 | #define GMMx2884_Reserved_31_20_OFFSET 20 |
| 12465 | #define GMMx2884_Reserved_31_20_WIDTH 12 |
| 12466 | #define GMMx2884_Reserved_31_20_MASK 0xfff00000 |
| 12467 | |
| 12468 | /// GMMx2884 |
| 12469 | typedef union { |
| 12470 | struct { ///< |
| 12471 | UINT32 Top:20; ///< |
| 12472 | UINT32 Reserved_31_20:12; ///< |
| 12473 | } Field; ///< |
| 12474 | UINT32 Value; ///< |
| 12475 | } GMMx2884_STRUCT; |
| 12476 | |
| 12477 | // **** GMMx2888 Register Definition **** |
| 12478 | // Address |
| 12479 | #define GMMx2888_ADDRESS 0x2888 |
| 12480 | |
| 12481 | // Type |
| 12482 | #define GMMx2888_TYPE TYPE_GMM |
| 12483 | // Field Data |
| 12484 | #define GMMx2888_Top_OFFSET 0 |
| 12485 | #define GMMx2888_Top_WIDTH 20 |
| 12486 | #define GMMx2888_Top_MASK 0xfffff |
| 12487 | #define GMMx2888_Reserved_31_20_OFFSET 20 |
| 12488 | #define GMMx2888_Reserved_31_20_WIDTH 12 |
| 12489 | #define GMMx2888_Reserved_31_20_MASK 0xfff00000 |
| 12490 | |
| 12491 | /// GMMx2888 |
| 12492 | typedef union { |
| 12493 | struct { ///< |
| 12494 | UINT32 Top:20; ///< |
| 12495 | UINT32 Reserved_31_20:12; ///< |
| 12496 | } Field; ///< |
| 12497 | UINT32 Value; ///< |
| 12498 | } GMMx2888_STRUCT; |
| 12499 | |
| 12500 | // **** GMMx288C Register Definition **** |
| 12501 | // Address |
| 12502 | #define GMMx288C_ADDRESS 0x288c |
| 12503 | |
| 12504 | // Type |
| 12505 | #define GMMx288C_TYPE TYPE_GMM |
| 12506 | // Field Data |
| 12507 | #define GMMx288C_Base_OFFSET 0 |
| 12508 | #define GMMx288C_Base_WIDTH 20 |
| 12509 | #define GMMx288C_Base_MASK 0xfffff |
| 12510 | #define GMMx288C_Reserved_31_20_OFFSET 20 |
| 12511 | #define GMMx288C_Reserved_31_20_WIDTH 12 |
| 12512 | #define GMMx288C_Reserved_31_20_MASK 0xfff00000 |
| 12513 | |
| 12514 | /// GMMx288C |
| 12515 | typedef union { |
| 12516 | struct { ///< |
| 12517 | UINT32 Base:20; ///< |
| 12518 | UINT32 Reserved_31_20:12; ///< |
| 12519 | } Field; ///< |
| 12520 | UINT32 Value; ///< |
| 12521 | } GMMx288C_STRUCT; |
| 12522 | |
| 12523 | // **** GMMx2890 Register Definition **** |
| 12524 | // Address |
| 12525 | #define GMMx2890_ADDRESS 0x2890 |
| 12526 | |
| 12527 | // Type |
| 12528 | #define GMMx2890_TYPE TYPE_GMM |
| 12529 | // Field Data |
| 12530 | #define GMMx2890_Top_OFFSET 0 |
| 12531 | #define GMMx2890_Top_WIDTH 20 |
| 12532 | #define GMMx2890_Top_MASK 0xfffff |
| 12533 | #define GMMx2890_Reserved_31_20_OFFSET 20 |
| 12534 | #define GMMx2890_Reserved_31_20_WIDTH 12 |
| 12535 | #define GMMx2890_Reserved_31_20_MASK 0xfff00000 |
| 12536 | |
| 12537 | /// GMMx2890 |
| 12538 | typedef union { |
| 12539 | struct { ///< |
| 12540 | UINT32 Top:20; ///< |
| 12541 | UINT32 Reserved_31_20:12; ///< |
| 12542 | } Field; ///< |
| 12543 | UINT32 Value; ///< |
| 12544 | } GMMx2890_STRUCT; |
| 12545 | |
| 12546 | // **** GMMx2894 Register Definition **** |
| 12547 | // Address |
| 12548 | #define GMMx2894_ADDRESS 0x2894 |
| 12549 | |
| 12550 | // Type |
| 12551 | #define GMMx2894_TYPE TYPE_GMM |
| 12552 | // Field Data |
| 12553 | #define GMMx2894_Def_OFFSET 0 |
| 12554 | #define GMMx2894_Def_WIDTH 28 |
| 12555 | #define GMMx2894_Def_MASK 0xfffffff |
| 12556 | #define GMMx2894_Reserved_31_28_OFFSET 28 |
| 12557 | #define GMMx2894_Reserved_31_28_WIDTH 4 |
| 12558 | #define GMMx2894_Reserved_31_28_MASK 0xf0000000 |
| 12559 | |
| 12560 | /// GMMx2894 |
| 12561 | typedef union { |
| 12562 | struct { ///< |
| 12563 | UINT32 Def:28; ///< |
| 12564 | UINT32 Reserved_31_28:4 ; ///< |
| 12565 | } Field; ///< |
| 12566 | UINT32 Value; ///< |
| 12567 | } GMMx2894_STRUCT; |
| 12568 | |
| 12569 | // **** GMMx2898 Register Definition **** |
| 12570 | // Address |
| 12571 | #define GMMx2898_ADDRESS 0x2898 |
| 12572 | |
| 12573 | // Type |
| 12574 | #define GMMx2898_TYPE TYPE_GMM |
| 12575 | // Field Data |
| 12576 | #define GMMx2898_Offset_OFFSET 0 |
| 12577 | #define GMMx2898_Offset_WIDTH 20 |
| 12578 | #define GMMx2898_Offset_MASK 0xfffff |
| 12579 | #define GMMx2898_Base_OFFSET 20 |
| 12580 | #define GMMx2898_Base_WIDTH 4 |
| 12581 | #define GMMx2898_Base_MASK 0xf00000 |
| 12582 | #define GMMx2898_Top_OFFSET 24 |
| 12583 | #define GMMx2898_Top_WIDTH 4 |
| 12584 | #define GMMx2898_Top_MASK 0xf000000 |
| 12585 | #define GMMx2898_Reserved_31_28_OFFSET 28 |
| 12586 | #define GMMx2898_Reserved_31_28_WIDTH 4 |
| 12587 | #define GMMx2898_Reserved_31_28_MASK 0xf0000000 |
| 12588 | |
| 12589 | /// GMMx2898 |
| 12590 | typedef union { |
| 12591 | struct { ///< |
| 12592 | UINT32 Offset:20; ///< |
| 12593 | UINT32 Base:4 ; ///< |
| 12594 | UINT32 Top:4 ; ///< |
| 12595 | UINT32 Reserved_31_28:4 ; ///< |
| 12596 | } Field; ///< |
| 12597 | UINT32 Value; ///< |
| 12598 | } GMMx2898_STRUCT; |
| 12599 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12600 | // **** GMMx28C8 Register Definition **** |
| 12601 | // Address |
| 12602 | #define GMMx28C8_ADDRESS 0x28c8 |
| 12603 | |
| 12604 | // Type |
| 12605 | #define GMMx28C8_TYPE TYPE_GMM |
| 12606 | // Field Data |
| 12607 | #define GMMx28C8_Delay_OFFSET 0 |
| 12608 | #define GMMx28C8_Delay_WIDTH 4 |
| 12609 | #define GMMx28C8_Delay_MASK 0xf |
| 12610 | #define GMMx28C8_Reserved_31_4_OFFSET 4 |
| 12611 | #define GMMx28C8_Reserved_31_4_WIDTH 28 |
| 12612 | #define GMMx28C8_Reserved_31_4_MASK 0xfffffff0 |
| 12613 | |
| 12614 | /// GMMx28C8 |
| 12615 | typedef union { |
| 12616 | struct { ///< |
| 12617 | UINT32 Delay:4 ; ///< |
| 12618 | UINT32 Reserved_31_4:28; ///< |
| 12619 | } Field; ///< |
| 12620 | UINT32 Value; ///< |
| 12621 | } GMMx28C8_STRUCT; |
| 12622 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 12623 | // **** GMMx28D8 Register Definition **** |
| 12624 | // Address |
| 12625 | #define GMMx28D8_ADDRESS 0x28d8 |
| 12626 | |
| 12627 | // Type |
| 12628 | #define GMMx28D8_TYPE TYPE_GMM |
| 12629 | // Field Data |
| 12630 | #define GMMx28D8_ActRd_OFFSET 0 |
| 12631 | #define GMMx28D8_ActRd_WIDTH 8 |
| 12632 | #define GMMx28D8_ActRd_MASK 0xff |
| 12633 | #define GMMx28D8_ActWr_OFFSET 8 |
| 12634 | #define GMMx28D8_ActWr_WIDTH 8 |
| 12635 | #define GMMx28D8_ActWr_MASK 0xff00 |
| 12636 | #define GMMx28D8_RasMActRd_OFFSET 16 |
| 12637 | #define GMMx28D8_RasMActRd_WIDTH 8 |
| 12638 | #define GMMx28D8_RasMActRd_MASK 0xff0000 |
| 12639 | #define GMMx28D8_RasMActWr_OFFSET 24 |
| 12640 | #define GMMx28D8_RasMActWr_WIDTH 8 |
| 12641 | #define GMMx28D8_RasMActWr_MASK 0xff000000 |
| 12642 | |
| 12643 | /// GMMx28D8 |
| 12644 | typedef union { |
| 12645 | struct { ///< |
| 12646 | UINT32 ActRd:8 ; ///< |
| 12647 | UINT32 ActWr:8 ; ///< |
| 12648 | UINT32 RasMActRd:8 ; ///< |
| 12649 | UINT32 RasMActWr:8 ; ///< |
| 12650 | } Field; ///< |
| 12651 | UINT32 Value; ///< |
| 12652 | } GMMx28D8_STRUCT; |
| 12653 | |
| 12654 | // **** GMMx28DC Register Definition **** |
| 12655 | // Address |
| 12656 | #define GMMx28DC_ADDRESS 0x28dc |
| 12657 | |
| 12658 | // Type |
| 12659 | #define GMMx28DC_TYPE TYPE_GMM |
| 12660 | // Field Data |
| 12661 | #define GMMx28DC_Ras2Ras_OFFSET 0 |
| 12662 | #define GMMx28DC_Ras2Ras_WIDTH 8 |
| 12663 | #define GMMx28DC_Ras2Ras_MASK 0xff |
| 12664 | #define GMMx28DC_Rp_OFFSET 8 |
| 12665 | #define GMMx28DC_Rp_WIDTH 8 |
| 12666 | #define GMMx28DC_Rp_MASK 0xff00 |
| 12667 | #define GMMx28DC_WrPlusRp_OFFSET 16 |
| 12668 | #define GMMx28DC_WrPlusRp_WIDTH 8 |
| 12669 | #define GMMx28DC_WrPlusRp_MASK 0xff0000 |
| 12670 | #define GMMx28DC_BusTurn_OFFSET 24 |
| 12671 | #define GMMx28DC_BusTurn_WIDTH 8 |
| 12672 | #define GMMx28DC_BusTurn_MASK 0xff000000 |
| 12673 | |
| 12674 | /// GMMx28DC |
| 12675 | typedef union { |
| 12676 | struct { ///< |
| 12677 | UINT32 Ras2Ras:8 ; ///< |
| 12678 | UINT32 Rp:8 ; ///< |
| 12679 | UINT32 WrPlusRp:8 ; ///< |
| 12680 | UINT32 BusTurn:8 ; ///< |
| 12681 | } Field; ///< |
| 12682 | UINT32 Value; ///< |
| 12683 | } GMMx28DC_STRUCT; |
| 12684 | |
| 12685 | // **** GMMx2B8C Register Definition **** |
| 12686 | // Address |
| 12687 | #define GMMx2B8C_ADDRESS 0x2b8c |
| 12688 | |
| 12689 | // Type |
| 12690 | #define GMMx2B8C_TYPE TYPE_GMM |
| 12691 | // Field Data |
| 12692 | #define GMMx2B8C_RengRamIndex_OFFSET 0 |
| 12693 | #define GMMx2B8C_RengRamIndex_WIDTH 10 |
| 12694 | #define GMMx2B8C_RengRamIndex_MASK 0x3ff |
| 12695 | #define GMMx2B8C_Reserved_31_10_OFFSET 10 |
| 12696 | #define GMMx2B8C_Reserved_31_10_WIDTH 22 |
| 12697 | #define GMMx2B8C_Reserved_31_10_MASK 0xfffffc00 |
| 12698 | |
| 12699 | /// GMMx2B8C |
| 12700 | typedef union { |
| 12701 | struct { ///< |
| 12702 | UINT32 RengRamIndex:10; ///< |
| 12703 | UINT32 Reserved_31_10:22; ///< |
| 12704 | } Field; ///< |
| 12705 | UINT32 Value; ///< |
| 12706 | } GMMx2B8C_STRUCT; |
| 12707 | |
| 12708 | // **** GMMx2B90 Register Definition **** |
| 12709 | // Address |
| 12710 | #define GMMx2B90_ADDRESS 0x2b90 |
| 12711 | |
| 12712 | // Type |
| 12713 | #define GMMx2B90_TYPE TYPE_GMM |
| 12714 | // Field Data |
| 12715 | #define GMMx2B90_RengRamData_OFFSET 0 |
| 12716 | #define GMMx2B90_RengRamData_WIDTH 32 |
| 12717 | #define GMMx2B90_RengRamData_MASK 0xffffffff |
| 12718 | |
| 12719 | /// GMMx2B90 |
| 12720 | typedef union { |
| 12721 | struct { ///< |
| 12722 | UINT32 RengRamData:32; ///< |
| 12723 | } Field; ///< |
| 12724 | UINT32 Value; ///< |
| 12725 | } GMMx2B90_STRUCT; |
| 12726 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12727 | // **** GMMx2B94 Register Definition **** |
| 12728 | // Address |
| 12729 | #define GMMx2B94_ADDRESS 0x2b94 |
| 12730 | |
| 12731 | // Type |
| 12732 | #define GMMx2B94_TYPE TYPE_GMM |
| 12733 | // Field Data |
| 12734 | #define GMMx2B94_RengExecuteOnPwrUp_OFFSET 0 |
| 12735 | #define GMMx2B94_RengExecuteOnPwrUp_WIDTH 1 |
| 12736 | #define GMMx2B94_RengExecuteOnPwrUp_MASK 0x1 |
| 12737 | #define GMMx2B94_Reserved_31_1_OFFSET 1 |
| 12738 | #define GMMx2B94_Reserved_31_1_WIDTH 31 |
| 12739 | #define GMMx2B94_Reserved_31_1_MASK 0xfffffffe |
| 12740 | |
| 12741 | /// GMMx2B94 |
| 12742 | typedef union { |
| 12743 | struct { ///< |
| 12744 | UINT32 RengExecuteOnPwrUp:1 ; ///< |
| 12745 | UINT32 Reserved_31_1:31; ///< |
| 12746 | } Field; ///< |
| 12747 | UINT32 Value; ///< |
| 12748 | } GMMx2B94_STRUCT; |
| 12749 | |
| 12750 | // **** GMMx2B98 Register Definition **** |
| 12751 | // Address |
| 12752 | #define GMMx2B98_ADDRESS 0x2b98 |
| 12753 | // Type |
| 12754 | #define GMMx2B98_TYPE TYPE_GMM |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 12755 | // **** GMMx2C04 Register Definition **** |
| 12756 | // Address |
| 12757 | #define GMMx2C04_ADDRESS 0x2c04 |
| 12758 | |
| 12759 | // Type |
| 12760 | #define GMMx2C04_TYPE TYPE_GMM |
| 12761 | // Field Data |
| 12762 | #define GMMx2C04_NonsurfBase_OFFSET 0 |
| 12763 | #define GMMx2C04_NonsurfBase_WIDTH 28 |
| 12764 | #define GMMx2C04_NonsurfBase_MASK 0xfffffff |
| 12765 | #define GMMx2C04_Reserved_31_28_OFFSET 28 |
| 12766 | #define GMMx2C04_Reserved_31_28_WIDTH 4 |
| 12767 | #define GMMx2C04_Reserved_31_28_MASK 0xf0000000 |
| 12768 | |
| 12769 | /// GMMx2C04 |
| 12770 | typedef union { |
| 12771 | struct { ///< |
| 12772 | UINT32 NonsurfBase:28; ///< |
| 12773 | UINT32 Reserved_31_28:4 ; ///< |
| 12774 | } Field; ///< |
| 12775 | UINT32 Value; ///< |
| 12776 | } GMMx2C04_STRUCT; |
| 12777 | |
| 12778 | // **** GMMx5428 Register Definition **** |
| 12779 | // Address |
| 12780 | #define GMMx5428_ADDRESS 0x5428 |
| 12781 | |
| 12782 | // Type |
| 12783 | #define GMMx5428_TYPE TYPE_GMM |
| 12784 | // Field Data |
| 12785 | #define GMMx5428_ConfigMemsize_OFFSET 0 |
| 12786 | #define GMMx5428_ConfigMemsize_WIDTH 32 |
| 12787 | #define GMMx5428_ConfigMemsize_MASK 0xffffffff |
| 12788 | |
| 12789 | /// GMMx5428 |
| 12790 | typedef union { |
| 12791 | struct { ///< |
| 12792 | UINT32 ConfigMemsize:32; ///< |
| 12793 | } Field; ///< |
| 12794 | UINT32 Value; ///< |
| 12795 | } GMMx5428_STRUCT; |
| 12796 | |
| 12797 | // **** GMMx5490 Register Definition **** |
| 12798 | // Address |
| 12799 | #define GMMx5490_ADDRESS 0x5490 |
| 12800 | |
| 12801 | // Type |
| 12802 | #define GMMx5490_TYPE TYPE_GMM |
| 12803 | // Field Data |
| 12804 | #define GMMx5490_FbReadEn_OFFSET 0 |
| 12805 | #define GMMx5490_FbReadEn_WIDTH 1 |
| 12806 | #define GMMx5490_FbReadEn_MASK 0x1 |
| 12807 | #define GMMx5490_FbWriteEn_OFFSET 1 |
| 12808 | #define GMMx5490_FbWriteEn_WIDTH 1 |
| 12809 | #define GMMx5490_FbWriteEn_MASK 0x2 |
| 12810 | #define GMMx5490_Reserved_31_2_OFFSET 2 |
| 12811 | #define GMMx5490_Reserved_31_2_WIDTH 30 |
| 12812 | #define GMMx5490_Reserved_31_2_MASK 0xfffffffc |
| 12813 | |
| 12814 | /// GMMx5490 |
| 12815 | typedef union { |
| 12816 | struct { ///< |
| 12817 | UINT32 FbReadEn:1 ; ///< |
| 12818 | UINT32 FbWriteEn:1 ; ///< |
| 12819 | UINT32 Reserved_31_2:30; ///< |
| 12820 | } Field; ///< |
| 12821 | UINT32 Value; ///< |
| 12822 | } GMMx5490_STRUCT; |
| 12823 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 12824 | // **** SMUx0B Register Definition **** |
| 12825 | // Address |
| 12826 | #define SMUx0B_ADDRESS 0xb |
| 12827 | |
| 12828 | // Type |
| 12829 | #define SMUx0B_TYPE TYPE_SMU |
| 12830 | // Field Data |
| 12831 | #define SMUx0B_MemAddr_OFFSET 0 |
| 12832 | #define SMUx0B_MemAddr_WIDTH 16 |
| 12833 | #define SMUx0B_MemAddr_MASK 0xffff |
| 12834 | |
| 12835 | /// SMUx0B |
| 12836 | typedef union { |
| 12837 | struct { ///< |
| 12838 | UINT32 MemAddr:16; ///< |
| 12839 | } Field; ///< |
| 12840 | UINT32 Value; ///< |
| 12841 | } SMUx0B_STRUCT; |
| 12842 | |
| 12843 | // **** MSRC001_001A Register Definition **** |
| 12844 | // Address |
| 12845 | #define MSRC001_001A_ADDRESS 0xc001001a |
| 12846 | |
| 12847 | // Type |
| 12848 | #define MSRC001_001A_TYPE TYPE_MSR |
| 12849 | // Field Data |
| 12850 | #define MSRC001_001A_RAZ_22_0_OFFSET 0 |
| 12851 | #define MSRC001_001A_RAZ_22_0_WIDTH 23 |
| 12852 | #define MSRC001_001A_RAZ_22_0_MASK 0x7fffff |
| 12853 | #define MSRC001_001A_TOM_35_23__OFFSET 23 |
| 12854 | #define MSRC001_001A_TOM_35_23__WIDTH 13 |
| 12855 | #define MSRC001_001A_TOM_35_23__MASK 0xfff800000 |
| 12856 | #define MSRC001_001A_RAZ_63_36_OFFSET 36 |
| 12857 | #define MSRC001_001A_RAZ_63_36_WIDTH 28 |
| 12858 | #define MSRC001_001A_RAZ_63_36_MASK 0xfffffff000000000 |
| 12859 | |
| 12860 | /// MSRC001_001A |
| 12861 | typedef union { |
| 12862 | struct { ///< |
| 12863 | UINT64 RAZ_22_0:23; ///< |
| 12864 | UINT64 TOM_35_23_:13; ///< |
| 12865 | UINT64 RAZ_63_36:28; ///< |
| 12866 | } Field; ///< |
| 12867 | UINT64 Value; ///< |
| 12868 | } MSRC001_001A_STRUCT; |
| 12869 | |
| 12870 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 12871 | |
| 12872 | // **** FCRxFF30_0134(GMMx4D0) Register Definition **** |
| 12873 | // Address |
| 12874 | #define FCRxFF30_0134_ADDRESS 0xff300134 |
| 12875 | |
| 12876 | // Field Data |
| 12877 | #define FCRxFF30_0134_DispclkDccgGateDisable_OFFSET 0 |
| 12878 | #define FCRxFF30_0134_DispclkDccgGateDisable_WIDTH 1 |
| 12879 | #define FCRxFF30_0134_DispclkDccgGateDisable_MASK 0x1 |
| 12880 | #define FCRxFF30_0134_DispclkRDccgGateDisable_OFFSET 1 |
| 12881 | #define FCRxFF30_0134_DispclkRDccgGateDisable_WIDTH 1 |
| 12882 | #define FCRxFF30_0134_DispclkRDccgGateDisable_MASK 0x2 |
| 12883 | #define FCRxFF30_0134_SclkGateDisable_OFFSET 2 |
| 12884 | #define FCRxFF30_0134_SclkGateDisable_WIDTH 1 |
| 12885 | #define FCRxFF30_0134_SclkGateDisable_MASK 0x4 |
| 12886 | #define FCRxFF30_0134_Reserved_7_3_OFFSET 3 |
| 12887 | #define FCRxFF30_0134_Reserved_7_3_WIDTH 5 |
| 12888 | #define FCRxFF30_0134_Reserved_7_3_MASK 0xf8 |
| 12889 | #define FCRxFF30_0134_SymclkaGateDisable_OFFSET 8 |
| 12890 | #define FCRxFF30_0134_SymclkaGateDisable_WIDTH 1 |
| 12891 | #define FCRxFF30_0134_SymclkaGateDisable_MASK 0x100 |
| 12892 | #define FCRxFF30_0134_SymclkbGateDisable_OFFSET 9 |
| 12893 | #define FCRxFF30_0134_SymclkbGateDisable_WIDTH 1 |
| 12894 | #define FCRxFF30_0134_SymclkbGateDisable_MASK 0x200 |
| 12895 | #define FCRxFF30_0134_Reserved_31_10_OFFSET 10 |
| 12896 | #define FCRxFF30_0134_Reserved_31_10_WIDTH 22 |
| 12897 | #define FCRxFF30_0134_Reserved_31_10_MASK 0xfffffc00 |
| 12898 | |
| 12899 | /// FCRxFF30_0134 |
| 12900 | typedef union { |
| 12901 | struct { ///< |
| 12902 | UINT32 DispclkDccgGateDisable:1 ; ///< |
| 12903 | UINT32 DispclkRDccgGateDisable:1 ; ///< |
| 12904 | UINT32 SclkGateDisable:1 ; ///< |
| 12905 | UINT32 Reserved_7_3:5 ; ///< |
| 12906 | UINT32 SymclkaGateDisable:1 ; ///< |
| 12907 | UINT32 SymclkbGateDisable:1 ; ///< |
| 12908 | UINT32 Reserved_31_10:22; ///< |
| 12909 | } Field; ///< |
| 12910 | UINT32 Value; ///< |
| 12911 | } FCRxFF30_0134_STRUCT; |
| 12912 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12913 | // **** FCRxFF30_01F4 Register Definition **** |
| 12914 | // Address |
| 12915 | #define FCRxFF30_01F4_ADDRESS 0xff3001f4 |
| 12916 | |
| 12917 | // Type |
| 12918 | #define FCRxFF30_01F4_TYPE TYPE_FCR |
| 12919 | // Field Data |
| 12920 | #define FCRxFF30_01F4_CgRlcCgttSclkOverride_OFFSET 0 |
| 12921 | #define FCRxFF30_01F4_CgRlcCgttSclkOverride_WIDTH 1 |
| 12922 | #define FCRxFF30_01F4_CgRlcCgttSclkOverride_MASK 0x1 |
| 12923 | #define FCRxFF30_01F4_CgCpCgttSclkOverride_OFFSET 1 |
| 12924 | #define FCRxFF30_01F4_CgCpCgttSclkOverride_WIDTH 1 |
| 12925 | #define FCRxFF30_01F4_CgCpCgttSclkOverride_MASK 0x2 |
| 12926 | #define FCRxFF30_01F4_CgVgtCgttSclkOverride_OFFSET 2 |
| 12927 | #define FCRxFF30_01F4_CgVgtCgttSclkOverride_WIDTH 1 |
| 12928 | #define FCRxFF30_01F4_CgVgtCgttSclkOverride_MASK 0x4 |
| 12929 | #define FCRxFF30_01F4_CgPaCgttSclkOverride_OFFSET 3 |
| 12930 | #define FCRxFF30_01F4_CgPaCgttSclkOverride_WIDTH 1 |
| 12931 | #define FCRxFF30_01F4_CgPaCgttSclkOverride_MASK 0x8 |
| 12932 | #define FCRxFF30_01F4_CgScCgttSclkOverride_OFFSET 4 |
| 12933 | #define FCRxFF30_01F4_CgScCgttSclkOverride_WIDTH 1 |
| 12934 | #define FCRxFF30_01F4_CgScCgttSclkOverride_MASK 0x10 |
| 12935 | #define FCRxFF30_01F4_CgSpimCgttSclkOverride_OFFSET 5 |
| 12936 | #define FCRxFF30_01F4_CgSpimCgttSclkOverride_WIDTH 1 |
| 12937 | #define FCRxFF30_01F4_CgSpimCgttSclkOverride_MASK 0x20 |
| 12938 | #define FCRxFF30_01F4_CgSxmCgttSclkOverride_OFFSET 6 |
| 12939 | #define FCRxFF30_01F4_CgSxmCgttSclkOverride_WIDTH 1 |
| 12940 | #define FCRxFF30_01F4_CgSxmCgttSclkOverride_MASK 0x40 |
| 12941 | #define FCRxFF30_01F4_CgSxsCgttSclkOverride_OFFSET 7 |
| 12942 | #define FCRxFF30_01F4_CgSxsCgttSclkOverride_WIDTH 1 |
| 12943 | #define FCRxFF30_01F4_CgSxsCgttSclkOverride_MASK 0x80 |
| 12944 | #define FCRxFF30_01F4_CgCb0CgttSclkOverride_OFFSET 8 |
| 12945 | #define FCRxFF30_01F4_CgCb0CgttSclkOverride_WIDTH 1 |
| 12946 | #define FCRxFF30_01F4_CgCb0CgttSclkOverride_MASK 0x100 |
| 12947 | #define FCRxFF30_01F4_CgCb1CgttSclkOverride_OFFSET 9 |
| 12948 | #define FCRxFF30_01F4_CgCb1CgttSclkOverride_WIDTH 1 |
| 12949 | #define FCRxFF30_01F4_CgCb1CgttSclkOverride_MASK 0x200 |
| 12950 | #define FCRxFF30_01F4_ReservedCgtt10Override_OFFSET 10 |
| 12951 | #define FCRxFF30_01F4_ReservedCgtt10Override_WIDTH 1 |
| 12952 | #define FCRxFF30_01F4_ReservedCgtt10Override_MASK 0x400 |
| 12953 | #define FCRxFF30_01F4_ReservedCgtt11Override_OFFSET 11 |
| 12954 | #define FCRxFF30_01F4_ReservedCgtt11Override_WIDTH 1 |
| 12955 | #define FCRxFF30_01F4_ReservedCgtt11Override_MASK 0x800 |
| 12956 | #define FCRxFF30_01F4_CgDb0CgttSclkOverride_OFFSET 12 |
| 12957 | #define FCRxFF30_01F4_CgDb0CgttSclkOverride_WIDTH 1 |
| 12958 | #define FCRxFF30_01F4_CgDb0CgttSclkOverride_MASK 0x1000 |
| 12959 | #define FCRxFF30_01F4_CgDb1CgttSclkOverride_OFFSET 13 |
| 12960 | #define FCRxFF30_01F4_CgDb1CgttSclkOverride_WIDTH 1 |
| 12961 | #define FCRxFF30_01F4_CgDb1CgttSclkOverride_MASK 0x2000 |
| 12962 | #define FCRxFF30_01F4_ReservedCgtt14Override_OFFSET 14 |
| 12963 | #define FCRxFF30_01F4_ReservedCgtt14Override_WIDTH 1 |
| 12964 | #define FCRxFF30_01F4_ReservedCgtt14Override_MASK 0x4000 |
| 12965 | #define FCRxFF30_01F4_ReservedCgtt15Override_OFFSET 15 |
| 12966 | #define FCRxFF30_01F4_ReservedCgtt15Override_WIDTH 1 |
| 12967 | #define FCRxFF30_01F4_ReservedCgtt15Override_MASK 0x8000 |
| 12968 | #define FCRxFF30_01F4_CgVcCgttSclkOverride_OFFSET 16 |
| 12969 | #define FCRxFF30_01F4_CgVcCgttSclkOverride_WIDTH 1 |
| 12970 | #define FCRxFF30_01F4_CgVcCgttSclkOverride_MASK 0x10000 |
| 12971 | #define FCRxFF30_01F4_CgAvpCgttSclkOverride_OFFSET 17 |
| 12972 | #define FCRxFF30_01F4_CgAvpCgttSclkOverride_WIDTH 1 |
| 12973 | #define FCRxFF30_01F4_CgAvpCgttSclkOverride_MASK 0x20000 |
| 12974 | #define FCRxFF30_01F4_CgAvpCgttEclkOverride_OFFSET 18 |
| 12975 | #define FCRxFF30_01F4_CgAvpCgttEclkOverride_WIDTH 1 |
| 12976 | #define FCRxFF30_01F4_CgAvpCgttEclkOverride_MASK 0x40000 |
| 12977 | #define FCRxFF30_01F4_CgUvdmCgttSclkOverride_OFFSET 19 |
| 12978 | #define FCRxFF30_01F4_CgUvdmCgttSclkOverride_WIDTH 1 |
| 12979 | #define FCRxFF30_01F4_CgUvdmCgttSclkOverride_MASK 0x80000 |
| 12980 | #define FCRxFF30_01F4_CgUvdmCgttVclkOverride_OFFSET 20 |
| 12981 | #define FCRxFF30_01F4_CgUvdmCgttVclkOverride_WIDTH 1 |
| 12982 | #define FCRxFF30_01F4_CgUvdmCgttVclkOverride_MASK 0x100000 |
| 12983 | #define FCRxFF30_01F4_CgUvdmCgttDclkOverride_OFFSET 21 |
| 12984 | #define FCRxFF30_01F4_CgUvdmCgttDclkOverride_WIDTH 1 |
| 12985 | #define FCRxFF30_01F4_CgUvdmCgttDclkOverride_MASK 0x200000 |
| 12986 | #define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 |
| 12987 | #define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 |
| 12988 | #define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 |
| 12989 | #define FCRxFF30_01F4_CgRomCgttSclkOverride_OFFSET 23 |
| 12990 | #define FCRxFF30_01F4_CgRomCgttSclkOverride_WIDTH 1 |
| 12991 | #define FCRxFF30_01F4_CgRomCgttSclkOverride_MASK 0x800000 |
| 12992 | #define FCRxFF30_01F4_CgDrmCgttSclkOverride_OFFSET 24 |
| 12993 | #define FCRxFF30_01F4_CgDrmCgttSclkOverride_WIDTH 1 |
| 12994 | #define FCRxFF30_01F4_CgDrmCgttSclkOverride_MASK 0x1000000 |
| 12995 | #define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 |
| 12996 | #define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 |
| 12997 | #define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 |
| 12998 | #define FCRxFF30_01F4_ReservedCgtt26Override_OFFSET 26 |
| 12999 | #define FCRxFF30_01F4_ReservedCgtt26Override_WIDTH 1 |
| 13000 | #define FCRxFF30_01F4_ReservedCgtt26Override_MASK 0x4000000 |
| 13001 | #define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 |
| 13002 | #define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 |
| 13003 | #define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 |
| 13004 | #define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 |
| 13005 | #define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 |
| 13006 | #define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 |
| 13007 | #define FCRxFF30_01F4_ReservedCgtt29Override_OFFSET 29 |
| 13008 | #define FCRxFF30_01F4_ReservedCgtt29Override_WIDTH 1 |
| 13009 | #define FCRxFF30_01F4_ReservedCgtt29Override_MASK 0x20000000 |
| 13010 | #define FCRxFF30_01F4_ReservedCgtt30Override_OFFSET 30 |
| 13011 | #define FCRxFF30_01F4_ReservedCgtt30Override_WIDTH 1 |
| 13012 | #define FCRxFF30_01F4_ReservedCgtt30Override_MASK 0x40000000 |
| 13013 | #define FCRxFF30_01F4_ReservedCgtt31Override_OFFSET 31 |
| 13014 | #define FCRxFF30_01F4_ReservedCgtt31Override_WIDTH 1 |
| 13015 | #define FCRxFF30_01F4_ReservedCgtt31Override_MASK 0x80000000 |
| 13016 | |
| 13017 | /// FCRxFF30_01F4 |
| 13018 | typedef union { |
| 13019 | struct { ///< |
| 13020 | UINT32 CgRlcCgttSclkOverride:1 ; ///< |
| 13021 | UINT32 CgCpCgttSclkOverride:1 ; ///< |
| 13022 | UINT32 CgVgtCgttSclkOverride:1 ; ///< |
| 13023 | UINT32 CgPaCgttSclkOverride:1 ; ///< |
| 13024 | UINT32 CgScCgttSclkOverride:1 ; ///< |
| 13025 | UINT32 CgSpimCgttSclkOverride:1 ; ///< |
| 13026 | UINT32 CgSxmCgttSclkOverride:1 ; ///< |
| 13027 | UINT32 CgSxsCgttSclkOverride:1 ; ///< |
| 13028 | UINT32 CgCb0CgttSclkOverride:1 ; ///< |
| 13029 | UINT32 CgCb1CgttSclkOverride:1 ; ///< |
| 13030 | UINT32 ReservedCgtt10Override:1 ; ///< |
| 13031 | UINT32 ReservedCgtt11Override:1 ; ///< |
| 13032 | UINT32 CgDb0CgttSclkOverride:1 ; ///< |
| 13033 | UINT32 CgDb1CgttSclkOverride:1 ; ///< |
| 13034 | UINT32 ReservedCgtt14Override:1 ; ///< |
| 13035 | UINT32 ReservedCgtt15Override:1 ; ///< |
| 13036 | UINT32 CgVcCgttSclkOverride:1 ; ///< |
| 13037 | UINT32 CgAvpCgttSclkOverride:1 ; ///< |
| 13038 | UINT32 CgAvpCgttEclkOverride:1 ; ///< |
| 13039 | UINT32 CgUvdmCgttSclkOverride:1 ; ///< |
| 13040 | UINT32 CgUvdmCgttVclkOverride:1 ; ///< |
| 13041 | UINT32 CgUvdmCgttDclkOverride:1 ; ///< |
| 13042 | UINT32 CgBifCgttSclkOverride:1 ; ///< |
| 13043 | UINT32 CgRomCgttSclkOverride:1 ; ///< |
| 13044 | UINT32 CgDrmCgttSclkOverride:1 ; ///< |
| 13045 | UINT32 CgDcCgttSclkOverride:1 ; ///< |
| 13046 | UINT32 ReservedCgtt26Override:1 ; ///< |
| 13047 | UINT32 CgMcbCgttSclkOverride:1 ; ///< |
| 13048 | UINT32 CgMcdwCgttSclkOverride:1 ; ///< |
| 13049 | UINT32 ReservedCgtt29Override:1 ; ///< |
| 13050 | UINT32 ReservedCgtt30Override:1 ; ///< |
| 13051 | UINT32 ReservedCgtt31Override:1 ; ///< |
| 13052 | } Field; ///< |
| 13053 | UINT32 Value; ///< |
| 13054 | } FCRxFF30_01F4_STRUCT; |
| 13055 | |
| 13056 | // **** FCRxFF30_01F5 Register Definition **** |
| 13057 | // Address |
| 13058 | #define FCRxFF30_01F5_ADDRESS 0xff3001f5 |
| 13059 | |
| 13060 | // Type |
| 13061 | #define FCRxFF30_01F5_TYPE TYPE_FCR |
| 13062 | // Field Data |
| 13063 | #define FCRxFF30_01F5_ReservedCgtt32Override_OFFSET 0 |
| 13064 | #define FCRxFF30_01F5_ReservedCgtt32Override_WIDTH 1 |
| 13065 | #define FCRxFF30_01F5_ReservedCgtt32Override_MASK 0x1 |
| 13066 | #define FCRxFF30_01F5_ReservedCgtt33Override_OFFSET 1 |
| 13067 | #define FCRxFF30_01F5_ReservedCgtt33Override_WIDTH 1 |
| 13068 | #define FCRxFF30_01F5_ReservedCgtt33Override_MASK 0x2 |
| 13069 | #define FCRxFF30_01F5_ReservedCgtt34Override_OFFSET 2 |
| 13070 | #define FCRxFF30_01F5_ReservedCgtt34Override_WIDTH 1 |
| 13071 | #define FCRxFF30_01F5_ReservedCgtt34Override_MASK 0x4 |
| 13072 | #define FCRxFF30_01F5_ReservedCgtt35Override_OFFSET 3 |
| 13073 | #define FCRxFF30_01F5_ReservedCgtt35Override_WIDTH 1 |
| 13074 | #define FCRxFF30_01F5_ReservedCgtt35Override_MASK 0x8 |
| 13075 | #define FCRxFF30_01F5_CgTaCgttSclkOverride_OFFSET 4 |
| 13076 | #define FCRxFF30_01F5_CgTaCgttSclkOverride_WIDTH 1 |
| 13077 | #define FCRxFF30_01F5_CgTaCgttSclkOverride_MASK 0x10 |
| 13078 | #define FCRxFF30_01F5_CgTdCgttSclkOverride_OFFSET 5 |
| 13079 | #define FCRxFF30_01F5_CgTdCgttSclkOverride_WIDTH 1 |
| 13080 | #define FCRxFF30_01F5_CgTdCgttSclkOverride_MASK 0x20 |
| 13081 | #define FCRxFF30_01F5_CgTcaCgttSclkOverride_OFFSET 6 |
| 13082 | #define FCRxFF30_01F5_CgTcaCgttSclkOverride_WIDTH 1 |
| 13083 | #define FCRxFF30_01F5_CgTcaCgttSclkOverride_MASK 0x40 |
| 13084 | #define FCRxFF30_01F5_CgTcpCgttSclkOverride_OFFSET 7 |
| 13085 | #define FCRxFF30_01F5_CgTcpCgttSclkOverride_WIDTH 1 |
| 13086 | #define FCRxFF30_01F5_CgTcpCgttSclkOverride_MASK 0x80 |
| 13087 | #define FCRxFF30_01F5_CgTccCgttSclkOverride_OFFSET 8 |
| 13088 | #define FCRxFF30_01F5_CgTccCgttSclkOverride_WIDTH 1 |
| 13089 | #define FCRxFF30_01F5_CgTccCgttSclkOverride_MASK 0x100 |
| 13090 | #define FCRxFF30_01F5_CgSqCgttSclkOverride_OFFSET 9 |
| 13091 | #define FCRxFF30_01F5_CgSqCgttSclkOverride_WIDTH 1 |
| 13092 | #define FCRxFF30_01F5_CgSqCgttSclkOverride_MASK 0x200 |
| 13093 | #define FCRxFF30_01F5_CgHdpCgttSclkOverride_OFFSET 10 |
| 13094 | #define FCRxFF30_01F5_CgHdpCgttSclkOverride_WIDTH 1 |
| 13095 | #define FCRxFF30_01F5_CgHdpCgttSclkOverride_MASK 0x400 |
| 13096 | #define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 |
| 13097 | #define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 |
| 13098 | #define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 |
| 13099 | #define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 |
| 13100 | #define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 |
| 13101 | #define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 |
| 13102 | #define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 |
| 13103 | #define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 |
| 13104 | #define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 |
| 13105 | #define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 |
| 13106 | #define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 |
| 13107 | #define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 |
| 13108 | #define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 |
| 13109 | #define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 |
| 13110 | #define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 |
| 13111 | #define FCRxFF30_01F5_CgGrbmCgttSclkOverride_OFFSET 16 |
| 13112 | #define FCRxFF30_01F5_CgGrbmCgttSclkOverride_WIDTH 1 |
| 13113 | #define FCRxFF30_01F5_CgGrbmCgttSclkOverride_MASK 0x10000 |
| 13114 | #define FCRxFF30_01F5_ReservedCgtt49Override_OFFSET 17 |
| 13115 | #define FCRxFF30_01F5_ReservedCgtt49Override_WIDTH 1 |
| 13116 | #define FCRxFF30_01F5_ReservedCgtt49Override_MASK 0x20000 |
| 13117 | #define FCRxFF30_01F5_CgSmuCgttSclkOverride_OFFSET 18 |
| 13118 | #define FCRxFF30_01F5_CgSmuCgttSclkOverride_WIDTH 1 |
| 13119 | #define FCRxFF30_01F5_CgSmuCgttSclkOverride_MASK 0x40000 |
| 13120 | #define FCRxFF30_01F5_ReservedCgtt51Override_OFFSET 19 |
| 13121 | #define FCRxFF30_01F5_ReservedCgtt51Override_WIDTH 1 |
| 13122 | #define FCRxFF30_01F5_ReservedCgtt51Override_MASK 0x80000 |
| 13123 | #define FCRxFF30_01F5_CgIhCgttSclkOverride_OFFSET 20 |
| 13124 | #define FCRxFF30_01F5_CgIhCgttSclkOverride_WIDTH 1 |
| 13125 | #define FCRxFF30_01F5_CgIhCgttSclkOverride_MASK 0x100000 |
| 13126 | #define FCRxFF30_01F5_CgDbgCgttSclkOverride_OFFSET 21 |
| 13127 | #define FCRxFF30_01F5_CgDbgCgttSclkOverride_WIDTH 1 |
| 13128 | #define FCRxFF30_01F5_CgDbgCgttSclkOverride_MASK 0x200000 |
| 13129 | #define FCRxFF30_01F5_CgSemCgttSclkOverride_OFFSET 22 |
| 13130 | #define FCRxFF30_01F5_CgSemCgttSclkOverride_WIDTH 1 |
| 13131 | #define FCRxFF30_01F5_CgSemCgttSclkOverride_MASK 0x400000 |
| 13132 | #define FCRxFF30_01F5_CgSrbmCgttSclkOverride_OFFSET 23 |
| 13133 | #define FCRxFF30_01F5_CgSrbmCgttSclkOverride_WIDTH 1 |
| 13134 | #define FCRxFF30_01F5_CgSrbmCgttSclkOverride_MASK 0x800000 |
| 13135 | #define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_OFFSET 24 |
| 13136 | #define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_WIDTH 1 |
| 13137 | #define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_MASK 0x1000000 |
| 13138 | #define FCRxFF30_01F5_CgUvduCgttSclkOverride_OFFSET 25 |
| 13139 | #define FCRxFF30_01F5_CgUvduCgttSclkOverride_WIDTH 1 |
| 13140 | #define FCRxFF30_01F5_CgUvduCgttSclkOverride_MASK 0x2000000 |
| 13141 | #define FCRxFF30_01F5_CgUvduCgttVclkOverride_OFFSET 26 |
| 13142 | #define FCRxFF30_01F5_CgUvduCgttVclkOverride_WIDTH 1 |
| 13143 | #define FCRxFF30_01F5_CgUvduCgttVclkOverride_MASK 0x4000000 |
| 13144 | #define FCRxFF30_01F5_CgUvduCgttDclkOverride_OFFSET 27 |
| 13145 | #define FCRxFF30_01F5_CgUvduCgttDclkOverride_WIDTH 1 |
| 13146 | #define FCRxFF30_01F5_CgUvduCgttDclkOverride_MASK 0x8000000 |
| 13147 | #define FCRxFF30_01F5_CgDcCgttDispclkOverride_OFFSET 28 |
| 13148 | #define FCRxFF30_01F5_CgDcCgttDispclkOverride_WIDTH 1 |
| 13149 | #define FCRxFF30_01F5_CgDcCgttDispclkOverride_MASK 0x10000000 |
| 13150 | #define FCRxFF30_01F5_CgXbrCgttSclkOverride_OFFSET 29 |
| 13151 | #define FCRxFF30_01F5_CgXbrCgttSclkOverride_WIDTH 1 |
| 13152 | #define FCRxFF30_01F5_CgXbrCgttSclkOverride_MASK 0x20000000 |
| 13153 | #define FCRxFF30_01F5_CgSpimCgtsSclkOverride_OFFSET 30 |
| 13154 | #define FCRxFF30_01F5_CgSpimCgtsSclkOverride_WIDTH 1 |
| 13155 | #define FCRxFF30_01F5_CgSpimCgtsSclkOverride_MASK 0x40000000 |
| 13156 | #define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_OFFSET 31 |
| 13157 | #define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_WIDTH 1 |
| 13158 | #define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_MASK 0x80000000 |
| 13159 | |
| 13160 | /// FCRxFF30_01F5 |
| 13161 | typedef union { |
| 13162 | struct { ///< |
| 13163 | UINT32 ReservedCgtt32Override:1 ; ///< |
| 13164 | UINT32 ReservedCgtt33Override:1 ; ///< |
| 13165 | UINT32 ReservedCgtt34Override:1 ; ///< |
| 13166 | UINT32 ReservedCgtt35Override:1 ; ///< |
| 13167 | UINT32 CgTaCgttSclkOverride:1 ; ///< |
| 13168 | UINT32 CgTdCgttSclkOverride:1 ; ///< |
| 13169 | UINT32 CgTcaCgttSclkOverride:1 ; ///< |
| 13170 | UINT32 CgTcpCgttSclkOverride:1 ; ///< |
| 13171 | UINT32 CgTccCgttSclkOverride:1 ; ///< |
| 13172 | UINT32 CgSqCgttSclkOverride:1 ; ///< |
| 13173 | UINT32 CgHdpCgttSclkOverride:1 ; ///< |
| 13174 | UINT32 CgVmcCgttSclkOverride:1 ; ///< |
| 13175 | UINT32 CgOrbCgttSclkOverride:1 ; ///< |
| 13176 | UINT32 CgOrbCgttLclkOverride:1 ; ///< |
| 13177 | UINT32 CgIocCgttSclkOverride:1 ; ///< |
| 13178 | UINT32 CgIocCgttLclkOverride:1 ; ///< |
| 13179 | UINT32 CgGrbmCgttSclkOverride:1 ; ///< |
| 13180 | UINT32 ReservedCgtt49Override:1 ; ///< |
| 13181 | UINT32 CgSmuCgttSclkOverride:1 ; ///< |
| 13182 | UINT32 ReservedCgtt51Override:1 ; ///< |
| 13183 | UINT32 CgIhCgttSclkOverride:1 ; ///< |
| 13184 | UINT32 CgDbgCgttSclkOverride:1 ; ///< |
| 13185 | UINT32 CgSemCgttSclkOverride:1 ; ///< |
| 13186 | UINT32 CgSrbmCgttSclkOverride:1 ; ///< |
| 13187 | UINT32 CgDrmdmaCgttSclkOverride:1 ; ///< |
| 13188 | UINT32 CgUvduCgttSclkOverride:1 ; ///< |
| 13189 | UINT32 CgUvduCgttVclkOverride:1 ; ///< |
| 13190 | UINT32 CgUvduCgttDclkOverride:1 ; ///< |
| 13191 | UINT32 CgDcCgttDispclkOverride:1 ; ///< |
| 13192 | UINT32 CgXbrCgttSclkOverride:1 ; ///< |
| 13193 | UINT32 CgSpimCgtsSclkOverride:1 ; ///< |
| 13194 | UINT32 CgSpimCgtsSclkLsOverride:1 ; ///< |
| 13195 | } Field; ///< |
| 13196 | UINT32 Value; ///< |
| 13197 | } FCRxFF30_01F5_STRUCT; |
| 13198 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13199 | // **** FCRxFF30_1B7C(GMMx6DF0) Register Definition **** |
| 13200 | // Address |
| 13201 | #define FCRxFF30_1B7C_ADDRESS 0xff301B7C |
| 13202 | |
| 13203 | // Field Data |
| 13204 | #define FCRxFF30_1B7C_Reserved_3_0_OFFSET 0 |
| 13205 | #define FCRxFF30_1B7C_Reserved_3_0_WIDTH 4 |
| 13206 | #define FCRxFF30_1B7C_Reserved_3_0_MASK 0xf |
| 13207 | #define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_OFFSET 4 |
| 13208 | #define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_WIDTH 1 |
| 13209 | #define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_MASK 0x10 |
| 13210 | #define FCRxFF30_1B7C_Reserved_7_5_OFFSET 5 |
| 13211 | #define FCRxFF30_1B7C_Reserved_7_5_WIDTH 3 |
| 13212 | #define FCRxFF30_1B7C_Reserved_7_5_MASK 0xe0 |
| 13213 | #define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_OFFSET 8 |
| 13214 | #define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_WIDTH 1 |
| 13215 | #define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_MASK 0x100 |
| 13216 | #define FCRxFF30_1B7C_Reserved_11_9_OFFSET 9 |
| 13217 | #define FCRxFF30_1B7C_Reserved_11_9_WIDTH 3 |
| 13218 | #define FCRxFF30_1B7C_Reserved_11_9_MASK 0xe00 |
| 13219 | #define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_OFFSET 12 |
| 13220 | #define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_WIDTH 1 |
| 13221 | #define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_MASK 0x1000 |
| 13222 | #define FCRxFF30_1B7C_Reserved_31_13_OFFSET 13 |
| 13223 | #define FCRxFF30_1B7C_Reserved_31_13_WIDTH 19 |
| 13224 | #define FCRxFF30_1B7C_Reserved_31_13_MASK 0xffffe000 |
| 13225 | |
| 13226 | /// FCRxFF30_1B7C |
| 13227 | typedef union { |
| 13228 | struct { ///< |
| 13229 | UINT32 Reserved_3_0:4 ; ///< |
| 13230 | UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///< |
| 13231 | UINT32 Reserved_7_5:3 ; ///< |
| 13232 | UINT32 CrtcDispclkGDcpGateDisable:1 ; ///< |
| 13233 | UINT32 Reserved_11_9:3 ; ///< |
| 13234 | UINT32 CrtcDispclkGSclGateDisable:1 ; ///< |
| 13235 | UINT32 Reserved_31_13:19; ///< |
| 13236 | } Field; ///< |
| 13237 | UINT32 Value; ///< |
| 13238 | } FCRxFF30_1B7C_STRUCT; |
| 13239 | |
| 13240 | // **** FCRxFF30_1E7C(GMMx79F0) Register Definition **** |
| 13241 | // Address |
| 13242 | #define FCRxFF30_1E7C_ADDRESS 0xff301E7C |
| 13243 | |
| 13244 | // Field Data |
| 13245 | #define FCRxFF30_1E7C_Reserved_3_0_OFFSET 0 |
| 13246 | #define FCRxFF30_1E7C_Reserved_3_0_WIDTH 4 |
| 13247 | #define FCRxFF30_1E7C_Reserved_3_0_MASK 0xf |
| 13248 | #define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_OFFSET 4 |
| 13249 | #define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_WIDTH 1 |
| 13250 | #define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_MASK 0x10 |
| 13251 | #define FCRxFF30_1E7C_Reserved_7_5_OFFSET 5 |
| 13252 | #define FCRxFF30_1E7C_Reserved_7_5_WIDTH 3 |
| 13253 | #define FCRxFF30_1E7C_Reserved_7_5_MASK 0xe0 |
| 13254 | #define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_OFFSET 8 |
| 13255 | #define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_WIDTH 1 |
| 13256 | #define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_MASK 0x100 |
| 13257 | #define FCRxFF30_1E7C_Reserved_11_9_OFFSET 9 |
| 13258 | #define FCRxFF30_1E7C_Reserved_11_9_WIDTH 3 |
| 13259 | #define FCRxFF30_1E7C_Reserved_11_9_MASK 0xe00 |
| 13260 | #define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_OFFSET 12 |
| 13261 | #define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_WIDTH 1 |
| 13262 | #define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_MASK 0x1000 |
| 13263 | #define FCRxFF30_1E7C_Reserved_31_13_OFFSET 13 |
| 13264 | #define FCRxFF30_1E7C_Reserved_31_13_WIDTH 19 |
| 13265 | #define FCRxFF30_1E7C_Reserved_31_13_MASK 0xffffe000 |
| 13266 | |
| 13267 | /// FCRxFF30_1E7C |
| 13268 | typedef union { |
| 13269 | struct { ///< |
| 13270 | UINT32 Reserved_3_0:4 ; ///< |
| 13271 | UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///< |
| 13272 | UINT32 Reserved_7_5:3 ; ///< |
| 13273 | UINT32 CrtcDispclkGDcpGateDisable:1 ; ///< |
| 13274 | UINT32 Reserved_11_9:3 ; ///< |
| 13275 | UINT32 CrtcDispclkGSclGateDisable:1 ; ///< |
| 13276 | UINT32 Reserved_31_13:19; ///< |
| 13277 | } Field; ///< |
| 13278 | UINT32 Value; ///< |
| 13279 | } FCRxFF30_1E7C_STRUCT; |
| 13280 | |
| 13281 | // **** FCRxFE00_600E Register Definition **** |
| 13282 | // Address |
| 13283 | #define FCRxFE00_600E_ADDRESS 0xfe00600e |
| 13284 | |
| 13285 | // Field Data |
| 13286 | #define FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET 0 |
| 13287 | #define FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH 6 |
| 13288 | #define FCRxFE00_600E_WrCkDid_OFFSET 10 |
| 13289 | #define FCRxFE00_600E_WrCkDid_WIDTH 5 |
| 13290 | |
| 13291 | /// FCRxFE00_600E |
| 13292 | typedef union { |
| 13293 | struct { |
| 13294 | UINT32 MainPllOpFreqIdStartup:6 ; ///< |
| 13295 | UINT32 Reserved:5 ; ///< |
| 13296 | UINT32 WrCkDid:5 ; ///< |
| 13297 | } Field; |
| 13298 | UINT32 Value; |
| 13299 | } FCRxFE00_600E_STRUCT; |
| 13300 | |
| 13301 | // **** SMUx0B_x8498 Register Definition **** |
| 13302 | // Address |
| 13303 | #define SMUx0B_x8498_ADDRESS 0x8498 |
| 13304 | |
| 13305 | // Field Data |
| 13306 | #define SMUx0B_x8498_ConditionalBF_1_0_OFFSET 0 |
| 13307 | #define SMUx0B_x8498_ConditionalBF_1_0_WIDTH 2 |
| 13308 | #define SMUx0B_x8498_ConditionalBF_1_0_MASK 0x3 |
| 13309 | #define SMUx0B_x8498_ConditionalBF_3_2_OFFSET 2 |
| 13310 | #define SMUx0B_x8498_ConditionalBF_3_2_WIDTH 2 |
| 13311 | #define SMUx0B_x8498_ConditionalBF_3_2_MASK 0xc |
| 13312 | #define SMUx0B_x8498_Reserved_7_4_OFFSET 4 |
| 13313 | #define SMUx0B_x8498_Reserved_7_4_WIDTH 4 |
| 13314 | #define SMUx0B_x8498_Reserved_7_4_MASK 0xf0 |
| 13315 | #define SMUx0B_x8498_ConditionalBF_9_8_OFFSET 8 |
| 13316 | #define SMUx0B_x8498_ConditionalBF_9_8_WIDTH 2 |
| 13317 | #define SMUx0B_x8498_ConditionalBF_9_8_MASK 0x300 |
| 13318 | #define SMUx0B_x8498_ConditionalBF_11_10_OFFSET 10 |
| 13319 | #define SMUx0B_x8498_ConditionalBF_11_10_WIDTH 2 |
| 13320 | #define SMUx0B_x8498_ConditionalBF_11_10_MASK 0xc00 |
| 13321 | #define SMUx0B_x8498_Reserved_15_12_OFFSET 12 |
| 13322 | #define SMUx0B_x8498_Reserved_15_12_WIDTH 4 |
| 13323 | #define SMUx0B_x8498_Reserved_15_12_MASK 0xf000 |
| 13324 | #define SMUx0B_x8498_BaseVid_5_OFFSET 16 |
| 13325 | #define SMUx0B_x8498_BaseVid_5_WIDTH 2 |
| 13326 | #define SMUx0B_x8498_BaseVid_5_MASK 0x30000 |
| 13327 | #define SMUx0B_x8498_TolExcdVid_5_OFFSET 18 |
| 13328 | #define SMUx0B_x8498_TolExcdVid_5_WIDTH 2 |
| 13329 | #define SMUx0B_x8498_TolExcdVid_5_MASK 0xc0000 |
| 13330 | #define SMUx0B_x8498_Reserved_23_20_OFFSET 20 |
| 13331 | #define SMUx0B_x8498_Reserved_23_20_WIDTH 4 |
| 13332 | #define SMUx0B_x8498_Reserved_23_20_MASK 0xf00000 |
| 13333 | #define SMUx0B_x8498_BaseVid_4_OFFSET 24 |
| 13334 | #define SMUx0B_x8498_BaseVid_4_WIDTH 2 |
| 13335 | #define SMUx0B_x8498_BaseVid_4_MASK 0x3000000 |
| 13336 | #define SMUx0B_x8498_TolExcdVid_4_OFFSET 26 |
| 13337 | #define SMUx0B_x8498_TolExcdVid_4_WIDTH 2 |
| 13338 | #define SMUx0B_x8498_TolExcdVid_4_MASK 0xc000000 |
| 13339 | #define SMUx0B_x8498_Reserved_31_28_OFFSET 28 |
| 13340 | #define SMUx0B_x8498_Reserved_31_28_WIDTH 4 |
| 13341 | #define SMUx0B_x8498_Reserved_31_28_MASK 0xf0000000 |
| 13342 | |
| 13343 | /// SMUx0B_x8498 |
| 13344 | typedef union { |
| 13345 | struct { ///< |
| 13346 | UINT32 ConditionalBF_1_0:2 ; ///< |
| 13347 | UINT32 ConditionalBF_3_2:2 ; ///< |
| 13348 | UINT32 Reserved_7_4:4 ; ///< |
| 13349 | UINT32 ConditionalBF_9_8:2 ; ///< |
| 13350 | UINT32 ConditionalBF_11_10:2 ; ///< |
| 13351 | UINT32 Reserved_15_12:4 ; ///< |
| 13352 | UINT32 BaseVid_5:2 ; ///< |
| 13353 | UINT32 TolExcdVid_5:2 ; ///< |
| 13354 | UINT32 Reserved_23_20:4 ; ///< |
| 13355 | UINT32 BaseVid_4:2 ; ///< |
| 13356 | UINT32 TolExcdVid_4:2 ; ///< |
| 13357 | UINT32 Reserved_31_28:4 ; ///< |
| 13358 | } Field; ///< |
| 13359 | UINT32 Value; ///< |
| 13360 | } SMUx0B_x8498_STRUCT; |
| 13361 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13362 | |
| 13363 | // **** SMUx0B_x85B0 Register Definition **** |
| 13364 | // Address |
| 13365 | #define SMUx0B_x85B0_ADDRESS 0x85B0 |
| 13366 | |
| 13367 | |
| 13368 | // **** SMUx0B_x85D0 Register Definition **** |
| 13369 | // Address |
| 13370 | #define SMUx0B_x85D0_ADDRESS 0x85D0 |
| 13371 | |
| 13372 | // **** D0F0x64_x51 Register Definition **** |
| 13373 | // Address |
| 13374 | #define D0F0x64_x51_ADDRESS 0x51 |
| 13375 | |
| 13376 | // Type |
| 13377 | #define D0F0x64_x51_TYPE TYPE_D0F0x64 |
| 13378 | // Field Data |
| 13379 | #define D0F0x64_x51_Reserved_2_0_OFFSET 0 |
| 13380 | #define D0F0x64_x51_Reserved_2_0_WIDTH 3 |
| 13381 | #define D0F0x64_x51_Reserved_2_0_MASK 0x7 |
| 13382 | #define D0F0x64_x51_P2pDis_OFFSET 3 |
| 13383 | #define D0F0x64_x51_P2pDis_WIDTH 1 |
| 13384 | #define D0F0x64_x51_P2pDis_MASK 0x8 |
| 13385 | #define D0F0x64_x51_Reserved_15_4_OFFSET 4 |
| 13386 | #define D0F0x64_x51_Reserved_15_4_WIDTH 12 |
| 13387 | #define D0F0x64_x51_Reserved_15_4_MASK 0xfff0 |
| 13388 | #define D0F0x64_x51_ExtDevPlug_OFFSET 16 |
| 13389 | #define D0F0x64_x51_ExtDevPlug_WIDTH 1 |
| 13390 | #define D0F0x64_x51_ExtDevPlug_MASK 0x10000 |
| 13391 | #define D0F0x64_x51_ExtDevCrsEn_OFFSET 17 |
| 13392 | #define D0F0x64_x51_ExtDevCrsEn_WIDTH 1 |
| 13393 | #define D0F0x64_x51_ExtDevCrsEn_MASK 0x20000 |
| 13394 | #define D0F0x64_x51_CrsEn_OFFSET 18 |
| 13395 | #define D0F0x64_x51_CrsEn_WIDTH 1 |
| 13396 | #define D0F0x64_x51_CrsEn_MASK 0x40000 |
| 13397 | #define D0F0x64_x51_IntSelMode_OFFSET 19 |
| 13398 | #define D0F0x64_x51_IntSelMode_WIDTH 1 |
| 13399 | #define D0F0x64_x51_IntSelMode_MASK 0x80000 |
| 13400 | #define D0F0x64_x51_SetPowEn_OFFSET 20 |
| 13401 | #define D0F0x64_x51_SetPowEn_WIDTH 1 |
| 13402 | #define D0F0x64_x51_SetPowEn_MASK 0x100000 |
| 13403 | #define D0F0x64_x51_Reserved_31_21_OFFSET 21 |
| 13404 | #define D0F0x64_x51_Reserved_31_21_WIDTH 11 |
| 13405 | #define D0F0x64_x51_Reserved_31_21_MASK 0xffe00000 |
| 13406 | |
| 13407 | /// D0F0x64_x51 |
| 13408 | typedef union { |
| 13409 | struct { ///< |
| 13410 | UINT32 Reserved_2_0:3 ; ///< |
| 13411 | UINT32 P2pDis:1 ; ///< |
| 13412 | UINT32 Reserved_15_4:12; ///< |
| 13413 | UINT32 ExtDevPlug:1 ; ///< |
| 13414 | UINT32 ExtDevCrsEn:1 ; ///< |
| 13415 | UINT32 CrsEn:1 ; ///< |
| 13416 | UINT32 IntSelMode:1 ; ///< |
| 13417 | UINT32 SetPowEn:1 ; ///< |
| 13418 | UINT32 Reserved_31_21:11; ///< |
| 13419 | } Field; ///< |
| 13420 | UINT32 Value; ///< |
| 13421 | } D0F0x64_x51_STRUCT; |
| 13422 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13423 | // **** D0F0xE4_PHY_6440 Register Definition **** |
| 13424 | // Address |
| 13425 | #define D0F0xE4_PHY_6440_ADDRESS 0x6440 |
| 13426 | |
| 13427 | // Type |
| 13428 | #define D0F0xE4_PHY_6440_TYPE TYPE_D0F0xE4 |
| 13429 | // Field Data |
| 13430 | #define D0F0xE4_PHY_6440_RxInCalForce_OFFSET 7 |
| 13431 | #define D0F0xE4_PHY_6440_RxInCalForce_WIDTH 1 |
| 13432 | #define D0F0xE4_PHY_6440_RxInCalForce_MASK 0x80 |
| 13433 | |
| 13434 | // **** D0F0xE4_PHY_6480 Register Definition **** |
| 13435 | // Address |
| 13436 | #define D0F0xE4_PHY_6480_ADDRESS 0x6480 |
| 13437 | |
| 13438 | // Type |
| 13439 | #define D0F0xE4_PHY_6480_TYPE TYPE_D0F0xE4 |
| 13440 | // Field Data |
| 13441 | #define D0F0xE4_PHY_6480_RxInCalForce_OFFSET 7 |
| 13442 | #define D0F0xE4_PHY_6480_RxInCalForce_WIDTH 1 |
| 13443 | #define D0F0xE4_PHY_6480_RxInCalForce_MASK 0x80 |
| 13444 | |
| 13445 | // **** D0F0xE4_PHY_6500 Register Definition **** |
| 13446 | // Address |
| 13447 | #define D0F0xE4_PHY_6500_ADDRESS 0x6500 |
| 13448 | |
| 13449 | // Type |
| 13450 | #define D0F0xE4_PHY_6500_TYPE TYPE_D0F0xE4 |
| 13451 | // Field Data |
| 13452 | #define D0F0xE4_PHY_6500_RxInCalForce_OFFSET 7 |
| 13453 | #define D0F0xE4_PHY_6500_RxInCalForce_WIDTH 1 |
| 13454 | #define D0F0xE4_PHY_6500_RxInCalForce_MASK 0x80 |
| 13455 | |
| 13456 | // **** D0F0xE4_PHY_6600 Register Definition **** |
| 13457 | // Address |
| 13458 | #define D0F0xE4_PHY_6600_ADDRESS 0x6600 |
| 13459 | |
| 13460 | // Type |
| 13461 | #define D0F0xE4_PHY_6600_TYPE TYPE_D0F0xE4 |
| 13462 | // Field Data |
| 13463 | #define D0F0xE4_PHY_6600_RxInCalForce_OFFSET 7 |
| 13464 | #define D0F0xE4_PHY_6600_RxInCalForce_WIDTH 1 |
| 13465 | #define D0F0xE4_PHY_6600_RxInCalForce_MASK 0x80 |
| 13466 | |
| 13467 | |
| 13468 | // **** D0F0xE4_PHY_6840 Register Definition **** |
| 13469 | // Address |
| 13470 | #define D0F0xE4_PHY_6840_ADDRESS 0x6840 |
| 13471 | |
| 13472 | // Type |
| 13473 | #define D0F0xE4_PHY_6840_TYPE TYPE_D0F0xE4 |
| 13474 | // Field Data |
| 13475 | #define D0F0xE4_PHY_6840_RxInCalForce_OFFSET 7 |
| 13476 | #define D0F0xE4_PHY_6840_RxInCalForce_WIDTH 1 |
| 13477 | #define D0F0xE4_PHY_6840_RxInCalForce_MASK 0x80 |
| 13478 | |
| 13479 | |
| 13480 | // **** D0F0xE4_PHY_6880 Register Definition **** |
| 13481 | // Address |
| 13482 | #define D0F0xE4_PHY_6880_ADDRESS 0x6880 |
| 13483 | |
| 13484 | // Type |
| 13485 | #define D0F0xE4_PHY_6880_TYPE TYPE_D0F0xE4 |
| 13486 | // Field Data |
| 13487 | #define D0F0xE4_PHY_6880_RxInCalForce_OFFSET 7 |
| 13488 | #define D0F0xE4_PHY_6880_RxInCalForce_WIDTH 1 |
| 13489 | #define D0F0xE4_PHY_6880_RxInCalForce_MASK 0x80 |
| 13490 | |
| 13491 | // **** D0F0xE4_PHY_6900 Register Definition **** |
| 13492 | // Address |
| 13493 | #define D0F0xE4_PHY_6900_ADDRESS 0x6900 |
| 13494 | |
| 13495 | // Type |
| 13496 | #define D0F0xE4_PHY_6900_TYPE TYPE_D0F0xE4 |
| 13497 | // Field Data |
| 13498 | #define D0F0xE4_PHY_6900_RxInCalForce_OFFSET 7 |
| 13499 | #define D0F0xE4_PHY_6900_RxInCalForce_WIDTH 1 |
| 13500 | #define D0F0xE4_PHY_6900_RxInCalForce_MASK 0x80 |
| 13501 | |
| 13502 | // **** D0F0xE4_PHY_6A00 Register Definition **** |
| 13503 | // Address |
| 13504 | #define D0F0xE4_PHY_6A00_ADDRESS 0x6a00 |
| 13505 | |
| 13506 | // Type |
| 13507 | #define D0F0xE4_PHY_6A00_TYPE TYPE_D0F0xE4 |
| 13508 | // Field Data |
| 13509 | #define D0F0xE4_PHY_6A00_RxInCalForce_OFFSET 7 |
| 13510 | #define D0F0xE4_PHY_6A00_RxInCalForce_WIDTH 1 |
| 13511 | #define D0F0xE4_PHY_6A00_RxInCalForce_MASK 0x80 |
| 13512 | |
| 13513 | // **** D0F0x64_x20 Register Definition **** |
| 13514 | // Address |
| 13515 | #define D0F0x64_x20_ADDRESS 0x20 |
| 13516 | |
| 13517 | // Type |
| 13518 | #define D0F0x64_x20_TYPE TYPE_D0F0x64 |
| 13519 | // Field Data |
| 13520 | #define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1 |
| 13521 | #define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1 |
| 13522 | #define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2 |
| 13523 | |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13524 | // **** SMUx33 Register Definition **** |
| 13525 | // Address |
| 13526 | #define SMUx33_ADDRESS 0x33 |
| 13527 | |
| 13528 | // Type |
| 13529 | #define SMUx33_TYPE TYPE_SMU |
| 13530 | // Field Data |
| 13531 | #define SMUx33_LclkActMonPrd_OFFSET 0 |
| 13532 | #define SMUx33_LclkActMonPrd_WIDTH 16 |
| 13533 | #define SMUx33_LclkActMonPrd_MASK 0xffff |
| 13534 | #define SMUx33_LclkActMonUnt_OFFSET 16 |
| 13535 | #define SMUx33_LclkActMonUnt_WIDTH 4 |
| 13536 | #define SMUx33_LclkActMonUnt_MASK 0xf0000 |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13537 | #define SMUx33_TrendMode_OFFSET 20 |
| 13538 | #define SMUx33_TrendMode_WIDTH 1 |
| 13539 | #define SMUx33_TrendMode_MASK 0x100000 |
| 13540 | #define SMUx33_ForceTrend_OFFSET 21 |
| 13541 | #define SMUx33_ForceTrend_WIDTH 1 |
| 13542 | #define SMUx33_ForceTrend_MASK 0x200000 |
| 13543 | #define SMUx33_ActMonRst_OFFSET 22 |
| 13544 | #define SMUx33_ActMonRst_WIDTH 1 |
| 13545 | #define SMUx33_ActMonRst_MASK 0x400000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13546 | #define SMUx33_BusyCntSel_OFFSET 23 |
| 13547 | #define SMUx33_BusyCntSel_WIDTH 2 |
| 13548 | #define SMUx33_BusyCntSel_MASK 0x1800000 |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13549 | #define SMUx33_AccessCntl_OFFSET 25 |
| 13550 | #define SMUx33_AccessCntl_WIDTH 1 |
| 13551 | #define SMUx33_AccessCntl_MASK 0x2000000 |
| 13552 | #define SMUx33_Reserved_31_26_OFFSET 26 |
| 13553 | #define SMUx33_Reserved_31_26_WIDTH 6 |
| 13554 | #define SMUx33_Reserved_31_26_MASK 0xfc000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13555 | |
| 13556 | /// SMUx33 |
| 13557 | typedef union { |
| 13558 | struct { ///< |
| 13559 | UINT32 LclkActMonPrd:16; ///< |
| 13560 | UINT32 LclkActMonUnt:4 ; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13561 | UINT32 TrendMode:1 ; ///< |
| 13562 | UINT32 ForceTrend:1 ; ///< |
| 13563 | UINT32 ActMonRst:1 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13564 | UINT32 BusyCntSel:2 ; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13565 | UINT32 AccessCntl:1 ; ///< |
| 13566 | UINT32 Reserved_31_26:6 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13567 | } Field; ///< |
| 13568 | UINT32 Value; ///< |
| 13569 | } SMUx33_STRUCT; |
| 13570 | |
| 13571 | // **** SMUx0B_x8434 Register Definition **** |
| 13572 | // Address |
| 13573 | #define SMUx0B_x8434_ADDRESS 0x8434 |
| 13574 | |
| 13575 | // Type |
| 13576 | #define SMUx0B_x8434_TYPE TYPE_SMUx0B |
| 13577 | // Field Data |
| 13578 | #define SMUx0B_x8434_LclkDpmEn_OFFSET 0 |
| 13579 | #define SMUx0B_x8434_LclkDpmEn_WIDTH 1 |
| 13580 | #define SMUx0B_x8434_LclkDpmEn_MASK 0x1 |
| 13581 | #define SMUx0B_x8434_LclkDpmType_OFFSET 1 |
| 13582 | #define SMUx0B_x8434_LclkDpmType_WIDTH 1 |
| 13583 | #define SMUx0B_x8434_LclkDpmType_MASK 0x2 |
| 13584 | #define SMUx0B_x8434_Reserved_3_2_OFFSET 2 |
| 13585 | #define SMUx0B_x8434_Reserved_3_2_WIDTH 2 |
| 13586 | #define SMUx0B_x8434_Reserved_3_2_MASK 0xc |
| 13587 | #define SMUx0B_x8434_LclkTimerPrescalar_OFFSET 4 |
| 13588 | #define SMUx0B_x8434_LclkTimerPrescalar_WIDTH 4 |
| 13589 | #define SMUx0B_x8434_LclkTimerPrescalar_MASK 0xf0 |
| 13590 | #define SMUx0B_x8434_Reserved_15_8_OFFSET 8 |
| 13591 | #define SMUx0B_x8434_Reserved_15_8_WIDTH 8 |
| 13592 | #define SMUx0B_x8434_Reserved_15_8_MASK 0xff00 |
| 13593 | #define SMUx0B_x8434_LclkTimerPeriod_OFFSET 16 |
| 13594 | #define SMUx0B_x8434_LclkTimerPeriod_WIDTH 16 |
| 13595 | #define SMUx0B_x8434_LclkTimerPeriod_MASK 0xffff0000 |
| 13596 | |
| 13597 | /// SMUx0B_x8434 |
| 13598 | typedef union { |
| 13599 | struct { ///< |
| 13600 | UINT32 LclkDpmEn:1 ; ///< |
| 13601 | UINT32 LclkDpmType:1 ; ///< |
| 13602 | UINT32 Reserved_3_2:2 ; ///< |
| 13603 | UINT32 LclkTimerPrescalar:4 ; ///< |
| 13604 | UINT32 Reserved_15_8:8 ; ///< |
| 13605 | UINT32 LclkTimerPeriod:16; ///< |
| 13606 | } Field; ///< |
| 13607 | UINT32 Value; ///< |
| 13608 | } SMUx0B_x8434_STRUCT; |
| 13609 | |
| 13610 | // **** FCRxFF30_01E4 Register Definition **** |
| 13611 | // Address |
| 13612 | #define FCRxFF30_01E4_ADDRESS 0xff3001e4 |
| 13613 | |
| 13614 | // Type |
| 13615 | #define FCRxFF30_01E4_TYPE TYPE_FCR |
| 13616 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13617 | #define FCRxFF30_01E4_Fraction_OFFSET 0 |
| 13618 | #define FCRxFF30_01E4_Fraction_WIDTH 8 |
| 13619 | #define FCRxFF30_01E4_Fraction_MASK 0xff |
| 13620 | #define FCRxFF30_01E4_Hysteresis_OFFSET 8 |
| 13621 | #define FCRxFF30_01E4_Hysteresis_WIDTH 12 |
| 13622 | #define FCRxFF30_01E4_Hysteresis_MASK 0xfff00 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13623 | #define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20 |
| 13624 | #define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1 |
| 13625 | #define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000 |
| 13626 | #define FCRxFF30_01E4_Reserved_31_21_OFFSET 21 |
| 13627 | #define FCRxFF30_01E4_Reserved_31_21_WIDTH 11 |
| 13628 | #define FCRxFF30_01E4_Reserved_31_21_MASK 0xffe00000 |
| 13629 | |
| 13630 | /// FCRxFF30_01E4 |
| 13631 | typedef union { |
| 13632 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13633 | UINT32 Fraction:8 ; ///< |
| 13634 | UINT32 Hysteresis:12; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13635 | UINT32 VoltageChangeEn:1 ; ///< |
| 13636 | UINT32 Reserved_31_21:11; ///< |
| 13637 | } Field; ///< |
| 13638 | UINT32 Value; ///< |
| 13639 | } FCRxFF30_01E4_STRUCT; |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13640 | // **** SMUx0B_x84AC Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13641 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13642 | #define SMUx0B_x84AC_ADDRESS 0x84ac |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13643 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13644 | // Type |
| 13645 | #define SMUx0B_x84AC_TYPE TYPE_SMUx0B |
| 13646 | // Field Data |
| 13647 | #define SMUx0B_x84AC_FstateCredits_1_OFFSET 0 |
| 13648 | #define SMUx0B_x84AC_FstateCredits_1_WIDTH 16 |
| 13649 | #define SMUx0B_x84AC_FstateCredits_1_MASK 0xffff |
| 13650 | #define SMUx0B_x84AC_FstateCredits_0_OFFSET 16 |
| 13651 | #define SMUx0B_x84AC_FstateCredits_0_WIDTH 16 |
| 13652 | #define SMUx0B_x84AC_FstateCredits_0_MASK 0xffff0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13653 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13654 | /// SMUx0B_x84AC |
| 13655 | typedef union { |
| 13656 | struct { ///< |
| 13657 | UINT32 FstateCredits_1:16; ///< |
| 13658 | UINT32 FstateCredits_0:16; ///< |
| 13659 | } Field; ///< |
| 13660 | UINT32 Value; ///< |
| 13661 | } SMUx0B_x84AC_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13662 | |
| 13663 | // **** SMUx0B_x848C Register Definition **** |
| 13664 | // Address |
| 13665 | #define SMUx0B_x848C_ADDRESS 0x848c |
| 13666 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13667 | // Type |
| 13668 | #define SMUx0B_x848C_TYPE TYPE_SMUx0B |
| 13669 | // Field Data |
| 13670 | #define SMUx0B_x848C_FstateDiv_7_OFFSET 0 |
| 13671 | #define SMUx0B_x848C_FstateDiv_7_WIDTH 7 |
| 13672 | #define SMUx0B_x848C_FstateDiv_7_MASK 0x7f |
| 13673 | #define SMUx0B_x848C_Reserved_7_7_OFFSET 7 |
| 13674 | #define SMUx0B_x848C_Reserved_7_7_WIDTH 1 |
| 13675 | #define SMUx0B_x848C_Reserved_7_7_MASK 0x80 |
| 13676 | #define SMUx0B_x848C_FstateDiv_6_OFFSET 8 |
| 13677 | #define SMUx0B_x848C_FstateDiv_6_WIDTH 7 |
| 13678 | #define SMUx0B_x848C_FstateDiv_6_MASK 0x7f00 |
| 13679 | #define SMUx0B_x848C_Reserved_15_15_OFFSET 15 |
| 13680 | #define SMUx0B_x848C_Reserved_15_15_WIDTH 1 |
| 13681 | #define SMUx0B_x848C_Reserved_15_15_MASK 0x8000 |
| 13682 | #define SMUx0B_x848C_FstateDiv_5_OFFSET 16 |
| 13683 | #define SMUx0B_x848C_FstateDiv_5_WIDTH 7 |
| 13684 | #define SMUx0B_x848C_FstateDiv_5_MASK 0x7f0000 |
| 13685 | #define SMUx0B_x848C_Reserved_23_23_OFFSET 23 |
| 13686 | #define SMUx0B_x848C_Reserved_23_23_WIDTH 1 |
| 13687 | #define SMUx0B_x848C_Reserved_23_23_MASK 0x800000 |
| 13688 | #define SMUx0B_x848C_FstateDiv_4_OFFSET 24 |
| 13689 | #define SMUx0B_x848C_FstateDiv_4_WIDTH 7 |
| 13690 | #define SMUx0B_x848C_FstateDiv_4_MASK 0x7f000000 |
| 13691 | #define SMUx0B_x848C_Reserved_31_31_OFFSET 31 |
| 13692 | #define SMUx0B_x848C_Reserved_31_31_WIDTH 1 |
| 13693 | #define SMUx0B_x848C_Reserved_31_31_MASK 0x80000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13694 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13695 | /// SMUx0B_x848C |
| 13696 | typedef union { |
| 13697 | struct { ///< |
| 13698 | UINT32 FstateDiv_7:7 ; ///< |
| 13699 | UINT32 Reserved_7_7:1 ; ///< |
| 13700 | UINT32 FstateDiv_6:7 ; ///< |
| 13701 | UINT32 Reserved_15_15:1 ; ///< |
| 13702 | UINT32 FstateDiv_5:7 ; ///< |
| 13703 | UINT32 Reserved_23_23:1 ; ///< |
| 13704 | UINT32 FstateDiv_4:7 ; ///< |
| 13705 | UINT32 Reserved_31_31:1 ; ///< |
| 13706 | } Field; ///< |
| 13707 | UINT32 Value; ///< |
| 13708 | } SMUx0B_x848C_STRUCT; |
| 13709 | |
| 13710 | // **** SMUx0B_x8470 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13711 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13712 | #define SMUx0B_x8470_ADDRESS 0x8470 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13713 | |
| 13714 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13715 | #define SMUx0B_x8470_TYPE TYPE_SMUx0B |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13716 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13717 | #define SMUx0B_x8470_Raising_OFFSET 0 |
| 13718 | #define SMUx0B_x8470_Raising_WIDTH 16 |
| 13719 | #define SMUx0B_x8470_Raising_MASK 0xffff |
| 13720 | #define SMUx0B_x8470_Lowering_OFFSET 16 |
| 13721 | #define SMUx0B_x8470_Lowering_WIDTH 16 |
| 13722 | #define SMUx0B_x8470_Lowering_MASK 0xffff0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13723 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13724 | /// SMUx0B_x8470 |
| 13725 | typedef union { |
| 13726 | struct { ///< |
| 13727 | UINT32 Raising:16; ///< |
| 13728 | UINT32 Lowering:16; ///< |
| 13729 | } Field; ///< |
| 13730 | UINT32 Value; ///< |
| 13731 | } SMUx0B_x8470_STRUCT; |
| 13732 | |
| 13733 | // **** SMUx0B_x8440 Register Definition **** |
| 13734 | // Address |
| 13735 | #define SMUx0B_x8440_ADDRESS 0x8440 |
| 13736 | |
| 13737 | // Type |
| 13738 | #define SMUx0B_x8440_TYPE TYPE_SMUx0B |
| 13739 | // Field Data |
| 13740 | #define SMUx0B_x8440_FstatePeriod_5_OFFSET 0 |
| 13741 | #define SMUx0B_x8440_FstatePeriod_5_WIDTH 16 |
| 13742 | #define SMUx0B_x8440_FstatePeriod_5_MASK 0xffff |
| 13743 | #define SMUx0B_x8440_FstatePeriod_4_OFFSET 16 |
| 13744 | #define SMUx0B_x8440_FstatePeriod_4_WIDTH 16 |
| 13745 | #define SMUx0B_x8440_FstatePeriod_4_MASK 0xffff0000 |
| 13746 | |
| 13747 | /// SMUx0B_x8440 |
| 13748 | typedef union { |
| 13749 | struct { ///< |
| 13750 | UINT32 FstatePeriod_5:16; ///< |
| 13751 | UINT32 FstatePeriod_4:16; ///< |
| 13752 | } Field; ///< |
| 13753 | UINT32 Value; ///< |
| 13754 | } SMUx0B_x8440_STRUCT; |
| 13755 | |
| 13756 | |
| 13757 | // **** SMUx51 Register Definition **** |
| 13758 | // Address |
| 13759 | #define SMUx51_ADDRESS 0x51 |
| 13760 | |
| 13761 | // Type |
| 13762 | #define SMUx51_TYPE TYPE_SMU |
| 13763 | // Field Data |
| 13764 | #define SMUx51_DownTrendCoef_OFFSET 0 |
| 13765 | #define SMUx51_DownTrendCoef_WIDTH 10 |
| 13766 | #define SMUx51_DownTrendCoef_MASK 0x3ff |
| 13767 | #define SMUx51_UpTrendCoef_OFFSET 10 |
| 13768 | #define SMUx51_UpTrendCoef_WIDTH 10 |
| 13769 | #define SMUx51_UpTrendCoef_MASK 0xffc00 |
| 13770 | #define SMUx51_Reserved_31_20_OFFSET 20 |
| 13771 | #define SMUx51_Reserved_31_20_WIDTH 12 |
| 13772 | #define SMUx51_Reserved_31_20_MASK 0xfff00000 |
| 13773 | |
| 13774 | /// SMUx51 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13775 | typedef union { |
| 13776 | struct { ///< |
| 13777 | UINT32 DownTrendCoef:10; ///< |
| 13778 | UINT32 UpTrendCoef:10; ///< |
| 13779 | UINT32 Reserved_31_20:12; ///< |
| 13780 | } Field; ///< |
| 13781 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13782 | } SMUx51_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13783 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13784 | // **** FCRxFE00_70A2 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13785 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13786 | #define FCRxFE00_70A2_ADDRESS 0xfe0070a2 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13787 | |
| 13788 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13789 | #define FCRxFE00_70A2_TYPE TYPE_FCR |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13790 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13791 | #define FCRxFE00_70A2_Reserved_6_0_OFFSET 0 |
| 13792 | #define FCRxFE00_70A2_Reserved_6_0_WIDTH 7 |
| 13793 | #define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f |
| 13794 | #define FCRxFE00_70A2_PPlayTableRev_OFFSET 7 |
| 13795 | #define FCRxFE00_70A2_PPlayTableRev_WIDTH 4 |
| 13796 | #define FCRxFE00_70A2_PPlayTableRev_MASK 0x780 |
| 13797 | #define FCRxFE00_70A2_SclkThermDid_OFFSET 11 |
| 13798 | #define FCRxFE00_70A2_SclkThermDid_WIDTH 7 |
| 13799 | #define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800 |
| 13800 | #define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18 |
| 13801 | #define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2 |
| 13802 | #define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000 |
| 13803 | #define FCRxFE00_70A2_Reserved_31_20_OFFSET 20 |
| 13804 | #define FCRxFE00_70A2_Reserved_31_20_WIDTH 12 |
| 13805 | #define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13806 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13807 | /// FCRxFE00_70A2 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13808 | typedef union { |
| 13809 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13810 | UINT32 Reserved_6_0:7 ; ///< |
| 13811 | UINT32 PPlayTableRev:4 ; ///< |
| 13812 | UINT32 SclkThermDid:7 ; ///< |
| 13813 | UINT32 PcieGen2Vid:2 ; ///< |
| 13814 | UINT32 Reserved_31_20:12; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13815 | } Field; ///< |
| 13816 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13817 | } FCRxFE00_70A2_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13818 | |
| 13819 | // **** FCRxFE00_70A4 Register Definition **** |
| 13820 | // Address |
| 13821 | #define FCRxFE00_70A4_ADDRESS 0xfe0070a4 |
| 13822 | |
| 13823 | // Type |
| 13824 | #define FCRxFE00_70A4_TYPE TYPE_FCR |
| 13825 | // Field Data |
| 13826 | #define FCRxFE00_70A4_Reserved_3_0_OFFSET 0 |
| 13827 | #define FCRxFE00_70A4_Reserved_3_0_WIDTH 4 |
| 13828 | #define FCRxFE00_70A4_Reserved_3_0_MASK 0xf |
| 13829 | #define FCRxFE00_70A4_SclkDpmVid0_OFFSET 4 |
| 13830 | #define FCRxFE00_70A4_SclkDpmVid0_WIDTH 2 |
| 13831 | #define FCRxFE00_70A4_SclkDpmVid0_MASK 0x30 |
| 13832 | #define FCRxFE00_70A4_SclkDpmVid1_OFFSET 6 |
| 13833 | #define FCRxFE00_70A4_SclkDpmVid1_WIDTH 2 |
| 13834 | #define FCRxFE00_70A4_SclkDpmVid1_MASK 0xc0 |
| 13835 | #define FCRxFE00_70A4_SclkDpmVid2_OFFSET 8 |
| 13836 | #define FCRxFE00_70A4_SclkDpmVid2_WIDTH 2 |
| 13837 | #define FCRxFE00_70A4_SclkDpmVid2_MASK 0x300 |
| 13838 | #define FCRxFE00_70A4_SclkDpmVid3_OFFSET 10 |
| 13839 | #define FCRxFE00_70A4_SclkDpmVid3_WIDTH 2 |
| 13840 | #define FCRxFE00_70A4_SclkDpmVid3_MASK 0xc00 |
| 13841 | #define FCRxFE00_70A4_SclkDpmVid4_OFFSET 12 |
| 13842 | #define FCRxFE00_70A4_SclkDpmVid4_WIDTH 2 |
| 13843 | #define FCRxFE00_70A4_SclkDpmVid4_MASK 0x3000 |
| 13844 | #define FCRxFE00_70A4_Reserved_31_14_OFFSET 14 |
| 13845 | #define FCRxFE00_70A4_Reserved_31_14_WIDTH 18 |
| 13846 | #define FCRxFE00_70A4_Reserved_31_14_MASK 0xffffc000 |
| 13847 | |
| 13848 | /// FCRxFE00_70A4 |
| 13849 | typedef union { |
| 13850 | struct { ///< |
| 13851 | UINT32 Reserved_3_0:4 ; ///< |
| 13852 | UINT32 SclkDpmVid0:2 ; ///< |
| 13853 | UINT32 SclkDpmVid1:2 ; ///< |
| 13854 | UINT32 SclkDpmVid2:2 ; ///< |
| 13855 | UINT32 SclkDpmVid3:2 ; ///< |
| 13856 | UINT32 SclkDpmVid4:2 ; ///< |
| 13857 | UINT32 Reserved_31_14:18; ///< |
| 13858 | } Field; ///< |
| 13859 | UINT32 Value; ///< |
| 13860 | } FCRxFE00_70A4_STRUCT; |
| 13861 | |
| 13862 | // **** FCRxFE00_70A5 Register Definition **** |
| 13863 | // Address |
| 13864 | #define FCRxFE00_70A5_ADDRESS 0xfe0070a5 |
| 13865 | |
| 13866 | // Type |
| 13867 | #define FCRxFE00_70A5_TYPE TYPE_FCR |
| 13868 | // Field Data |
| 13869 | #define FCRxFE00_70A5_Reserved_5_0_OFFSET 0 |
| 13870 | #define FCRxFE00_70A5_Reserved_5_0_WIDTH 6 |
| 13871 | #define FCRxFE00_70A5_Reserved_5_0_MASK 0x3f |
| 13872 | #define FCRxFE00_70A5_SclkDpmDid0_OFFSET 6 |
| 13873 | #define FCRxFE00_70A5_SclkDpmDid0_WIDTH 7 |
| 13874 | #define FCRxFE00_70A5_SclkDpmDid0_MASK 0x1fc0 |
| 13875 | #define FCRxFE00_70A5_SclkDpmDid1_OFFSET 13 |
| 13876 | #define FCRxFE00_70A5_SclkDpmDid1_WIDTH 7 |
| 13877 | #define FCRxFE00_70A5_SclkDpmDid1_MASK 0xfe000 |
| 13878 | #define FCRxFE00_70A5_SclkDpmDid2_OFFSET 20 |
| 13879 | #define FCRxFE00_70A5_SclkDpmDid2_WIDTH 7 |
| 13880 | #define FCRxFE00_70A5_SclkDpmDid2_MASK 0x7f00000 |
| 13881 | #define FCRxFE00_70A5_Reserved_31_27_OFFSET 27 |
| 13882 | #define FCRxFE00_70A5_Reserved_31_27_WIDTH 5 |
| 13883 | #define FCRxFE00_70A5_Reserved_31_27_MASK 0xf8000000 |
| 13884 | |
| 13885 | /// FCRxFE00_70A5 |
| 13886 | typedef union { |
| 13887 | struct { ///< |
| 13888 | UINT32 Reserved_5_0:6 ; ///< |
| 13889 | UINT32 SclkDpmDid0:7 ; ///< |
| 13890 | UINT32 SclkDpmDid1:7 ; ///< |
| 13891 | UINT32 SclkDpmDid2:7 ; ///< |
| 13892 | UINT32 Reserved_31_27:5 ; ///< |
| 13893 | } Field; ///< |
| 13894 | UINT32 Value; ///< |
| 13895 | } FCRxFE00_70A5_STRUCT; |
| 13896 | |
| 13897 | // **** FCRxFE00_70A8 Register Definition **** |
| 13898 | // Address |
| 13899 | #define FCRxFE00_70A8_ADDRESS 0xfe0070a8 |
| 13900 | |
| 13901 | // Type |
| 13902 | #define FCRxFE00_70A8_TYPE TYPE_FCR |
| 13903 | // Field Data |
| 13904 | #define FCRxFE00_70A8_Reserved_2_0_OFFSET 0 |
| 13905 | #define FCRxFE00_70A8_Reserved_2_0_WIDTH 3 |
| 13906 | #define FCRxFE00_70A8_Reserved_2_0_MASK 0x7 |
| 13907 | #define FCRxFE00_70A8_SclkDpmDid3_OFFSET 3 |
| 13908 | #define FCRxFE00_70A8_SclkDpmDid3_WIDTH 7 |
| 13909 | #define FCRxFE00_70A8_SclkDpmDid3_MASK 0x3f8 |
| 13910 | #define FCRxFE00_70A8_SclkDpmDid4_OFFSET 10 |
| 13911 | #define FCRxFE00_70A8_SclkDpmDid4_WIDTH 7 |
| 13912 | #define FCRxFE00_70A8_SclkDpmDid4_MASK 0x1fc00 |
| 13913 | #define FCRxFE00_70A8_Reserved_31_17_OFFSET 17 |
| 13914 | #define FCRxFE00_70A8_Reserved_31_17_WIDTH 15 |
| 13915 | #define FCRxFE00_70A8_Reserved_31_17_MASK 0xfffe0000 |
| 13916 | |
| 13917 | /// FCRxFE00_70A8 |
| 13918 | typedef union { |
| 13919 | struct { ///< |
| 13920 | UINT32 Reserved_2_0:3 ; ///< |
| 13921 | UINT32 SclkDpmDid3:7 ; ///< |
| 13922 | UINT32 SclkDpmDid4:7 ; ///< |
| 13923 | UINT32 Reserved_31_17:15; ///< |
| 13924 | } Field; ///< |
| 13925 | UINT32 Value; ///< |
| 13926 | } FCRxFE00_70A8_STRUCT; |
| 13927 | |
| 13928 | // **** FCRxFE00_70AE Register Definition **** |
| 13929 | // Address |
| 13930 | #define FCRxFE00_70AE_ADDRESS 0xfe0070ae |
| 13931 | |
| 13932 | // Type |
| 13933 | #define FCRxFE00_70AE_TYPE TYPE_FCR |
| 13934 | // Field Data |
| 13935 | #define FCRxFE00_70AE_Reserved_0_0_OFFSET 0 |
| 13936 | #define FCRxFE00_70AE_Reserved_0_0_WIDTH 1 |
| 13937 | #define FCRxFE00_70AE_Reserved_0_0_MASK 0x1 |
| 13938 | #define FCRxFE00_70AE_DispClkDid0_OFFSET 1 |
| 13939 | #define FCRxFE00_70AE_DispClkDid0_WIDTH 7 |
| 13940 | #define FCRxFE00_70AE_DispClkDid0_MASK 0xfe |
| 13941 | #define FCRxFE00_70AE_DispClkDid1_OFFSET 8 |
| 13942 | #define FCRxFE00_70AE_DispClkDid1_WIDTH 7 |
| 13943 | #define FCRxFE00_70AE_DispClkDid1_MASK 0x7f00 |
| 13944 | #define FCRxFE00_70AE_DispClkDid2_OFFSET 15 |
| 13945 | #define FCRxFE00_70AE_DispClkDid2_WIDTH 7 |
| 13946 | #define FCRxFE00_70AE_DispClkDid2_MASK 0x3f8000 |
| 13947 | #define FCRxFE00_70AE_DispClkDid3_OFFSET 22 |
| 13948 | #define FCRxFE00_70AE_DispClkDid3_WIDTH 7 |
| 13949 | #define FCRxFE00_70AE_DispClkDid3_MASK 0x1fc00000 |
| 13950 | #define FCRxFE00_70AE_Reserved_31_29_OFFSET 29 |
| 13951 | #define FCRxFE00_70AE_Reserved_31_29_WIDTH 3 |
| 13952 | #define FCRxFE00_70AE_Reserved_31_29_MASK 0xe0000000 |
| 13953 | |
| 13954 | /// FCRxFE00_70AE |
| 13955 | typedef union { |
| 13956 | struct { ///< |
| 13957 | UINT32 Reserved_0_0:1 ; ///< |
| 13958 | UINT32 DispClkDid0:7 ; ///< |
| 13959 | UINT32 DispClkDid1:7 ; ///< |
| 13960 | UINT32 DispClkDid2:7 ; ///< |
| 13961 | UINT32 DispClkDid3:7 ; ///< |
| 13962 | UINT32 Reserved_31_29:3 ; ///< |
| 13963 | } Field; ///< |
| 13964 | UINT32 Value; ///< |
| 13965 | } FCRxFE00_70AE_STRUCT; |
| 13966 | |
| 13967 | // **** FCRxFE00_70B1 Register Definition **** |
| 13968 | // Address |
| 13969 | #define FCRxFE00_70B1_ADDRESS 0xfe0070b1 |
| 13970 | |
| 13971 | // Type |
| 13972 | #define FCRxFE00_70B1_TYPE TYPE_FCR |
| 13973 | // Field Data |
| 13974 | #define FCRxFE00_70B1_Reserved_4_0_OFFSET 0 |
| 13975 | #define FCRxFE00_70B1_Reserved_4_0_WIDTH 5 |
| 13976 | #define FCRxFE00_70B1_Reserved_4_0_MASK 0x1f |
| 13977 | #define FCRxFE00_70B1_LclkDpmDid0_OFFSET 5 |
| 13978 | #define FCRxFE00_70B1_LclkDpmDid0_WIDTH 7 |
| 13979 | #define FCRxFE00_70B1_LclkDpmDid0_MASK 0xfe0 |
| 13980 | #define FCRxFE00_70B1_LclkDpmDid1_OFFSET 12 |
| 13981 | #define FCRxFE00_70B1_LclkDpmDid1_WIDTH 7 |
| 13982 | #define FCRxFE00_70B1_LclkDpmDid1_MASK 0x7f000 |
| 13983 | #define FCRxFE00_70B1_LclkDpmDid2_OFFSET 19 |
| 13984 | #define FCRxFE00_70B1_LclkDpmDid2_WIDTH 7 |
| 13985 | #define FCRxFE00_70B1_LclkDpmDid2_MASK 0x3f80000 |
| 13986 | #define FCRxFE00_70B1_Reserved_31_26_OFFSET 26 |
| 13987 | #define FCRxFE00_70B1_Reserved_31_26_WIDTH 6 |
| 13988 | #define FCRxFE00_70B1_Reserved_31_26_MASK 0xfc000000 |
| 13989 | |
| 13990 | /// FCRxFE00_70B1 |
| 13991 | typedef union { |
| 13992 | struct { ///< |
| 13993 | UINT32 Reserved_4_0:5 ; ///< |
| 13994 | UINT32 LclkDpmDid0:7 ; ///< |
| 13995 | UINT32 LclkDpmDid1:7 ; ///< |
| 13996 | UINT32 LclkDpmDid2:7 ; ///< |
| 13997 | UINT32 Reserved_31_26:6 ; ///< |
| 13998 | } Field; ///< |
| 13999 | UINT32 Value; ///< |
| 14000 | } FCRxFE00_70B1_STRUCT; |
| 14001 | |
| 14002 | // **** FCRxFE00_70B4 Register Definition **** |
| 14003 | // Address |
| 14004 | #define FCRxFE00_70B4_ADDRESS 0xfe0070b4 |
| 14005 | |
| 14006 | // Type |
| 14007 | #define FCRxFE00_70B4_TYPE TYPE_FCR |
| 14008 | // Field Data |
| 14009 | #define FCRxFE00_70B4_Reserved_1_0_OFFSET 0 |
| 14010 | #define FCRxFE00_70B4_Reserved_1_0_WIDTH 2 |
| 14011 | #define FCRxFE00_70B4_Reserved_1_0_MASK 0x3 |
| 14012 | #define FCRxFE00_70B4_LclkDpmDid3_OFFSET 2 |
| 14013 | #define FCRxFE00_70B4_LclkDpmDid3_WIDTH 7 |
| 14014 | #define FCRxFE00_70B4_LclkDpmDid3_MASK 0x1fc |
| 14015 | #define FCRxFE00_70B4_LclkDpmValid0_OFFSET 9 |
| 14016 | #define FCRxFE00_70B4_LclkDpmValid0_WIDTH 1 |
| 14017 | #define FCRxFE00_70B4_LclkDpmValid0_MASK 0x200 |
| 14018 | #define FCRxFE00_70B4_LclkDpmValid1_OFFSET 10 |
| 14019 | #define FCRxFE00_70B4_LclkDpmValid1_WIDTH 1 |
| 14020 | #define FCRxFE00_70B4_LclkDpmValid1_MASK 0x400 |
| 14021 | #define FCRxFE00_70B4_LclkDpmValid2_OFFSET 11 |
| 14022 | #define FCRxFE00_70B4_LclkDpmValid2_WIDTH 1 |
| 14023 | #define FCRxFE00_70B4_LclkDpmValid2_MASK 0x800 |
| 14024 | #define FCRxFE00_70B4_LclkDpmValid3_OFFSET 12 |
| 14025 | #define FCRxFE00_70B4_LclkDpmValid3_WIDTH 1 |
| 14026 | #define FCRxFE00_70B4_LclkDpmValid3_MASK 0x1000 |
| 14027 | #define FCRxFE00_70B4_Reserved_31_13_OFFSET 13 |
| 14028 | #define FCRxFE00_70B4_Reserved_31_13_WIDTH 19 |
| 14029 | #define FCRxFE00_70B4_Reserved_31_13_MASK 0xffffe000 |
| 14030 | |
| 14031 | /// FCRxFE00_70B4 |
| 14032 | typedef union { |
| 14033 | struct { ///< |
| 14034 | UINT32 Reserved_1_0:2 ; ///< |
| 14035 | UINT32 LclkDpmDid3:7 ; ///< |
| 14036 | UINT32 LclkDpmValid0:1 ; ///< |
| 14037 | UINT32 LclkDpmValid1:1 ; ///< |
| 14038 | UINT32 LclkDpmValid2:1 ; ///< |
| 14039 | UINT32 LclkDpmValid3:1 ; ///< |
| 14040 | UINT32 Reserved_31_13:19; ///< |
| 14041 | } Field; ///< |
| 14042 | UINT32 Value; ///< |
| 14043 | } FCRxFE00_70B4_STRUCT; |
| 14044 | |
| 14045 | // **** FCRxFE00_70B5 Register Definition **** |
| 14046 | // Address |
| 14047 | #define FCRxFE00_70B5_ADDRESS 0xfe0070b5 |
| 14048 | |
| 14049 | // Type |
| 14050 | #define FCRxFE00_70B5_TYPE TYPE_FCR |
| 14051 | // Field Data |
| 14052 | #define FCRxFE00_70B5_Reserved_4_0_OFFSET 0 |
| 14053 | #define FCRxFE00_70B5_Reserved_4_0_WIDTH 5 |
| 14054 | #define FCRxFE00_70B5_Reserved_4_0_MASK 0x1f |
| 14055 | #define FCRxFE00_70B5_DclkDid0_OFFSET 5 |
| 14056 | #define FCRxFE00_70B5_DclkDid0_WIDTH 7 |
| 14057 | #define FCRxFE00_70B5_DclkDid0_MASK 0xfe0 |
| 14058 | #define FCRxFE00_70B5_DclkDid1_OFFSET 12 |
| 14059 | #define FCRxFE00_70B5_DclkDid1_WIDTH 7 |
| 14060 | #define FCRxFE00_70B5_DclkDid1_MASK 0x7f000 |
| 14061 | #define FCRxFE00_70B5_DclkDid2_OFFSET 19 |
| 14062 | #define FCRxFE00_70B5_DclkDid2_WIDTH 7 |
| 14063 | #define FCRxFE00_70B5_DclkDid2_MASK 0x3f80000 |
| 14064 | #define FCRxFE00_70B5_Reserved_31_26_OFFSET 26 |
| 14065 | #define FCRxFE00_70B5_Reserved_31_26_WIDTH 6 |
| 14066 | #define FCRxFE00_70B5_Reserved_31_26_MASK 0xfc000000 |
| 14067 | |
| 14068 | /// FCRxFE00_70B5 |
| 14069 | typedef union { |
| 14070 | struct { ///< |
| 14071 | UINT32 Reserved_4_0:5 ; ///< |
| 14072 | UINT32 DclkDid0:7 ; ///< |
| 14073 | UINT32 DclkDid1:7 ; ///< |
| 14074 | UINT32 DclkDid2:7 ; ///< |
| 14075 | UINT32 Reserved_31_26:6 ; ///< |
| 14076 | } Field; ///< |
| 14077 | UINT32 Value; ///< |
| 14078 | } FCRxFE00_70B5_STRUCT; |
| 14079 | |
| 14080 | // **** FCRxFE00_70B8 Register Definition **** |
| 14081 | // Address |
| 14082 | #define FCRxFE00_70B8_ADDRESS 0xfe0070b8 |
| 14083 | |
| 14084 | // Type |
| 14085 | #define FCRxFE00_70B8_TYPE TYPE_FCR |
| 14086 | // Field Data |
| 14087 | #define FCRxFE00_70B8_Reserved_1_0_OFFSET 0 |
| 14088 | #define FCRxFE00_70B8_Reserved_1_0_WIDTH 2 |
| 14089 | #define FCRxFE00_70B8_Reserved_1_0_MASK 0x3 |
| 14090 | #define FCRxFE00_70B8_DclkDid3_OFFSET 2 |
| 14091 | #define FCRxFE00_70B8_DclkDid3_WIDTH 7 |
| 14092 | #define FCRxFE00_70B8_DclkDid3_MASK 0x1fc |
| 14093 | #define FCRxFE00_70B8_Reserved_31_9_OFFSET 9 |
| 14094 | #define FCRxFE00_70B8_Reserved_31_9_WIDTH 23 |
| 14095 | #define FCRxFE00_70B8_Reserved_31_9_MASK 0xfffffe00 |
| 14096 | |
| 14097 | /// FCRxFE00_70B8 |
| 14098 | typedef union { |
| 14099 | struct { ///< |
| 14100 | UINT32 Reserved_1_0:2 ; ///< |
| 14101 | UINT32 DclkDid3:7 ; ///< |
| 14102 | UINT32 Reserved_31_9:23; ///< |
| 14103 | } Field; ///< |
| 14104 | UINT32 Value; ///< |
| 14105 | } FCRxFE00_70B8_STRUCT; |
| 14106 | |
| 14107 | // **** FCRxFE00_70B9 Register Definition **** |
| 14108 | // Address |
| 14109 | #define FCRxFE00_70B9_ADDRESS 0xfe0070b9 |
| 14110 | |
| 14111 | // Type |
| 14112 | #define FCRxFE00_70B9_TYPE TYPE_FCR |
| 14113 | // Field Data |
| 14114 | #define FCRxFE00_70B9_Reserved_0_0_OFFSET 0 |
| 14115 | #define FCRxFE00_70B9_Reserved_0_0_WIDTH 1 |
| 14116 | #define FCRxFE00_70B9_Reserved_0_0_MASK 0x1 |
| 14117 | #define FCRxFE00_70B9_VclkDid0_OFFSET 1 |
| 14118 | #define FCRxFE00_70B9_VclkDid0_WIDTH 7 |
| 14119 | #define FCRxFE00_70B9_VclkDid0_MASK 0xfe |
| 14120 | #define FCRxFE00_70B9_VclkDid1_OFFSET 8 |
| 14121 | #define FCRxFE00_70B9_VclkDid1_WIDTH 7 |
| 14122 | #define FCRxFE00_70B9_VclkDid1_MASK 0x7f00 |
| 14123 | #define FCRxFE00_70B9_VclkDid2_OFFSET 15 |
| 14124 | #define FCRxFE00_70B9_VclkDid2_WIDTH 7 |
| 14125 | #define FCRxFE00_70B9_VclkDid2_MASK 0x3f8000 |
| 14126 | #define FCRxFE00_70B9_VclkDid3_OFFSET 22 |
| 14127 | #define FCRxFE00_70B9_VclkDid3_WIDTH 7 |
| 14128 | #define FCRxFE00_70B9_VclkDid3_MASK 0x1fc00000 |
| 14129 | #define FCRxFE00_70B9_Reserved_31_29_OFFSET 29 |
| 14130 | #define FCRxFE00_70B9_Reserved_31_29_WIDTH 3 |
| 14131 | #define FCRxFE00_70B9_Reserved_31_29_MASK 0xe0000000 |
| 14132 | |
| 14133 | /// FCRxFE00_70B9 |
| 14134 | typedef union { |
| 14135 | struct { ///< |
| 14136 | UINT32 Reserved_0_0:1 ; ///< |
| 14137 | UINT32 VclkDid0:7 ; ///< |
| 14138 | UINT32 VclkDid1:7 ; ///< |
| 14139 | UINT32 VclkDid2:7 ; ///< |
| 14140 | UINT32 VclkDid3:7 ; ///< |
| 14141 | UINT32 Reserved_31_29:3 ; ///< |
| 14142 | } Field; ///< |
| 14143 | UINT32 Value; ///< |
| 14144 | } FCRxFE00_70B9_STRUCT; |
| 14145 | |
| 14146 | // **** FCRxFE00_70BC Register Definition **** |
| 14147 | // Address |
| 14148 | #define FCRxFE00_70BC_ADDRESS 0xfe0070bc |
| 14149 | |
| 14150 | // Type |
| 14151 | #define FCRxFE00_70BC_TYPE TYPE_FCR |
| 14152 | // Field Data |
| 14153 | #define FCRxFE00_70BC_Reserved_4_0_OFFSET 0 |
| 14154 | #define FCRxFE00_70BC_Reserved_4_0_WIDTH 5 |
| 14155 | #define FCRxFE00_70BC_Reserved_4_0_MASK 0x1f |
| 14156 | #define FCRxFE00_70BC_SclkDpmValid0_OFFSET 5 |
| 14157 | #define FCRxFE00_70BC_SclkDpmValid0_WIDTH 5 |
| 14158 | #define FCRxFE00_70BC_SclkDpmValid0_MASK 0x3e0 |
| 14159 | #define FCRxFE00_70BC_SclkDpmValid1_OFFSET 10 |
| 14160 | #define FCRxFE00_70BC_SclkDpmValid1_WIDTH 5 |
| 14161 | #define FCRxFE00_70BC_SclkDpmValid1_MASK 0x7c00 |
| 14162 | #define FCRxFE00_70BC_SclkDpmValid2_OFFSET 15 |
| 14163 | #define FCRxFE00_70BC_SclkDpmValid2_WIDTH 5 |
| 14164 | #define FCRxFE00_70BC_SclkDpmValid2_MASK 0xf8000 |
| 14165 | #define FCRxFE00_70BC_SclkDpmValid3_OFFSET 20 |
| 14166 | #define FCRxFE00_70BC_SclkDpmValid3_WIDTH 5 |
| 14167 | #define FCRxFE00_70BC_SclkDpmValid3_MASK 0x1f00000 |
| 14168 | #define FCRxFE00_70BC_SclkDpmValid4_OFFSET 25 |
| 14169 | #define FCRxFE00_70BC_SclkDpmValid4_WIDTH 5 |
| 14170 | #define FCRxFE00_70BC_SclkDpmValid4_MASK 0x3e000000 |
| 14171 | #define FCRxFE00_70BC_Reserved_31_30_OFFSET 30 |
| 14172 | #define FCRxFE00_70BC_Reserved_31_30_WIDTH 2 |
| 14173 | #define FCRxFE00_70BC_Reserved_31_30_MASK 0xc0000000 |
| 14174 | |
| 14175 | /// FCRxFE00_70BC |
| 14176 | typedef union { |
| 14177 | struct { ///< |
| 14178 | UINT32 Reserved_4_0:5 ; ///< |
| 14179 | UINT32 SclkDpmValid0:5 ; ///< |
| 14180 | UINT32 SclkDpmValid1:5 ; ///< |
| 14181 | UINT32 SclkDpmValid2:5 ; ///< |
| 14182 | UINT32 SclkDpmValid3:5 ; ///< |
| 14183 | UINT32 SclkDpmValid4:5 ; ///< |
| 14184 | UINT32 Reserved_31_30:2 ; ///< |
| 14185 | } Field; ///< |
| 14186 | UINT32 Value; ///< |
| 14187 | } FCRxFE00_70BC_STRUCT; |
| 14188 | |
| 14189 | // **** FCRxFE00_70BF Register Definition **** |
| 14190 | // Address |
| 14191 | #define FCRxFE00_70BF_ADDRESS 0xfe0070bf |
| 14192 | |
| 14193 | // Type |
| 14194 | #define FCRxFE00_70BF_TYPE TYPE_FCR |
| 14195 | // Field Data |
| 14196 | #define FCRxFE00_70BF_Reserved_5_0_OFFSET 0 |
| 14197 | #define FCRxFE00_70BF_Reserved_5_0_WIDTH 6 |
| 14198 | #define FCRxFE00_70BF_Reserved_5_0_MASK 0x3f |
| 14199 | #define FCRxFE00_70BF_SclkDpmValid5_OFFSET 6 |
| 14200 | #define FCRxFE00_70BF_SclkDpmValid5_WIDTH 5 |
| 14201 | #define FCRxFE00_70BF_SclkDpmValid5_MASK 0x7c0 |
| 14202 | #define FCRxFE00_70BF_Reserved_31_11_OFFSET 11 |
| 14203 | #define FCRxFE00_70BF_Reserved_31_11_WIDTH 21 |
| 14204 | #define FCRxFE00_70BF_Reserved_31_11_MASK 0xfffff800 |
| 14205 | |
| 14206 | /// FCRxFE00_70BF |
| 14207 | typedef union { |
| 14208 | struct { ///< |
| 14209 | UINT32 Reserved_5_0:6 ; ///< |
| 14210 | UINT32 SclkDpmValid5:5 ; ///< |
| 14211 | UINT32 Reserved_31_11:21; ///< |
| 14212 | } Field; ///< |
| 14213 | UINT32 Value; ///< |
| 14214 | } FCRxFE00_70BF_STRUCT; |
| 14215 | |
| 14216 | // **** FCRxFE00_70C0 Register Definition **** |
| 14217 | // Address |
| 14218 | #define FCRxFE00_70C0_ADDRESS 0xfe0070c0 |
| 14219 | |
| 14220 | // Type |
| 14221 | #define FCRxFE00_70C0_TYPE TYPE_FCR |
| 14222 | // Field Data |
| 14223 | #define FCRxFE00_70C0_Reserved_2_0_OFFSET 0 |
| 14224 | #define FCRxFE00_70C0_Reserved_2_0_WIDTH 3 |
| 14225 | #define FCRxFE00_70C0_Reserved_2_0_MASK 0x7 |
| 14226 | #define FCRxFE00_70C0_PolicyLabel0_OFFSET 3 |
| 14227 | #define FCRxFE00_70C0_PolicyLabel0_WIDTH 2 |
| 14228 | #define FCRxFE00_70C0_PolicyLabel0_MASK 0x18 |
| 14229 | #define FCRxFE00_70C0_PolicyLabel1_OFFSET 5 |
| 14230 | #define FCRxFE00_70C0_PolicyLabel1_WIDTH 2 |
| 14231 | #define FCRxFE00_70C0_PolicyLabel1_MASK 0x60 |
| 14232 | #define FCRxFE00_70C0_PolicyLabel2_OFFSET 7 |
| 14233 | #define FCRxFE00_70C0_PolicyLabel2_WIDTH 2 |
| 14234 | #define FCRxFE00_70C0_PolicyLabel2_MASK 0x180 |
| 14235 | #define FCRxFE00_70C0_PolicyLabel3_OFFSET 9 |
| 14236 | #define FCRxFE00_70C0_PolicyLabel3_WIDTH 2 |
| 14237 | #define FCRxFE00_70C0_PolicyLabel3_MASK 0x600 |
| 14238 | #define FCRxFE00_70C0_PolicyLabel4_OFFSET 11 |
| 14239 | #define FCRxFE00_70C0_PolicyLabel4_WIDTH 2 |
| 14240 | #define FCRxFE00_70C0_PolicyLabel4_MASK 0x1800 |
| 14241 | #define FCRxFE00_70C0_PolicyLabel5_OFFSET 13 |
| 14242 | #define FCRxFE00_70C0_PolicyLabel5_WIDTH 2 |
| 14243 | #define FCRxFE00_70C0_PolicyLabel5_MASK 0x6000 |
| 14244 | #define FCRxFE00_70C0_Reserved_31_15_OFFSET 15 |
| 14245 | #define FCRxFE00_70C0_Reserved_31_15_WIDTH 17 |
| 14246 | #define FCRxFE00_70C0_Reserved_31_15_MASK 0xffff8000 |
| 14247 | |
| 14248 | /// FCRxFE00_70C0 |
| 14249 | typedef union { |
| 14250 | struct { ///< |
| 14251 | UINT32 Reserved_2_0:3 ; ///< |
| 14252 | UINT32 PolicyLabel0:2 ; ///< |
| 14253 | UINT32 PolicyLabel1:2 ; ///< |
| 14254 | UINT32 PolicyLabel2:2 ; ///< |
| 14255 | UINT32 PolicyLabel3:2 ; ///< |
| 14256 | UINT32 PolicyLabel4:2 ; ///< |
| 14257 | UINT32 PolicyLabel5:2 ; ///< |
| 14258 | UINT32 Reserved_31_15:17; ///< |
| 14259 | } Field; ///< |
| 14260 | UINT32 Value; ///< |
| 14261 | } FCRxFE00_70C0_STRUCT; |
| 14262 | |
| 14263 | // **** FCRxFE00_70C1 Register Definition **** |
| 14264 | // Address |
| 14265 | #define FCRxFE00_70C1_ADDRESS 0xfe0070c1 |
| 14266 | |
| 14267 | // Type |
| 14268 | #define FCRxFE00_70C1_TYPE TYPE_FCR |
| 14269 | // Field Data |
| 14270 | #define FCRxFE00_70C1_Reserved_6_0_OFFSET 0 |
| 14271 | #define FCRxFE00_70C1_Reserved_6_0_WIDTH 7 |
| 14272 | #define FCRxFE00_70C1_Reserved_6_0_MASK 0x7f |
| 14273 | #define FCRxFE00_70C1_PolicyFlags0_OFFSET 7 |
| 14274 | #define FCRxFE00_70C1_PolicyFlags0_WIDTH 7 |
| 14275 | #define FCRxFE00_70C1_PolicyFlags0_MASK 0x3f80 |
| 14276 | #define FCRxFE00_70C1_PolicyFlags1_OFFSET 14 |
| 14277 | #define FCRxFE00_70C1_PolicyFlags1_WIDTH 7 |
| 14278 | #define FCRxFE00_70C1_PolicyFlags1_MASK 0x1fc000 |
| 14279 | #define FCRxFE00_70C1_PolicyFlags2_OFFSET 21 |
| 14280 | #define FCRxFE00_70C1_PolicyFlags2_WIDTH 7 |
| 14281 | #define FCRxFE00_70C1_PolicyFlags2_MASK 0xfe00000 |
| 14282 | #define FCRxFE00_70C1_Reserved_31_28_OFFSET 28 |
| 14283 | #define FCRxFE00_70C1_Reserved_31_28_WIDTH 4 |
| 14284 | #define FCRxFE00_70C1_Reserved_31_28_MASK 0xf0000000 |
| 14285 | |
| 14286 | /// FCRxFE00_70C1 |
| 14287 | typedef union { |
| 14288 | struct { ///< |
| 14289 | UINT32 Reserved_6_0:7 ; ///< |
| 14290 | UINT32 PolicyFlags0:7 ; ///< |
| 14291 | UINT32 PolicyFlags1:7 ; ///< |
| 14292 | UINT32 PolicyFlags2:7 ; ///< |
| 14293 | UINT32 Reserved_31_28:4 ; ///< |
| 14294 | } Field; ///< |
| 14295 | UINT32 Value; ///< |
| 14296 | } FCRxFE00_70C1_STRUCT; |
| 14297 | |
| 14298 | // **** FCRxFE00_70C4 Register Definition **** |
| 14299 | // Address |
| 14300 | #define FCRxFE00_70C4_ADDRESS 0xfe0070c4 |
| 14301 | |
| 14302 | // Type |
| 14303 | #define FCRxFE00_70C4_TYPE TYPE_FCR |
| 14304 | // Field Data |
| 14305 | #define FCRxFE00_70C4_Reserved_3_0_OFFSET 0 |
| 14306 | #define FCRxFE00_70C4_Reserved_3_0_WIDTH 4 |
| 14307 | #define FCRxFE00_70C4_Reserved_3_0_MASK 0xf |
| 14308 | #define FCRxFE00_70C4_PolicyFlags3_OFFSET 4 |
| 14309 | #define FCRxFE00_70C4_PolicyFlags3_WIDTH 7 |
| 14310 | #define FCRxFE00_70C4_PolicyFlags3_MASK 0x7f0 |
| 14311 | #define FCRxFE00_70C4_PolicyFlags4_OFFSET 11 |
| 14312 | #define FCRxFE00_70C4_PolicyFlags4_WIDTH 7 |
| 14313 | #define FCRxFE00_70C4_PolicyFlags4_MASK 0x3f800 |
| 14314 | #define FCRxFE00_70C4_PolicyFlags5_OFFSET 18 |
| 14315 | #define FCRxFE00_70C4_PolicyFlags5_WIDTH 7 |
| 14316 | #define FCRxFE00_70C4_PolicyFlags5_MASK 0x1fc0000 |
| 14317 | #define FCRxFE00_70C4_Reserved_31_25_OFFSET 25 |
| 14318 | #define FCRxFE00_70C4_Reserved_31_25_WIDTH 7 |
| 14319 | #define FCRxFE00_70C4_Reserved_31_25_MASK 0xfe000000 |
| 14320 | |
| 14321 | /// FCRxFE00_70C4 |
| 14322 | typedef union { |
| 14323 | struct { ///< |
| 14324 | UINT32 Reserved_3_0:4 ; ///< |
| 14325 | UINT32 PolicyFlags3:7 ; ///< |
| 14326 | UINT32 PolicyFlags4:7 ; ///< |
| 14327 | UINT32 PolicyFlags5:7 ; ///< |
| 14328 | UINT32 Reserved_31_25:7 ; ///< |
| 14329 | } Field; ///< |
| 14330 | UINT32 Value; ///< |
| 14331 | } FCRxFE00_70C4_STRUCT; |
| 14332 | |
| 14333 | // **** FCRxFE00_70C7 Register Definition **** |
| 14334 | // Address |
| 14335 | #define FCRxFE00_70C7_ADDRESS 0xfe0070c7 |
| 14336 | |
| 14337 | // Type |
| 14338 | #define FCRxFE00_70C7_TYPE TYPE_FCR |
| 14339 | // Field Data |
| 14340 | #define FCRxFE00_70C7_Reserved_0_0_OFFSET 0 |
| 14341 | #define FCRxFE00_70C7_Reserved_0_0_WIDTH 1 |
| 14342 | #define FCRxFE00_70C7_Reserved_0_0_MASK 0x1 |
| 14343 | #define FCRxFE00_70C7_DclkVclkSel0_OFFSET 1 |
| 14344 | #define FCRxFE00_70C7_DclkVclkSel0_WIDTH 2 |
| 14345 | #define FCRxFE00_70C7_DclkVclkSel0_MASK 0x6 |
| 14346 | #define FCRxFE00_70C7_DclkVclkSel1_OFFSET 3 |
| 14347 | #define FCRxFE00_70C7_DclkVclkSel1_WIDTH 2 |
| 14348 | #define FCRxFE00_70C7_DclkVclkSel1_MASK 0x18 |
| 14349 | #define FCRxFE00_70C7_DclkVclkSel2_OFFSET 5 |
| 14350 | #define FCRxFE00_70C7_DclkVclkSel2_WIDTH 2 |
| 14351 | #define FCRxFE00_70C7_DclkVclkSel2_MASK 0x60 |
| 14352 | #define FCRxFE00_70C7_DclkVclkSel3_OFFSET 7 |
| 14353 | #define FCRxFE00_70C7_DclkVclkSel3_WIDTH 2 |
| 14354 | #define FCRxFE00_70C7_DclkVclkSel3_MASK 0x180 |
| 14355 | #define FCRxFE00_70C7_DclkVclkSel4_OFFSET 9 |
| 14356 | #define FCRxFE00_70C7_DclkVclkSel4_WIDTH 2 |
| 14357 | #define FCRxFE00_70C7_DclkVclkSel4_MASK 0x600 |
| 14358 | #define FCRxFE00_70C7_DclkVclkSel5_OFFSET 11 |
| 14359 | #define FCRxFE00_70C7_DclkVclkSel5_WIDTH 2 |
| 14360 | #define FCRxFE00_70C7_DclkVclkSel5_MASK 0x1800 |
| 14361 | #define FCRxFE00_70C7_Reserved_31_13_OFFSET 13 |
| 14362 | #define FCRxFE00_70C7_Reserved_31_13_WIDTH 19 |
| 14363 | #define FCRxFE00_70C7_Reserved_31_13_MASK 0xffffe000 |
| 14364 | |
| 14365 | /// FCRxFE00_70C7 |
| 14366 | typedef union { |
| 14367 | struct { ///< |
| 14368 | UINT32 Reserved_0_0:1 ; ///< |
| 14369 | UINT32 DclkVclkSel0:2 ; ///< |
| 14370 | UINT32 DclkVclkSel1:2 ; ///< |
| 14371 | UINT32 DclkVclkSel2:2 ; ///< |
| 14372 | UINT32 DclkVclkSel3:2 ; ///< |
| 14373 | UINT32 DclkVclkSel4:2 ; ///< |
| 14374 | UINT32 DclkVclkSel5:2 ; ///< |
| 14375 | UINT32 Reserved_31_13:19; ///< |
| 14376 | } Field; ///< |
| 14377 | UINT32 Value; ///< |
| 14378 | } FCRxFE00_70C7_STRUCT; |
| 14379 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14380 | // **** SMUx0B_x8490 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14381 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14382 | #define SMUx0B_x8490_ADDRESS 0x8490 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14383 | |
| 14384 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14385 | #define SMUx0B_x8490_TYPE TYPE_SMUx0B |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14386 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14387 | #define SMUx0B_x8490_LclkState0Valid_OFFSET 0 |
| 14388 | #define SMUx0B_x8490_LclkState0Valid_WIDTH 1 |
| 14389 | #define SMUx0B_x8490_LclkState0Valid_MASK 0x1 |
| 14390 | #define SMUx0B_x8490_LclkState1Valid_OFFSET 1 |
| 14391 | #define SMUx0B_x8490_LclkState1Valid_WIDTH 1 |
| 14392 | #define SMUx0B_x8490_LclkState1Valid_MASK 0x2 |
| 14393 | #define SMUx0B_x8490_LclkState2Valid_OFFSET 2 |
| 14394 | #define SMUx0B_x8490_LclkState2Valid_WIDTH 1 |
| 14395 | #define SMUx0B_x8490_LclkState2Valid_MASK 0x4 |
| 14396 | #define SMUx0B_x8490_LclkState3Valid_OFFSET 3 |
| 14397 | #define SMUx0B_x8490_LclkState3Valid_WIDTH 1 |
| 14398 | #define SMUx0B_x8490_LclkState3Valid_MASK 0x8 |
| 14399 | #define SMUx0B_x8490_LclkState4Valid_OFFSET 4 |
| 14400 | #define SMUx0B_x8490_LclkState4Valid_WIDTH 1 |
| 14401 | #define SMUx0B_x8490_LclkState4Valid_MASK 0x10 |
| 14402 | #define SMUx0B_x8490_LclkState5Valid_OFFSET 5 |
| 14403 | #define SMUx0B_x8490_LclkState5Valid_WIDTH 1 |
| 14404 | #define SMUx0B_x8490_LclkState5Valid_MASK 0x20 |
| 14405 | #define SMUx0B_x8490_LclkState6Valid_OFFSET 6 |
| 14406 | #define SMUx0B_x8490_LclkState6Valid_WIDTH 1 |
| 14407 | #define SMUx0B_x8490_LclkState6Valid_MASK 0x40 |
| 14408 | #define SMUx0B_x8490_LclkState7Valid_OFFSET 7 |
| 14409 | #define SMUx0B_x8490_LclkState7Valid_WIDTH 1 |
| 14410 | #define SMUx0B_x8490_LclkState7Valid_MASK 0x80 |
| 14411 | #define SMUx0B_x8490_LclkDivTtExit_OFFSET 8 |
| 14412 | #define SMUx0B_x8490_LclkDivTtExit_WIDTH 8 |
| 14413 | #define SMUx0B_x8490_LclkDivTtExit_MASK 0xff00 |
| 14414 | #define SMUx0B_x8490_MinDivAllowed_OFFSET 16 |
| 14415 | #define SMUx0B_x8490_MinDivAllowed_WIDTH 8 |
| 14416 | #define SMUx0B_x8490_MinDivAllowed_MASK 0xff0000 |
| 14417 | #define SMUx0B_x8490_Reserved_31_24_OFFSET 24 |
| 14418 | #define SMUx0B_x8490_Reserved_31_24_WIDTH 8 |
| 14419 | #define SMUx0B_x8490_Reserved_31_24_MASK 0xff000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14420 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14421 | /// SMUx0B_x8490 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14422 | typedef union { |
| 14423 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14424 | UINT32 LclkState0Valid:1 ; ///< |
| 14425 | UINT32 LclkState1Valid:1 ; ///< |
| 14426 | UINT32 LclkState2Valid:1 ; ///< |
| 14427 | UINT32 LclkState3Valid:1 ; ///< |
| 14428 | UINT32 LclkState4Valid:1 ; ///< |
| 14429 | UINT32 LclkState5Valid:1 ; ///< |
| 14430 | UINT32 LclkState6Valid:1 ; ///< |
| 14431 | UINT32 LclkState7Valid:1 ; ///< |
| 14432 | UINT32 LclkDivTtExit:8 ; ///< |
| 14433 | UINT32 MinDivAllowed:8 ; ///< |
| 14434 | UINT32 Reserved_31_24:8 ; ///< |
| 14435 | } Field; ///< |
| 14436 | UINT32 Value; ///< |
| 14437 | } SMUx0B_x8490_STRUCT; |
| 14438 | |
| 14439 | // **** SMUx35 Register Definition **** |
| 14440 | // Address |
| 14441 | #define SMUx35_ADDRESS 0x35 |
| 14442 | |
| 14443 | // Type |
| 14444 | #define SMUx35_TYPE TYPE_SMU |
| 14445 | // Field Data |
| 14446 | #define SMUx35_DownTrendCoef_OFFSET 0 |
| 14447 | #define SMUx35_DownTrendCoef_WIDTH 10 |
| 14448 | #define SMUx35_DownTrendCoef_MASK 0x3ff |
| 14449 | #define SMUx35_UpTrendCoef_OFFSET 10 |
| 14450 | #define SMUx35_UpTrendCoef_WIDTH 10 |
| 14451 | #define SMUx35_UpTrendCoef_MASK 0xffc00 |
| 14452 | #define SMUx35_Reserved_31_20_OFFSET 20 |
| 14453 | #define SMUx35_Reserved_31_20_WIDTH 12 |
| 14454 | #define SMUx35_Reserved_31_20_MASK 0xfff00000 |
| 14455 | |
| 14456 | /// SMUx35 |
| 14457 | typedef union { |
| 14458 | struct { ///< |
| 14459 | UINT32 DownTrendCoef:10; ///< |
| 14460 | UINT32 UpTrendCoef:10; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14461 | UINT32 Reserved_31_20:12; ///< |
| 14462 | } Field; ///< |
| 14463 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14464 | } SMUx35_STRUCT; |
| 14465 | |
| 14466 | // **** SMUx37 Register Definition **** |
| 14467 | // Address |
| 14468 | #define SMUx37_ADDRESS 0x37 |
| 14469 | |
| 14470 | // Type |
| 14471 | #define SMUx37_TYPE TYPE_SMU |
| 14472 | // Field Data |
| 14473 | #define SMUx37_DownTrendCoef_OFFSET 0 |
| 14474 | #define SMUx37_DownTrendCoef_WIDTH 10 |
| 14475 | #define SMUx37_DownTrendCoef_MASK 0x3ff |
| 14476 | #define SMUx37_UpTrendCoef_OFFSET 10 |
| 14477 | #define SMUx37_UpTrendCoef_WIDTH 10 |
| 14478 | #define SMUx37_UpTrendCoef_MASK 0xffc00 |
| 14479 | #define SMUx37_Reserved_31_20_OFFSET 20 |
| 14480 | #define SMUx37_Reserved_31_20_WIDTH 12 |
| 14481 | #define SMUx37_Reserved_31_20_MASK 0xfff00000 |
| 14482 | |
| 14483 | /// SMUx37 |
| 14484 | typedef union { |
| 14485 | struct { ///< |
| 14486 | UINT32 DownTrendCoef:10; ///< |
| 14487 | UINT32 UpTrendCoef:10; ///< |
| 14488 | UINT32 Reserved_31_20:12; ///< |
| 14489 | } Field; ///< |
| 14490 | UINT32 Value; ///< |
| 14491 | } SMUx37_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14492 | |
| 14493 | // **** FCRxFE00_70AA Register Definition **** |
| 14494 | // Address |
| 14495 | #define FCRxFE00_70AA_ADDRESS 0xfe0070aa |
| 14496 | |
| 14497 | // Type |
| 14498 | #define FCRxFE00_70AA_TYPE TYPE_FCR |
| 14499 | // Field Data |
| 14500 | #define FCRxFE00_70AA_Reserved_0_0_OFFSET 0 |
| 14501 | #define FCRxFE00_70AA_Reserved_0_0_WIDTH 1 |
| 14502 | #define FCRxFE00_70AA_Reserved_0_0_MASK 0x1 |
| 14503 | #define FCRxFE00_70AA_SclkDpmCacBase_OFFSET 1 |
| 14504 | #define FCRxFE00_70AA_SclkDpmCacBase_WIDTH 8 |
| 14505 | #define FCRxFE00_70AA_SclkDpmCacBase_MASK 0x1fe |
| 14506 | #define FCRxFE00_70AA_Reserved_31_9_OFFSET 9 |
| 14507 | #define FCRxFE00_70AA_Reserved_31_9_WIDTH 23 |
| 14508 | #define FCRxFE00_70AA_Reserved_31_9_MASK 0xfffffe00 |
| 14509 | |
| 14510 | /// FCRxFE00_70AA |
| 14511 | typedef union { |
| 14512 | struct { ///< |
| 14513 | UINT32 Reserved_0_0:1 ; ///< |
| 14514 | UINT32 SclkDpmCacBase:8 ; ///< |
| 14515 | UINT32 Reserved_31_9:23; ///< |
| 14516 | } Field; ///< |
| 14517 | UINT32 Value; ///< |
| 14518 | } FCRxFE00_70AA_STRUCT; |
| 14519 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14520 | // **** FCRxFE00_70C8 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14521 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14522 | #define FCRxFE00_70C8_ADDRESS 0xfe0070c8 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14523 | |
| 14524 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14525 | #define FCRxFE00_70C8_TYPE TYPE_FCR |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14526 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14527 | #define FCRxFE00_70C8_Reserved_4_0_OFFSET 0 |
| 14528 | #define FCRxFE00_70C8_Reserved_4_0_WIDTH 5 |
| 14529 | #define FCRxFE00_70C8_Reserved_4_0_MASK 0x1f |
| 14530 | #define FCRxFE00_70C8_GpuBoostCap_OFFSET 5 |
| 14531 | #define FCRxFE00_70C8_GpuBoostCap_WIDTH 1 |
| 14532 | #define FCRxFE00_70C8_GpuBoostCap_MASK 0x20 |
| 14533 | #define FCRxFE00_70C8_SclkDpmDid5_OFFSET 6 |
| 14534 | #define FCRxFE00_70C8_SclkDpmDid5_WIDTH 7 |
| 14535 | #define FCRxFE00_70C8_SclkDpmDid5_MASK 0x00001fc0 |
| 14536 | #define FCRxFE00_70C8_SclkDpmVid5_OFFSET 13 |
| 14537 | #define FCRxFE00_70C8_SclkDpmVid5_WIDTH 2 |
| 14538 | #define FCRxFE00_70C8_SclkDpmVid5_MASK 0x00060000 |
| 14539 | #define FCRxFE00_70C8_Reserved_31_15_OFFSET 15 |
| 14540 | #define FCRxFE00_70C8_Reserved_31_15_WIDTH 17 |
| 14541 | #define FCRxFE00_70C8_Reserved_31_15_MASK 0xffff8000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14542 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14543 | /// FCRxFE00_70C8 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14544 | typedef union { |
| 14545 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14546 | UINT32 Reserved_4_0:5 ; ///< |
| 14547 | UINT32 GpuBoostCap:1 ; ///< |
| 14548 | UINT32 SclkDpmDid5:7 ; ///< |
| 14549 | UINT32 SclkDpmVid5:2 ; ///< |
| 14550 | UINT32 Reserved_31_15:17; ///< |
| 14551 | } Field; ///< |
| 14552 | UINT32 Value; ///< |
| 14553 | } FCRxFE00_70C8_STRUCT; |
| 14554 | |
| 14555 | // **** FCRxFE00_70C9 Register Definition **** |
| 14556 | // Address |
| 14557 | #define FCRxFE00_70C9_ADDRESS 0xfe0070c9 |
| 14558 | |
| 14559 | // Type |
| 14560 | #define FCRxFE00_70C9_TYPE TYPE_FCR |
| 14561 | // Field Data |
| 14562 | #define FCRxFE00_70C9_Reserved_6_0_OFFSET 0 |
| 14563 | #define FCRxFE00_70C9_Reserved_6_0_WIDTH 7 |
| 14564 | #define FCRxFE00_70C9_Reserved_6_0_MASK 0x7f |
| 14565 | #define FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET 7 |
| 14566 | #define FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH 12 |
| 14567 | #define FCRxFE00_70C9_SclkDpmTdpLimit0_MASK 0x7ff80 |
| 14568 | #define FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET 19 |
| 14569 | #define FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH 12 |
| 14570 | #define FCRxFE00_70C9_SclkDpmTdpLimit1_MASK 0x7ff80000 |
| 14571 | #define FCRxFE00_70C9_Reserved_31_31_OFFSET 31 |
| 14572 | #define FCRxFE00_70C9_Reserved_31_31_WIDTH 1 |
| 14573 | #define FCRxFE00_70C9_Reserved_31_31_MASK 0x80000000 |
| 14574 | |
| 14575 | /// FCRxFE00_70C9 |
| 14576 | typedef union { |
| 14577 | struct { ///< |
| 14578 | UINT32 Reserved_6_0:7 ; ///< |
| 14579 | UINT32 SclkDpmTdpLimit0:12; ///< |
| 14580 | UINT32 SclkDpmTdpLimit1:12; ///< |
| 14581 | UINT32 Reserved_31_31:1 ; ///< |
| 14582 | } Field; ///< |
| 14583 | UINT32 Value; ///< |
| 14584 | } FCRxFE00_70C9_STRUCT; |
| 14585 | |
| 14586 | // **** FCRxFE00_70CC Register Definition **** |
| 14587 | // Address |
| 14588 | #define FCRxFE00_70CC_ADDRESS 0xfe0070cc |
| 14589 | |
| 14590 | // Type |
| 14591 | #define FCRxFE00_70CC_TYPE TYPE_FCR |
| 14592 | // Field Data |
| 14593 | #define FCRxFE00_70CC_Reserved_6_0_OFFSET 0 |
| 14594 | #define FCRxFE00_70CC_Reserved_6_0_WIDTH 7 |
| 14595 | #define FCRxFE00_70CC_Reserved_6_0_MASK 0x7f |
| 14596 | #define FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET 7 |
| 14597 | #define FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH 12 |
| 14598 | #define FCRxFE00_70CC_SclkDpmTdpLimit2_MASK 0x7ff80 |
| 14599 | #define FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET 19 |
| 14600 | #define FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH 12 |
| 14601 | #define FCRxFE00_70CC_SclkDpmTdpLimit3_MASK 0x7ff80000 |
| 14602 | #define FCRxFE00_70CC_Reserved_31_31_OFFSET 31 |
| 14603 | #define FCRxFE00_70CC_Reserved_31_31_WIDTH 1 |
| 14604 | #define FCRxFE00_70CC_Reserved_31_31_MASK 0x80000000 |
| 14605 | |
| 14606 | /// FCRxFE00_70CC |
| 14607 | typedef union { |
| 14608 | struct { ///< |
| 14609 | UINT32 Reserved_6_0:7 ; ///< |
| 14610 | UINT32 SclkDpmTdpLimit2:12; ///< |
| 14611 | UINT32 SclkDpmTdpLimit3:12; ///< |
| 14612 | UINT32 Reserved_31_31:1 ; ///< |
| 14613 | } Field; ///< |
| 14614 | UINT32 Value; ///< |
| 14615 | } FCRxFE00_70CC_STRUCT; |
| 14616 | |
| 14617 | // **** FCRxFE00_70CF Register Definition **** |
| 14618 | // Address |
| 14619 | #define FCRxFE00_70CF_ADDRESS 0xfe0070cf |
| 14620 | |
| 14621 | // Type |
| 14622 | #define FCRxFE00_70CF_TYPE TYPE_FCR |
| 14623 | // Field Data |
| 14624 | #define FCRxFE00_70CF_Reserved_6_0_OFFSET 0 |
| 14625 | #define FCRxFE00_70CF_Reserved_6_0_WIDTH 7 |
| 14626 | #define FCRxFE00_70CF_Reserved_6_0_MASK 0x7f |
| 14627 | #define FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET 7 |
| 14628 | #define FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH 12 |
| 14629 | #define FCRxFE00_70CF_SclkDpmTdpLimit4_MASK 0x7ff80 |
| 14630 | #define FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET 19 |
| 14631 | #define FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH 12 |
| 14632 | #define FCRxFE00_70CF_SclkDpmTdpLimit5_MASK 0x7ff80000 |
| 14633 | #define FCRxFE00_70CF_Reserved_31_31_OFFSET 31 |
| 14634 | #define FCRxFE00_70CF_Reserved_31_31_WIDTH 1 |
| 14635 | #define FCRxFE00_70CF_Reserved_31_31_MASK 0x80000000 |
| 14636 | |
| 14637 | /// FCRxFE00_70CF |
| 14638 | typedef union { |
| 14639 | struct { ///< |
| 14640 | UINT32 Reserved_6_0:7 ; ///< |
| 14641 | UINT32 SclkDpmTdpLimit4:12; ///< |
| 14642 | UINT32 SclkDpmTdpLimit5:12; ///< |
| 14643 | UINT32 Reserved_31_31:1 ; ///< |
| 14644 | } Field; ///< |
| 14645 | UINT32 Value; ///< |
| 14646 | } FCRxFE00_70CF_STRUCT; |
| 14647 | |
| 14648 | // **** FCRxFE00_70D2 Register Definition **** |
| 14649 | // Address |
| 14650 | #define FCRxFE00_70D2_ADDRESS 0xfe0070d2 |
| 14651 | |
| 14652 | // Type |
| 14653 | #define FCRxFE00_70D2_TYPE TYPE_FCR |
| 14654 | // Field Data |
| 14655 | #define FCRxFE00_70D2_Reserved_6_0_OFFSET 0 |
| 14656 | #define FCRxFE00_70D2_Reserved_6_0_WIDTH 7 |
| 14657 | #define FCRxFE00_70D2_Reserved_6_0_MASK 0x7f |
| 14658 | #define FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET 7 |
| 14659 | #define FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH 12 |
| 14660 | #define FCRxFE00_70D2_SclkDpmTdpLimitPG_MASK 0x7ff80 |
| 14661 | #define FCRxFE00_70D2_Reserved_31_19_OFFSET 19 |
| 14662 | #define FCRxFE00_70D2_Reserved_31_19_WIDTH 13 |
| 14663 | #define FCRxFE00_70D2_Reserved_31_19_MASK 0xfff80000 |
| 14664 | |
| 14665 | /// FCRxFE00_70D2 |
| 14666 | typedef union { |
| 14667 | struct { ///< |
| 14668 | UINT32 Reserved_6_0:7 ; ///< |
| 14669 | UINT32 SclkDpmTdpLimitPG:12; ///< |
| 14670 | UINT32 Reserved_31_19:13; ///< |
| 14671 | } Field; ///< |
| 14672 | UINT32 Value; ///< |
| 14673 | } FCRxFE00_70D2_STRUCT; |
| 14674 | |
| 14675 | // **** FCRxFE00_70D4 Register Definition **** |
| 14676 | // Address |
| 14677 | #define FCRxFE00_70D4_ADDRESS 0xfe0070d4 |
| 14678 | |
| 14679 | // Type |
| 14680 | #define FCRxFE00_70D4_TYPE TYPE_FCR |
| 14681 | // Field Data |
| 14682 | #define FCRxFE00_70D4_Reserved_2_0_OFFSET 0 |
| 14683 | #define FCRxFE00_70D4_Reserved_2_0_WIDTH 3 |
| 14684 | #define FCRxFE00_70D4_Reserved_2_0_MASK 0x7 |
| 14685 | #define FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET 3 |
| 14686 | #define FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH 21 |
| 14687 | #define FCRxFE00_70D4_SclkDpmBoostMargin_MASK 0xfffff8 |
| 14688 | #define FCRxFE00_70D4_Reserved_31_24_OFFSET 24 |
| 14689 | #define FCRxFE00_70D4_Reserved_31_24_WIDTH 8 |
| 14690 | #define FCRxFE00_70D4_Reserved_31_24_MASK 0xff000000 |
| 14691 | |
| 14692 | /// FCRxFE00_70D4 |
| 14693 | typedef union { |
| 14694 | struct { ///< |
| 14695 | UINT32 Reserved_2_0:3 ; ///< |
| 14696 | UINT32 SclkDpmBoostMargin:21; ///< |
| 14697 | UINT32 Reserved_31_24:8 ; ///< |
| 14698 | } Field; ///< |
| 14699 | UINT32 Value; ///< |
| 14700 | } FCRxFE00_70D4_STRUCT; |
| 14701 | |
| 14702 | // **** FCRxFE00_70D7 Register Definition **** |
| 14703 | // Address |
| 14704 | #define FCRxFE00_70D7_ADDRESS 0xfe0070d7 |
| 14705 | |
| 14706 | // Type |
| 14707 | #define FCRxFE00_70D7_TYPE TYPE_FCR |
| 14708 | // Field Data |
| 14709 | #define FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET 0 |
| 14710 | #define FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH 21 |
| 14711 | #define FCRxFE00_70D7_SclkDpmThrottleMargin_MASK 0x1fffff |
| 14712 | #define FCRxFE00_70D7_Reserved_31_21_OFFSET 21 |
| 14713 | #define FCRxFE00_70D7_Reserved_31_21_WIDTH 11 |
| 14714 | #define FCRxFE00_70D7_Reserved_31_21_MASK 0xffe00000 |
| 14715 | |
| 14716 | /// FCRxFE00_70D7 |
| 14717 | typedef union { |
| 14718 | struct { ///< |
| 14719 | UINT32 SclkDpmThrottleMargin:21; ///< |
| 14720 | UINT32 Reserved_31_21:11; ///< |
| 14721 | } Field; ///< |
| 14722 | UINT32 Value; ///< |
| 14723 | } FCRxFE00_70D7_STRUCT; |
| 14724 | |
| 14725 | // **** SMUx0B_x8410 Register Definition **** |
| 14726 | // Address |
| 14727 | #define SMUx0B_x8410_ADDRESS 0x8410 |
| 14728 | |
| 14729 | // Type |
| 14730 | #define SMUx0B_x8410_TYPE TYPE_SMUx0B |
| 14731 | // Field Data |
| 14732 | #define SMUx0B_x8410_PwrGatingEn_OFFSET 0 |
| 14733 | #define SMUx0B_x8410_PwrGatingEn_WIDTH 1 |
| 14734 | #define SMUx0B_x8410_PwrGatingEn_MASK 0x1 |
| 14735 | #define SMUx0B_x8410_Reserved_2_1_OFFSET 1 |
| 14736 | #define SMUx0B_x8410_Reserved_2_1_WIDTH 2 |
| 14737 | #define SMUx0B_x8410_Reserved_2_1_MASK 0x6 |
| 14738 | #define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 |
| 14739 | #define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 |
| 14740 | #define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 |
| 14741 | #define SMUx0B_x8410_SavePsoDelay_OFFSET 8 |
| 14742 | #define SMUx0B_x8410_SavePsoDelay_WIDTH 4 |
| 14743 | #define SMUx0B_x8410_SavePsoDelay_MASK 0xf00 |
| 14744 | #define SMUx0B_x8410_NRestoreIsoDelay_OFFSET 12 |
| 14745 | #define SMUx0B_x8410_NRestoreIsoDelay_WIDTH 4 |
| 14746 | #define SMUx0B_x8410_NRestoreIsoDelay_MASK 0xf000 |
| 14747 | #define SMUx0B_x8410_RstPulseWidth_OFFSET 16 |
| 14748 | #define SMUx0B_x8410_RstPulseWidth_WIDTH 8 |
| 14749 | #define SMUx0B_x8410_RstPulseWidth_MASK 0xff0000 |
| 14750 | #define SMUx0B_x8410_IsoDelay_OFFSET 24 |
| 14751 | #define SMUx0B_x8410_IsoDelay_WIDTH 4 |
| 14752 | #define SMUx0B_x8410_IsoDelay_MASK 0xf000000 |
| 14753 | #define SMUx0B_x8410_PwrGaterSel_OFFSET 28 |
| 14754 | #define SMUx0B_x8410_PwrGaterSel_WIDTH 4 |
| 14755 | #define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 |
| 14756 | |
| 14757 | /// SMUx0B_x8410 |
| 14758 | typedef union { |
| 14759 | struct { ///< |
| 14760 | UINT32 PwrGatingEn:1 ; ///< |
| 14761 | UINT32 Reserved_2_1:2 ; ///< |
| 14762 | UINT32 PsoControlValidNum:5 ; ///< |
| 14763 | UINT32 SavePsoDelay:4 ; ///< |
| 14764 | UINT32 NRestoreIsoDelay:4 ; ///< |
| 14765 | UINT32 RstPulseWidth:8 ; ///< |
| 14766 | UINT32 IsoDelay:4 ; ///< |
| 14767 | UINT32 PwrGaterSel:4 ; ///< |
| 14768 | } Field; ///< |
| 14769 | UINT32 Value; ///< |
| 14770 | } SMUx0B_x8410_STRUCT; |
| 14771 | |
| 14772 | // **** SMUx0B_x8504 Register Definition **** |
| 14773 | // Address |
| 14774 | #define SMUx0B_x8504_ADDRESS 0x8504 |
| 14775 | |
| 14776 | // Type |
| 14777 | #define SMUx0B_x8504_TYPE TYPE_SMUx0B |
| 14778 | // Field Data |
| 14779 | #define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0 |
| 14780 | #define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8 |
| 14781 | #define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff |
| 14782 | #define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8 |
| 14783 | #define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8 |
| 14784 | #define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00 |
| 14785 | #define SMUx0B_x8504_Reserved_31_16_OFFSET 16 |
| 14786 | #define SMUx0B_x8504_Reserved_31_16_WIDTH 16 |
| 14787 | #define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000 |
| 14788 | |
| 14789 | /// SMUx0B_x8504 |
| 14790 | typedef union { |
| 14791 | struct { ///< |
| 14792 | UINT32 SaveRestoreWidth:8 ; ///< |
| 14793 | UINT32 PsoRestoreTimer:8 ; ///< |
| 14794 | UINT32 Reserved_31_16:16; ///< |
| 14795 | } Field; ///< |
| 14796 | UINT32 Value; ///< |
| 14797 | } SMUx0B_x8504_STRUCT; |
| 14798 | |
| 14799 | // **** SMUx0B_x8408 Register Definition **** |
| 14800 | // Address |
| 14801 | #define SMUx0B_x8408_ADDRESS 0x8408 |
| 14802 | |
| 14803 | // Type |
| 14804 | #define SMUx0B_x8408_TYPE TYPE_SMUx0B |
| 14805 | // Field Data |
| 14806 | #define SMUx0B_x8408_PsoControlId0_OFFSET 0 |
| 14807 | #define SMUx0B_x8408_PsoControlId0_WIDTH 4 |
| 14808 | #define SMUx0B_x8408_PsoControlId0_MASK 0xf |
| 14809 | #define SMUx0B_x8408_PsoControlId1_OFFSET 4 |
| 14810 | #define SMUx0B_x8408_PsoControlId1_WIDTH 4 |
| 14811 | #define SMUx0B_x8408_PsoControlId1_MASK 0xf0 |
| 14812 | #define SMUx0B_x8408_PsoControlId2_OFFSET 8 |
| 14813 | #define SMUx0B_x8408_PsoControlId2_WIDTH 4 |
| 14814 | #define SMUx0B_x8408_PsoControlId2_MASK 0xf00 |
| 14815 | #define SMUx0B_x8408_PsoControlId3_OFFSET 12 |
| 14816 | #define SMUx0B_x8408_PsoControlId3_WIDTH 4 |
| 14817 | #define SMUx0B_x8408_PsoControlId3_MASK 0xf000 |
| 14818 | #define SMUx0B_x8408_PsoControlId4_OFFSET 16 |
| 14819 | #define SMUx0B_x8408_PsoControlId4_WIDTH 4 |
| 14820 | #define SMUx0B_x8408_PsoControlId4_MASK 0xf0000 |
| 14821 | #define SMUx0B_x8408_PsoControlId5_OFFSET 20 |
| 14822 | #define SMUx0B_x8408_PsoControlId5_WIDTH 4 |
| 14823 | #define SMUx0B_x8408_PsoControlId5_MASK 0xf00000 |
| 14824 | #define SMUx0B_x8408_PsoControlId6_OFFSET 24 |
| 14825 | #define SMUx0B_x8408_PsoControlId6_WIDTH 4 |
| 14826 | #define SMUx0B_x8408_PsoControlId6_MASK 0xf000000 |
| 14827 | #define SMUx0B_x8408_PsoControlId7_OFFSET 28 |
| 14828 | #define SMUx0B_x8408_PsoControlId7_WIDTH 4 |
| 14829 | #define SMUx0B_x8408_PsoControlId7_MASK 0xf0000000 |
| 14830 | |
| 14831 | /// SMUx0B_x8408 |
| 14832 | typedef union { |
| 14833 | struct { ///< |
| 14834 | UINT32 PsoControlId0:4 ; ///< |
| 14835 | UINT32 PsoControlId1:4 ; ///< |
| 14836 | UINT32 PsoControlId2:4 ; ///< |
| 14837 | UINT32 PsoControlId3:4 ; ///< |
| 14838 | UINT32 PsoControlId4:4 ; ///< |
| 14839 | UINT32 PsoControlId5:4 ; ///< |
| 14840 | UINT32 PsoControlId6:4 ; ///< |
| 14841 | UINT32 PsoControlId7:4 ; ///< |
| 14842 | } Field; ///< |
| 14843 | UINT32 Value; ///< |
| 14844 | } SMUx0B_x8408_STRUCT; |
| 14845 | |
| 14846 | // **** FCRxFF30_0398 Register Definition **** |
| 14847 | // Address |
| 14848 | #define FCRxFF30_0398_ADDRESS 0xff300398 |
| 14849 | |
| 14850 | // Type |
| 14851 | #define FCRxFF30_0398_TYPE TYPE_FCR |
| 14852 | // Field Data |
| 14853 | #define FCRxFF30_0398_Reserved_0_0_OFFSET 0 |
| 14854 | #define FCRxFF30_0398_Reserved_0_0_WIDTH 1 |
| 14855 | #define FCRxFF30_0398_Reserved_0_0_MASK 0x1 |
| 14856 | #define FCRxFF30_0398_SoftResetCg_OFFSET 2 |
| 14857 | #define FCRxFF30_0398_SoftResetCg_WIDTH 1 |
| 14858 | #define FCRxFF30_0398_SoftResetCg_MASK 0x4 |
| 14859 | #define FCRxFF30_0398_Reserved_4_3_OFFSET 3 |
| 14860 | #define FCRxFF30_0398_Reserved_4_3_WIDTH 2 |
| 14861 | #define FCRxFF30_0398_Reserved_4_3_MASK 0x18 |
| 14862 | #define FCRxFF30_0398_SoftResetDc_OFFSET 5 |
| 14863 | #define FCRxFF30_0398_SoftResetDc_WIDTH 1 |
| 14864 | #define FCRxFF30_0398_SoftResetDc_MASK 0x20 |
| 14865 | #define FCRxFF30_0398_Reserved_6_6_OFFSET 6 |
| 14866 | #define FCRxFF30_0398_Reserved_6_6_WIDTH 1 |
| 14867 | #define FCRxFF30_0398_Reserved_6_6_MASK 0x40 |
| 14868 | #define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 |
| 14869 | #define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 |
| 14870 | #define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 |
| 14871 | #define FCRxFF30_0398_SoftResetMc_OFFSET 11 |
| 14872 | #define FCRxFF30_0398_SoftResetMc_WIDTH 1 |
| 14873 | #define FCRxFF30_0398_SoftResetMc_MASK 0x800 |
| 14874 | #define FCRxFF30_0398_Reserved_12_12_OFFSET 12 |
| 14875 | #define FCRxFF30_0398_Reserved_12_12_WIDTH 1 |
| 14876 | #define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 |
| 14877 | #define FCRxFF30_0398_SoftResetRlc_OFFSET 13 |
| 14878 | #define FCRxFF30_0398_SoftResetRlc_WIDTH 1 |
| 14879 | #define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 |
| 14880 | #define FCRxFF30_0398_Reserved_16_16_OFFSET 16 |
| 14881 | #define FCRxFF30_0398_Reserved_16_16_WIDTH 1 |
| 14882 | #define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 |
| 14883 | #define FCRxFF30_0398_SoftResetUvd_OFFSET 18 |
| 14884 | #define FCRxFF30_0398_SoftResetUvd_WIDTH 1 |
| 14885 | #define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 |
| 14886 | #define FCRxFF30_0398_Reserved_19_19_OFFSET 19 |
| 14887 | #define FCRxFF30_0398_Reserved_19_19_WIDTH 1 |
| 14888 | #define FCRxFF30_0398_Reserved_19_19_MASK 0x80000 |
| 14889 | |
| 14890 | #define FCRxFF30_0398_Reserved_31_24_OFFSET 24 |
| 14891 | #define FCRxFF30_0398_Reserved_31_24_WIDTH 8 |
| 14892 | #define FCRxFF30_0398_Reserved_31_24_MASK 0xff000000 |
| 14893 | |
| 14894 | /// FCRxFF30_0398 |
| 14895 | typedef union { |
| 14896 | struct { ///< |
| 14897 | UINT32 Reserved_0_0:1 ; ///< |
| 14898 | UINT32 Reserved_1_1:1 ; ///< |
| 14899 | UINT32 SoftResetCg:1 ; ///< |
| 14900 | UINT32 Reserved_4_3:2 ; ///< |
| 14901 | UINT32 SoftResetDc:1 ; ///< |
| 14902 | UINT32 Reserved_6_6:1 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14903 | UINT32 Reserved_7_7:1 ; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14904 | UINT32 SoftResetGrbm:1 ; ///< |
| 14905 | UINT32 Reserved_9_9:1 ; ///< |
| 14906 | UINT32 Reserved_10_10:1 ; ///< |
| 14907 | UINT32 SoftResetMc:1 ; ///< |
| 14908 | UINT32 Reserved_12_12:1 ; ///< |
| 14909 | UINT32 SoftResetRlc:1 ; ///< |
| 14910 | UINT32 Reserved_14_14:1 ; ///< |
| 14911 | UINT32 Reserved_15_15:1 ; ///< |
| 14912 | UINT32 Reserved_16_16:1 ; ///< |
| 14913 | UINT32 Reserved_17_17:1 ; ///< |
| 14914 | UINT32 SoftResetUvd:1 ; ///< |
| 14915 | UINT32 Reserved_19_19:1 ; ///< |
| 14916 | UINT32 Reserved_20_20:1 ; ///< |
| 14917 | UINT32 Reserved_21_21:1 ; ///< |
| 14918 | UINT32 Reserved_22_22:1 ; ///< |
| 14919 | UINT32 Reserved_23_23:1 ; ///< |
| 14920 | UINT32 Reserved_31_24:8 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14921 | } Field; ///< |
| 14922 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14923 | } FCRxFF30_0398_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14924 | |
| 14925 | // **** FCRxFF30_1512 Register Definition **** |
| 14926 | // Address |
| 14927 | #define FCRxFF30_1512_ADDRESS 0xff301512 |
| 14928 | |
| 14929 | // Type |
| 14930 | #define FCRxFF30_1512_TYPE TYPE_FCR |
| 14931 | // Field Data |
| 14932 | #define FCRxFF30_1512_Reserved_30_0_OFFSET 0 |
| 14933 | #define FCRxFF30_1512_Reserved_30_0_WIDTH 31 |
| 14934 | #define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff |
| 14935 | #define FCRxFF30_1512_SoftOverride0_OFFSET 31 |
| 14936 | #define FCRxFF30_1512_SoftOverride0_WIDTH 1 |
| 14937 | #define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 |
| 14938 | |
| 14939 | /// FCRxFF30_1512 |
| 14940 | typedef union { |
| 14941 | struct { ///< |
| 14942 | UINT32 Reserved_30_0:31; ///< |
| 14943 | UINT32 SoftOverride0:1 ; ///< |
| 14944 | } Field; ///< |
| 14945 | UINT32 Value; ///< |
| 14946 | } FCRxFF30_1512_STRUCT; |
| 14947 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14948 | // **** SMUx0B_x84A0 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14949 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14950 | #define SMUx0B_x84A0_ADDRESS 0x84a0 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14951 | |
| 14952 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14953 | #define SMUx0B_x84A0_TYPE TYPE_SMUx0B |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14954 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14955 | #define SMUx0B_x84A0_MothPsoPwrup_OFFSET 0 |
| 14956 | #define SMUx0B_x84A0_MothPsoPwrup_WIDTH 16 |
| 14957 | #define SMUx0B_x84A0_MothPsoPwrup_MASK 0xffff |
| 14958 | #define SMUx0B_x84A0_MothPsoPwrdn_OFFSET 16 |
| 14959 | #define SMUx0B_x84A0_MothPsoPwrdn_WIDTH 16 |
| 14960 | #define SMUx0B_x84A0_MothPsoPwrdn_MASK 0xffff0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14961 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14962 | /// SMUx0B_x84A0 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14963 | typedef union { |
| 14964 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14965 | UINT32 MothPsoPwrup:16; ///< |
| 14966 | UINT32 MothPsoPwrdn:16; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14967 | } Field; ///< |
| 14968 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14969 | } SMUx0B_x84A0_STRUCT; |
| 14970 | // **** GMMxCAC Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14971 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14972 | #define GMMxCAC_ADDRESS 0xcac |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14973 | |
| 14974 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14975 | #define GMMxCAC_TYPE TYPE_GMM |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14976 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 14977 | #define GMMxCAC_NbPstateChangeEnable_OFFSET 0 |
| 14978 | #define GMMxCAC_NbPstateChangeEnable_WIDTH 1 |
| 14979 | #define GMMxCAC_NbPstateChangeEnable_MASK 0x1 |
| 14980 | #define GMMxCAC_Reserved_3_1_OFFSET 1 |
| 14981 | #define GMMxCAC_Reserved_3_1_WIDTH 3 |
| 14982 | #define GMMxCAC_Reserved_3_1_MASK 0xe |
| 14983 | #define GMMxCAC_NbPstateChangeUrgentDuringRequest_OFFSET 4 |
| 14984 | #define GMMxCAC_NbPstateChangeUrgentDuringRequest_WIDTH 1 |
| 14985 | #define GMMxCAC_NbPstateChangeUrgentDuringRequest_MASK 0x10 |
| 14986 | #define GMMxCAC_Reserved_7_5_OFFSET 5 |
| 14987 | #define GMMxCAC_Reserved_7_5_WIDTH 3 |
| 14988 | #define GMMxCAC_Reserved_7_5_MASK 0xe0 |
| 14989 | #define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8 |
| 14990 | #define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1 |
| 14991 | #define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100 |
| 14992 | #define GMMxCAC_NbPstateChangeForceOn_OFFSET 9 |
| 14993 | #define GMMxCAC_NbPstateChangeForceOn_WIDTH 1 |
| 14994 | #define GMMxCAC_NbPstateChangeForceOn_MASK 0x200 |
| 14995 | #define GMMxCAC_Reserved_11_10_OFFSET 10 |
| 14996 | #define GMMxCAC_Reserved_11_10_WIDTH 2 |
| 14997 | #define GMMxCAC_Reserved_11_10_MASK 0xc00 |
| 14998 | #define GMMxCAC_NbPstateChangeWatermarkMask_OFFSET 12 |
| 14999 | #define GMMxCAC_NbPstateChangeWatermarkMask_WIDTH 2 |
| 15000 | #define GMMxCAC_NbPstateChangeWatermarkMask_MASK 0x3000 |
| 15001 | #define GMMxCAC_Reserved_15_14_OFFSET 14 |
| 15002 | #define GMMxCAC_Reserved_15_14_WIDTH 2 |
| 15003 | #define GMMxCAC_Reserved_15_14_MASK 0xc000 |
| 15004 | #define GMMxCAC_NbPstateChangeWatermark_OFFSET 16 |
| 15005 | #define GMMxCAC_NbPstateChangeWatermark_WIDTH 16 |
| 15006 | #define GMMxCAC_NbPstateChangeWatermark_MASK 0xffff0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15007 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15008 | /// GMMxCAC |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15009 | typedef union { |
| 15010 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15011 | UINT32 NbPstateChangeEnable:1 ; ///< |
| 15012 | UINT32 Reserved_3_1:3 ; ///< |
| 15013 | UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///< |
| 15014 | UINT32 Reserved_7_5:3 ; ///< |
| 15015 | UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///< |
| 15016 | UINT32 NbPstateChangeForceOn:1 ; ///< |
| 15017 | UINT32 Reserved_11_10:2 ; ///< |
| 15018 | UINT32 NbPstateChangeWatermarkMask:2 ; ///< |
| 15019 | UINT32 Reserved_15_14:2 ; ///< |
| 15020 | UINT32 NbPstateChangeWatermark:16; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15021 | } Field; ///< |
| 15022 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15023 | } GMMxCAC_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15024 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15025 | // **** GMMxCCC Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15026 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15027 | #define GMMxCCC_ADDRESS 0xccc |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15028 | |
| 15029 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15030 | #define GMMxCCC_TYPE TYPE_GMM |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15031 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15032 | #define GMMxCCC_NbPstateChangeEnable_OFFSET 0 |
| 15033 | #define GMMxCCC_NbPstateChangeEnable_WIDTH 1 |
| 15034 | #define GMMxCCC_NbPstateChangeEnable_MASK 0x1 |
| 15035 | #define GMMxCCC_Reserved_3_1_OFFSET 1 |
| 15036 | #define GMMxCCC_Reserved_3_1_WIDTH 3 |
| 15037 | #define GMMxCCC_Reserved_3_1_MASK 0xe |
| 15038 | #define GMMxCCC_NbPstateChangeUrgentDuringRequest_OFFSET 4 |
| 15039 | #define GMMxCCC_NbPstateChangeUrgentDuringRequest_WIDTH 1 |
| 15040 | #define GMMxCCC_NbPstateChangeUrgentDuringRequest_MASK 0x10 |
| 15041 | #define GMMxCCC_Reserved_7_5_OFFSET 5 |
| 15042 | #define GMMxCCC_Reserved_7_5_WIDTH 3 |
| 15043 | #define GMMxCCC_Reserved_7_5_MASK 0xe0 |
| 15044 | #define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8 |
| 15045 | #define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1 |
| 15046 | #define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100 |
| 15047 | #define GMMxCCC_NbPstateChangeForceOn_OFFSET 9 |
| 15048 | #define GMMxCCC_NbPstateChangeForceOn_WIDTH 1 |
| 15049 | #define GMMxCCC_NbPstateChangeForceOn_MASK 0x200 |
| 15050 | #define GMMxCCC_Reserved_11_10_OFFSET 10 |
| 15051 | #define GMMxCCC_Reserved_11_10_WIDTH 2 |
| 15052 | #define GMMxCCC_Reserved_11_10_MASK 0xc00 |
| 15053 | #define GMMxCCC_NbPstateChangeWatermarkMask_OFFSET 12 |
| 15054 | #define GMMxCCC_NbPstateChangeWatermarkMask_WIDTH 2 |
| 15055 | #define GMMxCCC_NbPstateChangeWatermarkMask_MASK 0x3000 |
| 15056 | #define GMMxCCC_Reserved_15_14_OFFSET 14 |
| 15057 | #define GMMxCCC_Reserved_15_14_WIDTH 2 |
| 15058 | #define GMMxCCC_Reserved_15_14_MASK 0xc000 |
| 15059 | #define GMMxCCC_NbPstateChangeWatermark_OFFSET 16 |
| 15060 | #define GMMxCCC_NbPstateChangeWatermark_WIDTH 16 |
| 15061 | #define GMMxCCC_NbPstateChangeWatermark_MASK 0xffff0000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15062 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15063 | /// GMMxCCC |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15064 | typedef union { |
| 15065 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15066 | UINT32 NbPstateChangeEnable:1 ; ///< |
| 15067 | UINT32 Reserved_3_1:3 ; ///< |
| 15068 | UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///< |
| 15069 | UINT32 Reserved_7_5:3 ; ///< |
| 15070 | UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///< |
| 15071 | UINT32 NbPstateChangeForceOn:1 ; ///< |
| 15072 | UINT32 Reserved_11_10:2 ; ///< |
| 15073 | UINT32 NbPstateChangeWatermarkMask:2 ; ///< |
| 15074 | UINT32 Reserved_15_14:2 ; ///< |
| 15075 | UINT32 NbPstateChangeWatermark:16; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15076 | } Field; ///< |
| 15077 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15078 | } GMMxCCC_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15079 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15080 | // **** GMMx6B30 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15081 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15082 | #define GMMx6B30_ADDRESS 0x6b30 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15083 | |
| 15084 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15085 | #define GMMx6B30_TYPE TYPE_GMM |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15086 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15087 | #define GMMx6B30_DcAllowNbPstatesForceOne_OFFSET 25 |
| 15088 | #define GMMx6B30_DcAllowNbPstatesForceOne_WIDTH 1 |
| 15089 | #define GMMx6B30_DcAllowNbPstatesForceOne_MASK 0x2000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15090 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15091 | /// GMMx6B30 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15092 | typedef union { |
| 15093 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15094 | UINT32 Reserved_0_24:25 ; ///< |
| 15095 | UINT32 DcAllowNbPstatesForceOne:1 ; ///< |
| 15096 | UINT32 Reserved_31_26:6 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15097 | } Field; ///< |
| 15098 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15099 | } GMMx6B30_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15100 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15101 | // **** GMMx7730 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15102 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15103 | #define GMMx7730_ADDRESS 0x7730 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15104 | |
| 15105 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15106 | #define GMMx7730_TYPE TYPE_GMM |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15107 | // Field Data |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15108 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15109 | #define GMMx7730_DcAllowNbPstatesForceOne_OFFSET 25 |
| 15110 | #define GMMx7730_DcAllowNbPstatesForceOne_WIDTH 1 |
| 15111 | #define GMMx7730_DcAllowNbPstatesForceOne_MASK 0x2000000 |
| 15112 | |
| 15113 | /// GMMx7730 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15114 | typedef union { |
| 15115 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15116 | UINT32 Reserved_0_24:25 ; ///< |
| 15117 | UINT32 DcAllowNbPstatesForceOne:1 ; ///< |
| 15118 | UINT32 Reserved_31_26:6 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15119 | } Field; ///< |
| 15120 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15121 | } GMMx7730_STRUCT; |
| 15122 | // **** GMMx2854 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15123 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15124 | #define GMMx2854_ADDRESS 0x2854 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15125 | |
| 15126 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15127 | #define GMMx2854_TYPE TYPE_GMM |
| 15128 | // **** D0F0x98_x0C Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15129 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15130 | #define D0F0x98_x0C_ADDRESS 0xc |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15131 | |
| 15132 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15133 | #define D0F0x98_x0C_TYPE TYPE_D0F0x98 |
| 15134 | #define D0F0x98_x0C_IntrHiPriClr_OFFSET 31 |
| 15135 | #define D0F0x98_x0C_IntrHiPriClr_WIDTH 1 |
| 15136 | #define D0F0x98_x0C_IntrHiPriClr_MASK 0x80000000 |
| 15137 | // **** D0F0x98_x0D Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15138 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15139 | #define D0F0x98_x0D_ADDRESS 0xd |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15140 | |
| 15141 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15142 | #define D0F0x98_x0D_TYPE TYPE_D0F0x98 |
| 15143 | // **** D18F3xA0 Register Definition **** |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15144 | // Address |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15145 | #define D18F3xA0_ADDRESS 0xa0 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15146 | |
| 15147 | // Type |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15148 | #define D18F3xA0_TYPE TYPE_D18F3 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15149 | // Field Data |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15150 | #define D18F3xA0_PsiVid_OFFSET 0 |
| 15151 | #define D18F3xA0_PsiVid_WIDTH 7 |
| 15152 | #define D18F3xA0_PsiVid_MASK 0x7f |
| 15153 | #define D18F3xA0_PsiVidEn_OFFSET 7 |
| 15154 | #define D18F3xA0_PsiVidEn_WIDTH 1 |
| 15155 | #define D18F3xA0_PsiVidEn_MASK 0x80 |
| 15156 | #define D18F3xA0_Reserved_8_8_OFFSET 8 |
| 15157 | #define D18F3xA0_Reserved_8_8_WIDTH 1 |
| 15158 | #define D18F3xA0_Reserved_8_8_MASK 0x100 |
| 15159 | #define D18F3xA0_SviHighFreqSel_OFFSET 9 |
| 15160 | #define D18F3xA0_SviHighFreqSel_WIDTH 1 |
| 15161 | #define D18F3xA0_SviHighFreqSel_MASK 0x200 |
| 15162 | #define D18F3xA0_Reserved_15_10_OFFSET 10 |
| 15163 | #define D18F3xA0_Reserved_15_10_WIDTH 6 |
| 15164 | #define D18F3xA0_Reserved_15_10_MASK 0xfc00 |
| 15165 | #define D18F3xA0_ConfigId_OFFSET 16 |
| 15166 | #define D18F3xA0_ConfigId_WIDTH 12 |
| 15167 | #define D18F3xA0_ConfigId_MASK 0xfff0000 |
| 15168 | #define D18F3xA0_Reserved_30_28_OFFSET 28 |
| 15169 | #define D18F3xA0_Reserved_30_28_WIDTH 3 |
| 15170 | #define D18F3xA0_Reserved_30_28_MASK 0x70000000 |
| 15171 | #define D18F3xA0_CofVidProg_OFFSET 31 |
| 15172 | #define D18F3xA0_CofVidProg_WIDTH 1 |
| 15173 | #define D18F3xA0_CofVidProg_MASK 0x80000000 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15174 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15175 | /// D18F3xA0 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15176 | typedef union { |
| 15177 | struct { ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15178 | UINT32 PsiVid:7 ; ///< |
| 15179 | UINT32 PsiVidEn:1 ; ///< |
| 15180 | UINT32 Reserved_8_8:1 ; ///< |
| 15181 | UINT32 SviHighFreqSel:1 ; ///< |
| 15182 | UINT32 Reserved_15_10:6 ; ///< |
| 15183 | UINT32 ConfigId:12; ///< |
| 15184 | UINT32 Reserved_30_28:3 ; ///< |
| 15185 | UINT32 CofVidProg:1 ; ///< |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15186 | } Field; ///< |
| 15187 | UINT32 Value; ///< |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15188 | } D18F3xA0_STRUCT; |
| 15189 | // **** D18F6x110 Register Definition **** |
| 15190 | // Address |
| 15191 | #define D18F6x110_ADDRESS 0x110 |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15192 | |
| efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 15193 | // Type |
| 15194 | #define D18F6x110_TYPE TYPE_D18F6 |
| 15195 | // Field Data |
| 15196 | #define D18F6x110_NclkFifoOff_OFFSET 0 |
| 15197 | #define D18F6x110_NclkFifoOff_WIDTH 3 |
| 15198 | #define D18F6x110_NclkFifoOff_MASK 0x7 |
| 15199 | #define D18F6x110_Reserved_3_3_OFFSET 3 |
| 15200 | #define D18F6x110_Reserved_3_3_WIDTH 1 |
| 15201 | #define D18F6x110_Reserved_3_3_MASK 0x8 |
| 15202 | #define D18F6x110_LclkFifoOff_OFFSET 4 |
| 15203 | #define D18F6x110_LclkFifoOff_WIDTH 3 |
| 15204 | #define D18F6x110_LclkFifoOff_MASK 0x70 |
| 15205 | #define D18F6x110_Reserved_7_7_OFFSET 7 |
| 15206 | #define D18F6x110_Reserved_7_7_WIDTH 1 |
| 15207 | #define D18F6x110_Reserved_7_7_MASK 0x80 |
| 15208 | #define D18F6x110_PllMult_OFFSET 8 |
| 15209 | #define D18F6x110_PllMult_WIDTH 6 |
| 15210 | #define D18F6x110_PllMult_MASK 0x3f00 |
| 15211 | #define D18F6x110_Reserved_14_14_OFFSET 14 |
| 15212 | #define D18F6x110_Reserved_14_14_WIDTH 1 |
| 15213 | #define D18F6x110_Reserved_14_14_MASK 0x4000 |
| 15214 | #define D18F6x110_Enable_OFFSET 15 |
| 15215 | #define D18F6x110_Enable_WIDTH 1 |
| 15216 | #define D18F6x110_Enable_MASK 0x8000 |
| 15217 | #define D18F6x110_LclkFreq_OFFSET 16 |
| 15218 | #define D18F6x110_LclkFreq_WIDTH 7 |
| 15219 | #define D18F6x110_LclkFreq_MASK 0x7f0000 |
| 15220 | #define D18F6x110_LclkFreqType_OFFSET 23 |
| 15221 | #define D18F6x110_LclkFreqType_WIDTH 1 |
| 15222 | #define D18F6x110_LclkFreqType_MASK 0x800000 |
| 15223 | #define D18F6x110_NclkFreq_OFFSET 24 |
| 15224 | #define D18F6x110_NclkFreq_WIDTH 7 |
| 15225 | #define D18F6x110_NclkFreq_MASK 0x7f000000 |
| 15226 | #define D18F6x110_NclkFreqType_OFFSET 31 |
| 15227 | #define D18F6x110_NclkFreqType_WIDTH 1 |
| 15228 | #define D18F6x110_NclkFreqType_MASK 0x80000000 |
| 15229 | |
| 15230 | /// D18F6x110 |
| 15231 | typedef union { |
| 15232 | struct { ///< |
| 15233 | UINT32 NclkFifoOff:3 ; ///< |
| 15234 | UINT32 Reserved_3_3:1 ; ///< |
| 15235 | UINT32 LclkFifoOff:3 ; ///< |
| 15236 | UINT32 Reserved_7_7:1 ; ///< |
| 15237 | UINT32 PllMult:6 ; ///< |
| 15238 | UINT32 Reserved_14_14:1 ; ///< |
| 15239 | UINT32 Enable:1 ; ///< |
| 15240 | UINT32 LclkFreq:7 ; ///< |
| 15241 | UINT32 LclkFreqType:1 ; ///< |
| 15242 | UINT32 NclkFreq:7 ; ///< |
| 15243 | UINT32 NclkFreqType:1 ; ///< |
| 15244 | } Field; ///< |
| 15245 | UINT32 Value; ///< |
| 15246 | } D18F6x110_STRUCT; |
| Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 15247 | #endif |