Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD AGESA Basic Level Public APIs |
| 6 | * |
| 7 | * Contains basic Level Initialization routines. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: Interface |
| 12 | * @e \$Revision: 36908 $ @e \$Date: 2010-08-27 09:19:54 +0800 (Fri, 27 Aug 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | |
| 48 | /*---------------------------------------------------------------------------------------- |
| 49 | * M O D U L E S U S E D |
| 50 | *---------------------------------------------------------------------------------------- |
| 51 | */ |
| 52 | #include "AGESA.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "Ids.h" |
| 55 | #include "cpuCacheInit.h" |
| 56 | #include "cpuServices.h" |
| 57 | #include "AdvancedApi.h" |
| 58 | #include "GeneralServices.h" |
| 59 | #include "OptionsHt.h" |
| 60 | #include "Filecode.h" |
| 61 | CODE_GROUP (G1_PEICC) |
| 62 | RDATA_GROUP (G1_PEICC) |
| 63 | |
| 64 | #define FILECODE PROC_COMMON_AMDINITRESET_FILECODE |
| 65 | |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * D E F I N I T I O N S A N D M A C R O S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | extern CONST OPTION_HT_INIT_RESET HtOptionInitReset; |
| 71 | extern BUILD_OPT_CFG UserOptions; |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * T Y P E D E F S A N D S T R U C T U R E S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | /*---------------------------------------------------------------------------------------- |
| 79 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 80 | *---------------------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 83 | AGESA_STATUS |
| 84 | AmdInitResetExecutionCacheAllocateInitializer ( |
| 85 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 86 | IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr |
| 87 | ); |
| 88 | |
| 89 | AGESA_STATUS |
| 90 | AmdInitResetConstructor ( |
| 91 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 92 | IN AMD_RESET_PARAMS *AmdResetParams |
| 93 | ); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 94 | |
| 95 | /*---------------------------------------------------------------------------------------- |
| 96 | * E X P O R T E D F U N C T I O N S |
| 97 | *---------------------------------------------------------------------------------------- |
| 98 | */ |
| 99 | |
| 100 | /*------------------------------------------------------------------------------------*/ |
| 101 | /** |
| 102 | * Initializer routine that will be invoked by the wrapper to initialize the input |
| 103 | * structure for the AllocateExecutionCache. |
| 104 | * |
| 105 | * Parameters: |
| 106 | * @param[in] StdHeader Opaque handle to standard config header |
| 107 | * @param[in] AmdExeAddrMapPtr Our Service interface struct |
| 108 | * |
| 109 | * @retval AGESA_SUCCESS Always Succeeds. |
| 110 | * |
| 111 | */ |
| 112 | AGESA_STATUS |
| 113 | AmdInitResetExecutionCacheAllocateInitializer ( |
| 114 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 115 | IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr |
| 116 | ) |
| 117 | { |
| 118 | ASSERT (AmdExeAddrMapPtr != NULL); |
| 119 | |
| 120 | LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader); |
| 121 | |
| 122 | return AGESA_SUCCESS; |
| 123 | } |
| 124 | /*---------------------------------------------------------------------------------------*/ |
| 125 | /** |
| 126 | * Main entry point for the AMD_INIT_RESET function. |
| 127 | * |
| 128 | * This entry point is responsible for establishing the HT links to the program |
| 129 | * ROM and for performing basic processor initialization. |
| 130 | * |
| 131 | * @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET |
| 132 | * entry point. |
| 133 | * |
| 134 | * @return Aggregated status across all internal AMD reset calls invoked. |
| 135 | * |
| 136 | */ |
| 137 | AGESA_STATUS |
| 138 | AmdInitReset ( |
| 139 | IN OUT AMD_RESET_PARAMS *ResetParams |
| 140 | ) |
| 141 | { |
| 142 | AGESA_STATUS AgesaStatus; |
| 143 | AGESA_STATUS CalledAgesaStatus; |
| 144 | WARM_RESET_REQUEST Request; |
| 145 | UINT8 PrevRequestBit; |
| 146 | UINT8 PrevStateBits; |
| 147 | |
| 148 | // Init Debug Print function |
| 149 | IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader); |
| 150 | IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); |
| 151 | |
| 152 | IDS_HDT_CONSOLE_DEBUG_CODE ( |
| 153 | { |
| 154 | extern CHAR8 *BldOptDebugOutput[]; |
| 155 | |
| 156 | UINT8 i; |
| 157 | for (i = 0; BldOptDebugOutput[i] != NULL; i++) { |
| 158 | IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]); |
| 159 | } |
| 160 | } |
| 161 | ) |
| 162 | |
| 163 | IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); |
| 164 | |
| 165 | AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); |
| 166 | ASSERT (ResetParams != NULL); |
| 167 | |
| 168 | AgesaStatus = AGESA_SUCCESS; |
| 169 | PrevRequestBit = FALSE; |
| 170 | PrevStateBits = WR_STATE_COLD; |
| 171 | |
| 172 | // If a previously requested warm reset cannot be triggered in the |
| 173 | // current stage, store the previous state of request and reset the |
| 174 | // request struct to the current post stage |
| 175 | GetWarmResetFlag (&ResetParams->StdHeader, &Request); |
| 176 | if (Request.RequestBit == TRUE) { |
| 177 | if (Request.StateBits >= Request.PostStage) { |
| 178 | PrevRequestBit = Request.RequestBit; |
| 179 | PrevStateBits = Request.StateBits; |
| 180 | Request.RequestBit = FALSE; |
| 181 | Request.StateBits = Request.PostStage - 1; |
| 182 | SetWarmResetFlag (&ResetParams->StdHeader, &Request); |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n"); |
| 187 | // Setup ROM execution cache |
| 188 | CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]); |
| 189 | IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n"); |
| 190 | if (CalledAgesaStatus > AgesaStatus) { |
| 191 | AgesaStatus = CalledAgesaStatus; |
| 192 | } |
| 193 | |
| 194 | // Initialize the PCI MMIO access mechanism |
| 195 | InitializePciMmio (&ResetParams->StdHeader); |
| 196 | |
| 197 | // Initialize Hyper Transport Registers |
| 198 | if (HtOptionInitReset.HtInitReset != NULL) { |
| 199 | IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n"); |
| 200 | CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig); |
| 201 | IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n"); |
| 202 | if (CalledAgesaStatus > AgesaStatus) { |
| 203 | AgesaStatus = CalledAgesaStatus; |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | // Warm Reset, should be at the end of AmdInitReset |
| 208 | GetWarmResetFlag (&ResetParams->StdHeader, &Request); |
| 209 | // If a warm reset is requested in the current post stage, trigger the |
| 210 | // warm reset and ignore the previous request |
| 211 | if (Request.RequestBit == TRUE) { |
| 212 | if (Request.StateBits < Request.PostStage) { |
| 213 | AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader); |
| 214 | } |
| 215 | } else { |
| 216 | // Otherwise, if there's a previous request, restore it |
| 217 | // so that the subsequent post stage can trigger the warm reset |
| 218 | if (PrevRequestBit == TRUE) { |
| 219 | Request.RequestBit = PrevRequestBit; |
| 220 | Request.StateBits = PrevStateBits; |
| 221 | SetWarmResetFlag (&ResetParams->StdHeader, &Request); |
| 222 | } |
| 223 | } |
| 224 | // Check for Cache As Ram Corruption |
| 225 | IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader); |
| 226 | IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n"); |
| 227 | |
| 228 | AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader); |
| 229 | return AgesaStatus; |
| 230 | } |
| 231 | |
| 232 | /*---------------------------------------------------------------------------------------*/ |
| 233 | /** |
| 234 | * Initialize defaults and options for Amd Init Reset. |
| 235 | * |
| 236 | * @param[in] StdHeader Header |
| 237 | * @param[in] AmdResetParams The Reset Init interface to initialize. |
| 238 | * |
| 239 | * @retval AGESA_SUCCESS Always Succeeds. |
| 240 | */ |
| 241 | AGESA_STATUS |
| 242 | AmdInitResetConstructor ( |
| 243 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 244 | IN AMD_RESET_PARAMS *AmdResetParams |
| 245 | ) |
| 246 | { |
| 247 | ASSERT (AmdResetParams != NULL); |
| 248 | |
| 249 | AmdResetParams->StdHeader = *StdHeader; |
| 250 | |
| 251 | AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]); |
Kyösti Mälkki | 7f937cb | 2017-08-31 22:02:56 +0300 | [diff] [blame] | 252 | // Initialize Hyper Transport input structure |
| 253 | if (HtOptionInitReset.HtResetConstructor != NULL) { |
| 254 | HtOptionInitReset.HtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig); |
| 255 | } |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 256 | |
| 257 | return AGESA_SUCCESS; |
| 258 | } |
| 259 | |