Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD AGESA Basic Level Public APIs |
| 6 | * |
| 7 | * Contains basic Level Initialization routines. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: Interface |
| 12 | * @e \$Revision: 37437 $ @e \$Date: 2010-09-04 01:15:21 +0800 (Sat, 04 Sep 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | |
| 48 | /*---------------------------------------------------------------------------------------- |
| 49 | * M O D U L E S U S E D |
| 50 | *---------------------------------------------------------------------------------------- |
| 51 | */ |
| 52 | #include "AGESA.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "mm.h" |
| 55 | #include "Ids.h" |
| 56 | #include "cpuRegisters.h" |
| 57 | #include "cpuServices.h" |
| 58 | #include "cpuPostInit.h" |
| 59 | #include "AdvancedApi.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 60 | #include "CreateStruct.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 61 | #include "heapManager.h" |
| 62 | #include "CommonInits.h" |
| 63 | #include "cpuServices.h" |
| 64 | #include "GnbInterface.h" |
| 65 | #include "Filecode.h" |
| 66 | CODE_GROUP (G1_PEICC) |
| 67 | RDATA_GROUP (G1_PEICC) |
| 68 | |
| 69 | #define FILECODE PROC_COMMON_AMDINITPOST_FILECODE |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * D E F I N I T I O N S A N D M A C R O S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * T Y P E D E F S A N D S T R U C T U R E S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | |
| 81 | |
| 82 | /*---------------------------------------------------------------------------------------- |
| 83 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 84 | *---------------------------------------------------------------------------------------- |
| 85 | */ |
| 86 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 87 | AGESA_STATUS |
| 88 | AmdPostPlatformConfigInit ( |
| 89 | IN OUT PLATFORM_CONFIGURATION *PlatformConfig, |
| 90 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 91 | ); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 92 | |
| 93 | /*---------------------------------------------------------------------------------------- |
| 94 | * E X P O R T E D F U N C T I O N S |
| 95 | *---------------------------------------------------------------------------------------- |
| 96 | */ |
| 97 | |
| 98 | extern BUILD_OPT_CFG UserOptions; |
| 99 | |
| 100 | /*------------------------------------------------------------------------------------*/ |
| 101 | /** |
| 102 | * Initialize AmdInitPost stage platform profile and user option input. |
| 103 | * |
| 104 | * @param[in,out] PlatformConfig Platform profile/build option config structure |
| 105 | * @param[in,out] StdHeader AMD standard header config param |
| 106 | * |
| 107 | * @retval AGESA_SUCCESS Always Succeeds. |
| 108 | * |
| 109 | */ |
| 110 | AGESA_STATUS |
| 111 | AmdPostPlatformConfigInit ( |
| 112 | IN OUT PLATFORM_CONFIGURATION *PlatformConfig, |
| 113 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 114 | ) |
| 115 | { |
| 116 | CommonPlatformConfigInit (PlatformConfig, StdHeader); |
| 117 | |
| 118 | return AGESA_SUCCESS; |
| 119 | } |
| 120 | |
| 121 | /* |
| 122 | *--------------------------------------------------------------------------------------- |
| 123 | * |
| 124 | * AmdInitPostInitializer |
| 125 | * |
| 126 | * Initializer routine that will be invoked by the wrapper |
| 127 | * to initialize the input structure for the AmdInitPost |
| 128 | * |
| 129 | * @param[in, out] IN OUT AMD_POST_PARAMS *PostParamsPtr |
| 130 | * |
| 131 | * @retval AGESA_STATUS |
| 132 | * |
| 133 | *--------------------------------------------------------------------------------------- |
| 134 | */ |
| 135 | AGESA_STATUS |
| 136 | AmdInitPostInitializer ( |
| 137 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 138 | IN OUT AMD_POST_PARAMS *PostParamsPtr |
| 139 | ) |
| 140 | { |
| 141 | AGESA_STATUS AgesaStatus; |
| 142 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 143 | |
| 144 | ASSERT (StdHeader != NULL); |
| 145 | ASSERT (PostParamsPtr != NULL); |
| 146 | |
| 147 | PostParamsPtr->StdHeader = *StdHeader; |
| 148 | |
| 149 | AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); |
| 150 | AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; |
| 151 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 152 | AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader); |
| 153 | |
| 154 | if (AgesaStatus == AGESA_SUCCESS) { |
| 155 | PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr; |
| 156 | PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig); |
| 157 | PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader; |
| 158 | AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader); |
| 159 | AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig); |
| 160 | } |
| 161 | return AgesaStatus; |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | *--------------------------------------------------------------------------------------- |
| 166 | * |
| 167 | * AmdInitPostDestructor |
| 168 | * |
| 169 | * Destruct routine that provide a chance if something need to be done |
| 170 | * before the end of AmdInitPost. |
| 171 | * |
| 172 | * @param[in] StdHeader The standard header. |
| 173 | * @param[in] PostParamsPtr AMD init post param. |
| 174 | * |
| 175 | * @retval AGESA_STATUS |
| 176 | * |
| 177 | *--------------------------------------------------------------------------------------- |
| 178 | */ |
| 179 | AGESA_STATUS |
| 180 | AmdInitPostDestructor ( |
| 181 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 182 | IN AMD_POST_PARAMS *PostParamsPtr |
| 183 | ) |
| 184 | { |
| 185 | |
| 186 | ASSERT (PostParamsPtr != NULL); |
| 187 | |
| 188 | PostParamsPtr->StdHeader = *StdHeader; |
| 189 | PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader; |
| 190 | |
| 191 | // |
| 192 | // AmdMemAuto completed. Here, release heap space which is used for memory init. |
| 193 | // |
| 194 | MemAmdFinalize (PostParamsPtr->MemConfig.MemData); |
| 195 | HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); |
| 196 | |
| 197 | // |
| 198 | // AmdCpuPost completed. |
| 199 | // |
| 200 | if (PostParamsPtr->MemConfig.SysLimit != 0) { |
| 201 | // WBINVD can only be executed when memory is available |
| 202 | FinalizeAtPost (StdHeader); |
| 203 | } |
| 204 | |
| 205 | return AGESA_SUCCESS; |
| 206 | } |
| 207 | |
| 208 | /*---------------------------------------------------------------------------------------*/ |
| 209 | /** |
| 210 | * Main entry point for the AMD_INIT_POST function. |
| 211 | * |
| 212 | * This entry point is responsible for initializing all system memory, |
| 213 | * gathering important data out of the pre-memory cache storage into a |
| 214 | * temporary holding buffer in main memory. After that APs will be |
| 215 | * shutdown in preparation for the host environment to take control. |
| 216 | * Note: pre-memory stack will be disabled also. |
| 217 | * |
| 218 | * @param[in,out] PostParams Required input parameters for the AMD_INIT_POST |
| 219 | * entry point. |
| 220 | * |
| 221 | * @return Aggregated status across all internal AMD POST calls invoked. |
| 222 | * |
| 223 | */ |
| 224 | AGESA_STATUS |
| 225 | AmdInitPost ( |
| 226 | IN OUT AMD_POST_PARAMS *PostParams |
| 227 | ) |
| 228 | { |
| 229 | AGESA_STATUS AgesaStatus; |
| 230 | AGESA_STATUS AmdInitPostStatus; |
| 231 | WARM_RESET_REQUEST Request; |
| 232 | UINT8 PrevRequestBit; |
| 233 | UINT8 PrevStateBits; |
| 234 | |
| 235 | AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader); |
| 236 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n"); |
| 237 | IDS_PERF_TIME_MEASURE (&PostParams->StdHeader); |
| 238 | |
| 239 | ASSERT (PostParams != NULL); |
| 240 | AmdInitPostStatus = AGESA_SUCCESS; |
| 241 | PrevRequestBit = FALSE; |
| 242 | PrevStateBits = WR_STATE_COLD; |
| 243 | |
| 244 | IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader); |
| 245 | |
| 246 | IDS_OPTION_HOOK (IDS_BEFORE_MEM_INIT, PostParams, &PostParams->StdHeader); |
| 247 | |
| 248 | // If a previously requested warm reset cannot be triggered in the |
| 249 | // current stage, store the previous state of request and reset the |
| 250 | // request struct to the current post stage |
| 251 | GetWarmResetFlag (&PostParams->StdHeader, &Request); |
| 252 | if (Request.RequestBit == TRUE) { |
| 253 | if (Request.StateBits >= Request.PostStage) { |
| 254 | PrevRequestBit = Request.RequestBit; |
| 255 | PrevStateBits = Request.StateBits; |
| 256 | Request.RequestBit = FALSE; |
| 257 | Request.StateBits = Request.PostStage - 1; |
| 258 | SetWarmResetFlag (&PostParams->StdHeader, &Request); |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | AgesaStatus = GnbInitAtPost (PostParams); |
| 263 | if (AgesaStatus > AmdInitPostStatus) { |
| 264 | AmdInitPostStatus = AgesaStatus; |
| 265 | } |
| 266 | |
| 267 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n"); |
| 268 | AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData); |
| 269 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n"); |
| 270 | if (AgesaStatus > AmdInitPostStatus) { |
| 271 | AmdInitPostStatus = AgesaStatus; |
| 272 | } |
| 273 | |
| 274 | if (AgesaStatus != AGESA_FATAL) { |
| 275 | |
| 276 | IDS_OPTION_HOOK (IDS_INIT_POST_MID, PostParams, &PostParams->StdHeader); |
| 277 | |
| 278 | // Check BIST status |
| 279 | AgesaStatus = CheckBistStatus (&PostParams->StdHeader); |
| 280 | if (AgesaStatus > AmdInitPostStatus) { |
| 281 | AmdInitPostStatus = AgesaStatus; |
| 282 | } |
| 283 | |
| 284 | // |
| 285 | // P-State data gathered, then, Relinquish APs |
| 286 | // |
| 287 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n"); |
| 288 | AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig); |
| 289 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n"); |
| 290 | if (AgesaStatus > AmdInitPostStatus) { |
| 291 | AmdInitPostStatus = AgesaStatus; |
| 292 | } |
| 293 | |
| 294 | // Warm Reset |
| 295 | GetWarmResetFlag (&PostParams->StdHeader, &Request); |
| 296 | // If a warm reset is requested in the current post stage, trigger the |
| 297 | // warm reset and ignore the previous request |
| 298 | if (Request.RequestBit == TRUE) { |
| 299 | if (Request.StateBits < Request.PostStage) { |
| 300 | AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader); |
| 301 | } |
| 302 | } else { |
| 303 | // Otherwise, if there's a previous request, restore it |
| 304 | // so that the subsequent post stage can trigger the warm reset |
| 305 | if (PrevRequestBit == TRUE) { |
| 306 | Request.RequestBit = PrevRequestBit; |
| 307 | Request.StateBits = PrevStateBits; |
| 308 | SetWarmResetFlag (&PostParams->StdHeader, &Request); |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | AgesaStatus = GnbInitAtPostAfterDram (PostParams); |
| 313 | if (AgesaStatus > AmdInitPostStatus) { |
| 314 | AmdInitPostStatus = AgesaStatus; |
| 315 | } |
| 316 | |
| 317 | IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader); |
| 318 | |
| 319 | IDS_PERF_TIME_MEASURE (&PostParams->StdHeader); |
| 320 | AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader); |
| 321 | IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n"); |
| 322 | IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n"); |
| 323 | |
| 324 | //For Heap will be relocate to new address in next stage, flush out debug print buffer if needed |
| 325 | IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader); |
| 326 | |
| 327 | // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost |
| 328 | AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader)); |
| 329 | if (AgesaStatus > AmdInitPostStatus) { |
| 330 | AmdInitPostStatus = AgesaStatus; |
| 331 | } |
| 332 | PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; |
| 333 | } |
| 334 | // Check for Cache As Ram Corruption |
| 335 | IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader); |
| 336 | |
| 337 | // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside |
| 338 | // of AGESA to be recognized by IsWarmReset() |
| 339 | GetWarmResetFlag (&PostParams->StdHeader, &Request); |
| 340 | Request.StateBits = Request.PostStage; |
| 341 | SetWarmResetFlag (&PostParams->StdHeader, &Request); |
| 342 | |
| 343 | return AmdInitPostStatus; |
| 344 | } |
| 345 | |