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review.coreboot.org / coreboot / dbdf170dcdf9edbc860766606e53c6d647d89d38 / . / src / vendorcode / amd / agesa / f14 / Proc / CPU / heapManager.h
blob: 6531496946a07c6ef056ab453ab7f7812b4eac7d [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD Heap Manager and Heap Allocation APIs, and related functions.
6 *
7 * Contains code that initialize, maintain, and allocate the heap space.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: CPU
12 * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
13 *
14 */
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]20 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]30 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]31 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]42 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]43 * ***************************************************************************
44 *
45 */
46
47#ifndef _HEAP_MANAGER_H_
48#define _HEAP_MANAGER_H_
49
50/*---------------------------------------------------------------------------------------
51 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
52 *---------------------------------------------------------------------------------------
53 */
54
55
56/*---------------------------------------------------------------------------------------
57 * D E F I N I T I O N S A N D M A C R O S
58 *---------------------------------------------------------------------------------------
59 */
60#define AMD_MTRR_VARIABLE_BASE0 0x200
61#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
62#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
63
64#define AMD_HEAP_START_ADDRESS 0x400000
65#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF
66#define AMD_HEAP_SIZE_PER_CORE 0x010000
67#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFF
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]68#define AMD_HEAP_MTRR_MASK (0xFFFFFFFFFFFFF800ull & (((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800))
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]69#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
70
71#define AMD_TEMP_TOM 0x20000000 // Set TOM to 512 MB (temporary value)
72#define AMD_VAR_MTRR_ENABLE_BIT 0x100000 // bit 20
73
74#define AMD_HEAP_RAM_ADDRESS 0xB0000
75
76#define HEAP_SIGNATURE_VALID 0x50414548 // Signature: 'HEAP'
77#define HEAP_SIGNATURE_INVALID 0x00000000 // Signature cleared
78
79///Heap Manager Life cycle
80#define HEAP_DO_NOT_EXIST_YET 1
81#define HEAP_LOCAL_CACHE 2
82#define HEAP_TEMP_MEM 3
83#define HEAP_SYSTEM_MEM 4
84#define HEAP_DO_NOT_EXIST_ANYMORE 5
85#define HEAP_S3_RESUME 6
86
87
88#define AMD_MTRR_FIX64k_00000 0x250
89#define AMD_MTRR_FIX16k_80000 0x258
90#define AMD_MTRR_FIX16k_A0000 0x259
91#define AMD_MTRR_FIX4k_C0000 0x268
92#define AMD_MTRR_FIX4k_C8000 0x269
93#define AMD_MTRR_FIX4k_D0000 0x26A
94#define AMD_MTRR_FIX4k_D8000 0x26B
95#define AMD_MTRR_FIX4k_E0000 0x26C
96#define AMD_MTRR_FIX4k_E8000 0x26D
97#define AMD_MTRR_FIX4k_F0000 0x26E
98#define AMD_MTRR_FIX4k_F8000 0x26F
99
100#define AMD_MTRR_FIX64K_WB_DRAM 0x1E
101#define AMD_MTRR_FIX64K_WT_DRAM 0x1C
102#define AMD_MTRR_FIX64K_UC_DRAM 0x18
103#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1E
104#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1C
105#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818
106#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1E
107#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1C
108#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818
109
110/*---------------------------------------------------------------------------------------
111 * T Y P E D E F S, S T R U C T U R E S, E N U M S
112 *---------------------------------------------------------------------------------------
113 */
114/// Allocate Heap Parameters
115typedef struct _ALLOCATE_HEAP_PARAMS {
116 UINT32 RequestedBufferSize; ///< Size of buffer.
117 UINT32 BufferHandle; ///< An unique ID of buffer.
118 UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
119 UINT8 *BufferPtr; ///< Pointer to buffer.
120} ALLOCATE_HEAP_PARAMS;
121
122/// Locate Heap Parameters
123typedef struct _LOCATE_HEAP_PTR {
124 UINT32 BufferHandle; ///< An unique ID of buffer.
125 UINT32 BufferSize; ///< Data buffer size.
126 UINT8 *BufferPtr; ///< Pointer to buffer.
127} LOCATE_HEAP_PTR;
128
129/// Heap Node Header
130typedef struct _BUFFER_NODE {
131 UINT32 BufferHandle; ///< An unique ID of buffer.
132 UINT32 BufferSize; ///< Size of buffer.
133 UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
134 UINT8 PadSize; ///< Size of pad.
135 UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
136} BUFFER_NODE;
137
138/// Heap Manager
139typedef struct _HEAP_MANAGER {
140 UINT32 Signature; ///< a signature to indicate if the heap is valid.
141 UINT32 UsedSize; ///< Used size of heap.
142 UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
143 UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
144} HEAP_MANAGER;
145
146/// AGESA Buffer Handles (These are reserved)
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]147typedef enum _AGESA_BUFFER_HANDLE {
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]148 AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
149 AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
150 AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
151 AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
152 AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
153 AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
154 AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
155 AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
156 AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
157 AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
158 AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
159 AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
160 AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
161 AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
162 AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
163 AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
164 AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
165 AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
166 AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
167 AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
168 AMD_UMA_INFO_HANDLE, ///< Assign 0x000A014 buffer handle to be used for Uma information
169 AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to DMI Type16 17 19 20 information
170 HT_STATE_DATA_HANDLE, ///< Assign 0x000A016 buffer handle to HT State Data
171 PRESERVE_MAIL_BOX_HANDLE, ///< Assign 0x000A017 buffer handle for Preserve Mailbox Feature.
172 EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A018 buffer handle to Event Log
173 IDS_CONTROL_HANDLE, ///< Assign 0x000A019 buffer handle to AmdIds routine.
174 IDS_HT_DATA_HANDLE, ///< Assign 0x000A01A buffer handle to Ht IDS control
175 IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A01B buffer handle to be used for HDTOUT support.
176 IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01C buffer handle to Performance analysis
177 IDS_GRA_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GRA support
178 AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01E buffer handle to be used for PCIe support
179 AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for GNB SMU configuration
180 AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A020 buffer handle to be used for TT fuse table
181 AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A021 buffer handle to be used for Gfx platform configuration
182 AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
183 AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
184 AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
185 SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
186 NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
187 HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
188 LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258, ///< 'ambx'
189 IDS_REG_TABLE_HANDLE = 0x49524547 ///< 'IREG' Handle for IDS register table
190} AGESA_BUFFER_HANDLE;
191
192
193/*---------------------------------------------------------------------------------------
194 * F U N C T I O N P R O T O T Y P E
195 *---------------------------------------------------------------------------------------
196 */
197
198AGESA_STATUS
199HeapManagerInit (
200 IN AMD_CONFIG_PARAMS *StdHeader
201 );
202
203AGESA_STATUS
204HeapAllocateBuffer (
205 IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
206 IN OUT AMD_CONFIG_PARAMS *StdHeader
207 );
208
209AGESA_STATUS
210HeapDeallocateBuffer (
211 IN UINT32 BufferHandle,
212 IN AMD_CONFIG_PARAMS *StdHeader
213 );
214
215AGESA_STATUS
216HeapLocateBuffer (
217 IN OUT LOCATE_HEAP_PTR *LocateHeap,
218 IN AMD_CONFIG_PARAMS *StdHeader
219 );
220
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]221VOID
222*HeapGetBaseAddress (
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]223 IN AMD_CONFIG_PARAMS *StdHeader
224 );
225
226AGESA_STATUS
227EventLogInitialization (
228 IN AMD_CONFIG_PARAMS *StdHeader
229 );
230#endif // _HEAP_MANAGER_H_