Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Power Management functions. |
| 6 | * |
| 7 | * Contains code for doing early power management |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision: 36369 $ @e \$Date: 2010-08-17 22:54:34 +0800 (Tue, 17 Aug 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | #include "AGESA.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "cpuRegisters.h" |
| 55 | #include "cpuFamilyTranslation.h" |
| 56 | #include "OptionMultiSocket.h" |
| 57 | #include "cpuApicUtilities.h" |
| 58 | #include "cpuEarlyInit.h" |
| 59 | #include "cpuPowerMgmtSystemTables.h" |
| 60 | #include "cpuServices.h" |
| 61 | #include "Filecode.h" |
| 62 | CODE_GROUP (G1_PEICC) |
| 63 | RDATA_GROUP (G1_PEICC) |
| 64 | |
| 65 | #define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * D E F I N I T I O N S A N D M A C R O S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * T Y P E D E F S A N D S T R U C T U R E S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | VOID |
| 81 | STATIC |
| 82 | PerformThisPmStep ( |
| 83 | IN VOID *Step, |
| 84 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 85 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 86 | ); |
| 87 | |
| 88 | VOID |
| 89 | STATIC |
| 90 | GoToMemInitPstateCore0 ( |
| 91 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 92 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 93 | ); |
| 94 | |
| 95 | VOID |
| 96 | STATIC |
| 97 | GoToMemInitPstateCore ( |
| 98 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 99 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 100 | ); |
| 101 | |
| 102 | /*---------------------------------------------------------------------------------------- |
| 103 | * E X P O R T E D F U N C T I O N S |
| 104 | *---------------------------------------------------------------------------------------- |
| 105 | */ |
| 106 | extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; |
| 107 | |
| 108 | /*---------------------------------------------------------------------------------------*/ |
| 109 | /** |
| 110 | * Perform the "BIOS Requirements for P-State Initialization and Transitions." |
| 111 | * |
| 112 | * This is the generic arbiter code to be executed by the BSC. The system power |
| 113 | * management init tables will be traversed. This must be run by the system BSC |
| 114 | * only. |
| 115 | * |
| 116 | * @param[in] CpuEarlyParams Required input parameters for early CPU initialization |
| 117 | * @param[in] StdHeader Config handle for library and services |
| 118 | * |
| 119 | * @return Most severe AGESA_STATUS level that any system processor encountered |
| 120 | * |
| 121 | */ |
| 122 | AGESA_STATUS |
| 123 | PmInitializationAtEarly ( |
| 124 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, |
| 125 | IN AMD_CONFIG_PARAMS *StdHeader |
| 126 | ) |
| 127 | { |
| 128 | UINT8 i; |
| 129 | UINT8 NumberOfSystemWideSteps; |
| 130 | AP_TASK TaskPtr; |
| 131 | AGESA_STATUS ReturnCode; |
| 132 | WARM_RESET_REQUEST Request; |
| 133 | |
| 134 | // Determine the number of steps to perform |
| 135 | OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader); |
| 136 | |
| 137 | // Traverse the PM init table |
| 138 | TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep; |
| 139 | TaskPtr.DataTransfer.DataSizeInDwords = 1; |
| 140 | TaskPtr.DataTransfer.DataPtr = &i; |
| 141 | TaskPtr.DataTransfer.DataTransferFlags = 0; |
| 142 | TaskPtr.ExeFlags = PASS_EARLY_PARAMS; |
| 143 | for (i = 0; i < NumberOfSystemWideSteps; ++i) { |
| 144 | IDS_HDT_CONSOLE (CPU_TRACE, " Perform PM init step %d\n", i); |
| 145 | OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); |
| 146 | } |
| 147 | |
| 148 | // GoToMemInitPstateCore0 only if there is no pending warm reset. |
| 149 | GetWarmResetFlag (StdHeader, &Request); |
| 150 | if (Request.RequestBit == FALSE) { |
| 151 | TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0; |
| 152 | TaskPtr.DataTransfer.DataSizeInDwords = 0; |
| 153 | TaskPtr.ExeFlags = PASS_EARLY_PARAMS; |
| 154 | IDS_HDT_CONSOLE (CPU_TRACE, " Transition all cores to POST P-state\n"); |
| 155 | OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); |
| 156 | } |
| 157 | |
| 158 | // Retrieve/Process any errors |
| 159 | ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader); |
| 160 | |
| 161 | return (ReturnCode); |
| 162 | } |
| 163 | |
| 164 | |
| 165 | /*---------------------------------------------------------------------------------------*/ |
| 166 | /** |
| 167 | * Performs the next step in the executing core 0's family specific power |
| 168 | * management table. |
| 169 | * |
| 170 | * This function determines if the input step is valid, and invokes the power |
| 171 | * management step if appropriate. This must be run by processor core 0s only. |
| 172 | * |
| 173 | * @param[in] Step Zero based step number |
| 174 | * @param[in] StdHeader Config handle for library and services |
| 175 | * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization |
| 176 | * |
| 177 | */ |
| 178 | VOID |
| 179 | STATIC |
| 180 | PerformThisPmStep ( |
| 181 | IN VOID *Step, |
| 182 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 183 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 184 | ) |
| 185 | { |
| 186 | UINT8 MyNumberOfSteps; |
| 187 | SYS_PM_TBL_STEP *FamilyTablePtr; |
| 188 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 189 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 190 | GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
| 191 | FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&FamilyTablePtr, &MyNumberOfSteps, StdHeader); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 192 | |
| 193 | if (*(UINT8 *)Step < MyNumberOfSteps) { |
| 194 | if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) { |
| 195 | if (!(BOOLEAN) (FamilyTablePtr[*(UINT8 *)Step].ExeFlags & PM_EXEFLAGS_WARM_ONLY) || |
| 196 | IsWarmReset (StdHeader)) { |
| 197 | FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader); |
| 198 | } |
| 199 | } |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | |
| 204 | /*---------------------------------------------------------------------------------------*/ |
| 205 | /** |
| 206 | * Transitions the executing processor to the desired P-state. |
| 207 | * |
| 208 | * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is |
| 209 | * run by all processor core 0s. |
| 210 | * |
| 211 | * @param[in] StdHeader Config handle for library and services |
| 212 | * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization |
| 213 | * |
| 214 | */ |
| 215 | VOID |
| 216 | STATIC |
| 217 | GoToMemInitPstateCore0 ( |
| 218 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 219 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 220 | ) |
| 221 | { |
| 222 | AP_TASK TaskPtr; |
| 223 | |
| 224 | TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore; |
| 225 | TaskPtr.DataTransfer.DataSizeInDwords = 0; |
| 226 | TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS; |
| 227 | ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); |
| 228 | } |
| 229 | |
| 230 | |
| 231 | /*---------------------------------------------------------------------------------------*/ |
| 232 | /** |
| 233 | * Transitions the executing core to the desired P-state. |
| 234 | * |
| 235 | * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is |
| 236 | * run by all system cores. |
| 237 | * |
| 238 | * @param[in] StdHeader Config handle for library and services |
| 239 | * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization |
| 240 | * |
| 241 | */ |
| 242 | VOID |
| 243 | STATIC |
| 244 | GoToMemInitPstateCore ( |
| 245 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 246 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 247 | ) |
| 248 | { |
| 249 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 250 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 251 | GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 252 | FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader); |
| 253 | } |