Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Register Table Related Functions |
| 6 | * |
| 7 | * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision: 36421 $ @e \$Date: 2010-08-18 22:46:48 +0800 (Wed, 18 Aug 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _CPU_FAM_REGISTERS_H_ |
| 48 | #define _CPU_FAM_REGISTERS_H_ |
| 49 | |
| 50 | /* |
| 51 | *-------------------------------------------------------------- |
| 52 | * |
| 53 | * M O D U L E S U S E D |
| 54 | * |
| 55 | *--------------------------------------------------------------- |
| 56 | */ |
| 57 | |
| 58 | /* |
| 59 | *-------------------------------------------------------------- |
| 60 | * |
| 61 | * D E F I N I T I O N S / M A C R O S |
| 62 | * |
| 63 | *--------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | // This define should be equal to the total number of families |
| 67 | // in the cpuFamily enum. |
| 68 | #define MAX_CPU_FAMILIES 64 |
| 69 | #define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family |
| 70 | |
| 71 | // CPU_LOGICAL_ID.Family equates |
| 72 | // Family 10h equates |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 73 | #define AMD_FAMILY_10_RB 0x0000000000000001ull |
| 74 | #define AMD_FAMILY_10_BL 0x0000000000000002ull |
| 75 | #define AMD_FAMILY_10_DA 0x0000000000000004ull |
| 76 | #define AMD_FAMILY_10_HY 0x0000000000000008ull |
| 77 | #define AMD_FAMILY_10_PH 0x0000000000000010ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 78 | #define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY |
| 79 | |
| 80 | #define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) |
| 81 | #define AMD_FAMILY_GH (AMD_FAMILY_10) |
| 82 | |
| 83 | // Family 12h equates |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 84 | #define AMD_FAMILY_12_LN 0x0000000000000020ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 85 | #define AMD_FAMILY_12 (AMD_FAMILY_12_LN) |
| 86 | #define AMD_FAMILY_LN (AMD_FAMILY_12_LN) |
| 87 | |
| 88 | // Family 14h equates |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 89 | #define AMD_FAMILY_14_ON 0x0000000000000040ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 90 | #define AMD_FAMILY_14 (AMD_FAMILY_14_ON) |
| 91 | #define AMD_FAMILY_ON (AMD_FAMILY_14_ON) |
| 92 | |
| 93 | // Family 15h equates |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 94 | #define AMD_FAMILY_15_OR 0x0000000000000100ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 95 | #define AMD_FAMILY_15 (AMD_FAMILY_15_OR) |
| 96 | #define AMD_FAMILY_OR (AMD_FAMILY_15_OR) |
| 97 | |
| 98 | // Family 16h equates |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 99 | #define AMD_FAMILY_16 0x0000000000000800ull |
| 100 | #define AMD_FAMILY_WF (AMD_FAMILY_16) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 101 | |
| 102 | // Family Unknown |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 103 | #define AMD_FAMILY_UNKNOWN 0x8000000000000000ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 104 | |
| 105 | // Family Group equates |
| 106 | #define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16) |
| 107 | |
| 108 | // Family 10h CPU_LOGICAL_ID.Revision equates |
| 109 | // ------------------------------------- |
| 110 | // Family 10h RB steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 111 | #define AMD_F10_RB_C0 0x0000000000000001ull |
| 112 | #define AMD_F10_RB_C1 0x0000000000000002ull |
| 113 | #define AMD_F10_RB_C2 0x0000000000000004ull |
| 114 | #define AMD_F10_RB_C3 0x0000000000000008ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 115 | // Family 10h BL steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 116 | #define AMD_F10_BL_C2 0x0000000000000010ull |
| 117 | #define AMD_F10_BL_C3 0x0000000000000020ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 118 | // Family 10h DA steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 119 | #define AMD_F10_DA_C2 0x0000000000000040ull |
| 120 | #define AMD_F10_DA_C3 0x0000000000000080ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 121 | // Family 10h HY SCM steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 122 | #define AMD_F10_HY_SCM_D0 0x0000000000000100ull |
| 123 | #define AMD_F10_HY_SCM_D1 0x0000000000000400ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 124 | // Family 10h HY MCM steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 125 | #define AMD_F10_HY_MCM_D0 0x0000000000000200ull |
| 126 | #define AMD_F10_HY_MCM_D1 0x0000000000000800ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 127 | // Family 10h PH steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 128 | #define AMD_F10_PH_E0 0x0000000000001000ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 129 | |
| 130 | // Family 10h Unknown stepping |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 131 | #define AMD_F10_UNKNOWN 0x8000000000000000ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 132 | |
| 133 | // Family 10h Miscellaneous equates |
| 134 | #define AMD_F10_C0 (AMD_F10_RB_C0) |
| 135 | #define AMD_F10_C1 (AMD_F10_RB_C1) |
| 136 | #define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2) |
| 137 | #define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3) |
| 138 | #define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3) |
| 139 | |
| 140 | #define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3) |
| 141 | |
| 142 | #define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3) |
| 143 | #define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3) |
| 144 | |
| 145 | #define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3) |
| 146 | #define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3) |
| 147 | |
| 148 | #define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0) |
| 149 | #define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1) |
| 150 | #define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1) |
| 151 | |
| 152 | #define AMD_F10_PH_ALL (AMD_F10_PH_E0) |
| 153 | #define AMD_F10_Ex (AMD_F10_PH_E0) |
| 154 | |
| 155 | #define AMD_F10_HY_ALL (AMD_F10_Dx) |
| 156 | #define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1) |
| 157 | |
| 158 | #define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 159 | #define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 160 | #define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 161 | #define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 162 | #define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex) |
| 163 | #define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex) |
| 164 | |
| 165 | #define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex | AMD_F10_UNKNOWN) |
| 166 | |
| 167 | // Family 12h CPU_LOGICAL_ID.Revision equates |
| 168 | // ------------------------------------- |
| 169 | |
| 170 | // Family 12h LN steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 171 | #define AMD_F12_LN_A0 0x0000000000000001ull |
| 172 | #define AMD_F12_LN_A1 0x0000000000000002ull |
| 173 | #define AMD_F12_LN_B0 0x0000000000000004ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 174 | // Family 12h Unknown stepping |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 175 | #define AMD_F12_UNKNOWN 0x8000000000000000ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 176 | |
| 177 | #define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) |
| 178 | #define AMD_F12_LN_Bx (AMD_F12_LN_B0) |
| 179 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 180 | #define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 181 | |
| 182 | // Family 14h CPU_LOGICAL_ID.Revision equates |
| 183 | // ------------------------------------- |
| 184 | |
| 185 | // Family 14h ON steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 186 | #define AMD_F14_ON_A0 0x0000000000000001ull |
| 187 | #define AMD_F14_ON_A1 0x0000000000000002ull |
| 188 | #define AMD_F14_ON_B0 0x0000000000000004ull |
| 189 | #define AMD_F14_ON_C0 0x0000000000000008ull |
| 190 | // Family 14h KR steppings |
| 191 | #define AMD_F14_KR_A0 0x0000000000000100ull |
| 192 | #define AMD_F14_KR_A1 0x0000000000000200ull |
| 193 | #define AMD_F14_KR_B0 0x0000000000000400ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 194 | // Family 14h Unknown stepping |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 195 | #define AMD_F14_UNKNOWN 0x8000000000000000ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 196 | |
| 197 | #define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) |
| 198 | #define AMD_F14_ON_Bx (AMD_F14_ON_B0) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 199 | #define AMD_F14_ON_Cx (AMD_F14_ON_C0) |
| 200 | #define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 201 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 202 | #define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 203 | |
| 204 | // Family 15h CPU_LOGICAL_ID.Revision equates |
| 205 | // ------------------------------------- |
| 206 | |
| 207 | // Family 15h OROCHI steppings |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 208 | #define AMD_F15_OR_A0 0x0000000000000001ull |
| 209 | #define AMD_F15_OR_A1 0x0000000000000002ull |
| 210 | #define AMD_F15_OR_B0 0x0000000000000004ull |
| 211 | // Family 15h TN steppings |
| 212 | #define AMD_F15_TN_A0 0x0000000000000100ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 213 | // Family 15h Unknown stepping |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 214 | #define AMD_F15_UNKNOWN 0x8000000000000000ull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 215 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 216 | #define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) |
| 217 | #define AMD_F15_OR_Bx AMD_F15_OR_B0 |
| 218 | #define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) |
| 219 | #define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) |
| 220 | #define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 221 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 222 | #define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 223 | |
| 224 | // Family 16h CPU_LOGICAL_ID.Revision equates |
| 225 | // TBD |
| 226 | |
| 227 | #endif // _CPU_FAM_REGISTERS_H_ |
| 228 | |