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review.coreboot.org / coreboot / dbdf170dcdf9edbc860766606e53c6d647d89d38 / . / src / vendorcode / amd / agesa / f14 / Proc / CPU / Family / 0x14 / cpuF14PowerMgmt.h
blob: e912a2a60e2945ffa75235f6b887d74d949fa489 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD Family_14 Power Management related stuff
6 *
7 * @xrefitem bom "File Content Label" "Release Content"
8 * @e project: AGESA
9 * @e sub-project: CPU/F14
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]10 * @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]11 *
12 */
13/*
14 *****************************************************************************
15 *
16 * Copyright (c) 2011, Advanced Micro Devices, Inc.
17 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]18 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]28 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]29 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]40 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]41 * ***************************************************************************
42 *
43 */
44
45#ifndef _CPUF14POWERMGMT_H_
46#define _CPUF14POWERMGMT_H_
47
48/*
49 * Family 14h CPU Power Management MSR definitions
50 *
51 */
52
53/* P-state Current Limit Register 0xC0010061 */
54#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
55
56/// Pstate Current Limit MSR Register
57typedef struct {
58 UINT64 CurPstateLimit:3; ///< Current Pstate Limit
59 UINT64 :1; ///< Reserved
60 UINT64 PstateMaxVal:3; ///< Pstate Max Value
61 UINT64 :57; ///< Reserved
62} PSTATE_CURLIM_MSR;
63
64
65/* P-state Control Register 0xC0010062 */
66#define MSR_PSTATE_CTL 0xC0010062
67
68/// Pstate Control MSR Register
69typedef struct {
70 UINT64 PstateCmd:3; ///< Pstate change command
71 UINT64 :61; ///< Reserved
72} PSTATE_CTRL_MSR;
73
74
75/* P-state Status Register 0xC0010063 */
76#define MSR_PSTATE_STS 0xC0010063
77
78/// Pstate Status MSR Register
79typedef struct {
80 UINT64 CurPstate:3; ///< Current Pstate
81 UINT64 :61; ///< Reserved
82} PSTATE_STS_MSR;
83
84
85/* P-state Registers 0xC001006[B:4] */
86#define MSR_PSTATE_0 0xC0010064
87#define MSR_PSTATE_1 0xC0010065
88#define MSR_PSTATE_2 0xC0010066
89#define MSR_PSTATE_3 0xC0010067
90#define MSR_PSTATE_4 0xC0010068
91#define MSR_PSTATE_5 0xC0010069
92#define MSR_PSTATE_6 0xC001006A
93#define MSR_PSTATE_7 0xC001006B
94
95#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
96#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */
97#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */
98#define NM_PS_REG 8 /* number of P-state MSR registers */
99
100/// Pstate MSR
101typedef struct {
102 UINT64 CpuDidLSD:4; ///< CPU core divisor identifier least significant digit
103 UINT64 CpuDidMSD:5; ///< CPU core divisor identifier most significant digit
104 UINT64 CpuVid:7; ///< CPU core VID
105 UINT64 :16; ///< Reserved
106 UINT64 IddValue:8; ///< Current value field
107 UINT64 IddDiv:2; ///< Current divisor field
108 UINT64 :21; ///< Reserved
109 UINT64 PsEnable:1; ///< P-state Enable
110} PSTATE_MSR;
111
112
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]113/* COFVID Control Register 0xC0010070 */
114#define MSR_COFVID_CTL 0xC0010070
115
116/// COFVID Control MSR Register
117typedef struct {
118 UINT64 CpuDid:4; ///< CPU core divisor identifier
119 UINT64 CpuDidMSD:5; ///< CPU core frequency identifier
120 UINT64 CpuVid:7; ///< CPU core VID
121 UINT64 PstateId:3; ///< P-state identifier
122 UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID
123 UINT64 :44; ///< Reserved
124} COFVID_CTRL_MSR;
125
126
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]127/* COFVID Status Register 0xC0010071 */
128#define MSR_COFVID_STS 0xC0010071
129
130/// COFVID Status MSR Register
131typedef struct {
132 UINT64 CurCpuDid:4; ///< Current CPU core divisor ID
133 UINT64 CurCpuDidMSD:5; ///< Current CPU core frequency ID
134 UINT64 CurCpuVid:7; ///< Current CPU core VID
135 UINT64 CurPstate:3; ///< Current P-state
136 UINT64 :1; ///< Reserved
137 UINT64 PstateInProgress:1; ///< P-state change in progress
138 UINT64 :4; ///< Reserved
139 UINT64 CurNbVid:7; ///< Current northbridge VID
140 UINT64 StartupPstate:3; ///< Startup P-state number
141 UINT64 MaxVid:7; ///< Maximum voltage
142 UINT64 MinVid:7; ///< Minimum voltage
143 UINT64 MainPllOpFreqIdMax:6; ///< Main PLL operating frequency ID maximum
144 UINT64 :1; ///< Reserved
145 UINT64 CurPstateLimit:3; ///< Current P-state Limit
146 UINT64 :5; ///< Reserved
147} COFVID_STS_MSR;
148
149
150/* C-state Address Register 0xC0010073 */
151#define MSR_CSTATE_ADDRESS 0xC0010073
152
153/// C-state Address MSR Register
154typedef struct {
155 UINT64 CstateAddr:16; ///< C-state address
156 UINT64 :48; ///< Reserved
157} CSTATE_ADDRESS_MSR;
158
159
160/* CPU Watchdog Timer Register 0xC0010074 */
161#define MSR_CPU_WDT 0xC0010074
162
163/// CPU Watchdog Timer Register
164typedef struct {
165 UINT64 CpuWdtEn:1; ///< CPU watchdog timer enable
166 UINT64 CpuWdtTimeBase:2; ///< CPU watchdog timer time base
167 UINT64 CpuWdtCountSel:4; ///< CPU watchdog timer count select
168 UINT64 :57; ///< Reserved
169} CPU_WDT_MSR;
170
171
172/*
173 * Family 14h CPU Power Management PCI definitions
174 *
175 */
176
177/* Memory controller configuration low register D18F2x118 */
178#define MEM_CFG_LOW_REG 0x118
179#define MEM_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, MEM_CFG_LOW_REG))
180
181/// Memory Controller Configuration Low
182typedef struct {
183 UINT32 MctPriCpuRd:2; ///< CPU read priority
184 UINT32 MctPriCpuWr:2; ///< CPU write priority
185 UINT32 MctPriHiRd:2; ///< High-priority VC set read priority
186 UINT32 MctPriHiWr:2; ///< High-priority VC set write priority
187 UINT32 MctPriDefault:2; ///< Default non-write priority
188 UINT32 MctPriWr:2; ///< Default write priority
189 UINT32 :7; ///< Reserved
190 UINT32 C6DramLock:1; ///< C6 DRAM lock
191 UINT32 :8; ///< Reserved
192 UINT32 MctVarPriCntLmt:4; ///< Variable priority time limit
193} MEM_CFG_LOW_REGISTER;
194
195
196/* Hardware thermal control register D18F3x64 */
197#define HTC_REG 0x64
198#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
199
200/// Hardware Thermal Control PCI Register
201typedef struct {
202 UINT32 HtcEn:1; ///< HTC Enable
203 UINT32 :3; ///< Reserved
204 UINT32 HtcAct:1; ///< HTC Active State
205 UINT32 HtcActSts:1; ///< HTC Active Status
206 UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
207 UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
208 UINT32 :8; ///< Reserved
209 UINT32 HtcTmpLmt:7; ///< HTC temperature limit
210 UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
211 UINT32 HtcHystLmt:4; ///< HTC hysteresis
212 UINT32 HtcPstateLimit:3; ///< HTC P-state limit select
213 UINT32 HtcLock:1; ///< HTC lock
214} HTC_REGISTER;
215
216
217/* Power Control Miscellaneous Register D18F3xA0 */
218#define PW_CTL_MISC_REG 0xA0
219#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
220
221/// Power Control Miscellaneous PCI Register
222typedef struct {
223 UINT32 PsiVid:7; ///< PSI_L VID threshold
224 UINT32 PsiVidEn:1; ///< PSI_L VID enable
225 UINT32 :1; ///< Reserved
226 UINT32 SviHighFreqSel:1; ///< SVI high frequency select
227 UINT32 :6; ///< Reserved
228 UINT32 ConfigId:12; ///< Configuration Identifier
229 UINT32 :3; ///< Reserved
230 UINT32 CofVidProg:1; ///< COF and VID of P-states programmed
231} POWER_CTRL_MISC_REGISTER;
232
233
234/* Clock Power/Timing Control 0 Register D18F3xD4 */
235#define CPTC0_REG 0xD4
236#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
237
238/// Clock Power Timing Control PCI Register
239typedef struct {
240 UINT32 MainPllOpFreqId:6; ///< Main PLL Fid
241 UINT32 MainPllOpFreqIdEn:1; ///< Main PLL Fid Enable
242 UINT32 :1; ///< Reserved
243 UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
244 UINT32 OnionOutHyst:4; ///< ONION outbound hysteresis
245 UINT32 DisNclkGatingIdle:1; ///< Disable NCLK gating when idle
246 UINT32 ClkGatingEnDram:1; ///< Clock gating enable DRAM
247 UINT32 :1; ///< Reserved
248 UINT32 PstateSpecFuseSel:8; ///< P-State Specification Fuse Select
249 UINT32 :5; ///< Reserved
250} CLK_PWR_TIMING_CTRL_REGISTER;
251
252
253/* Clock Power/Timing Control 1 Register D18F3xD8 */
254#define CPTC1_REG 0xD8
255#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
256
257/// Clock Power Timing Control 1 PCI Register
258typedef struct {
259 UINT32 :4; ///< Reserved
260 UINT32 VSRampSlamTime:3; ///< Voltage stabilization slam time
261 UINT32 :22; ///< Reserved
262 UINT32 SlamModeSelect:1; ///< Voltage slam mode select
263 UINT32 :2; ///< Reserved
264} CLK_PWR_TIMING_CTRL1_REGISTER;
265
266
267/* Clock Power/Timing Control 2 Register D18F3xDC */
268#define CPTC2_REG 0xDC
269#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
270
271/// Clock Power Timing Control 2 PCI Register
272typedef struct {
273 UINT32 :8; ///< Reserved
274 UINT32 PstateMaxVal:3; ///< P-state maximum value
275 UINT32 :1; ///< Reserved
276 UINT32 NbPs0Vid:7; ///< NB VID
277 UINT32 NclkFreqDone:1; ///< NCLK frequency change done
278 UINT32 NbPs0NclkDiv:7; ///< NCLK divisor
279 UINT32 NbClockGateHyst:3; ///< Northbridge clock gating hysteresis
280 UINT32 NbClockGateEn:1; ///< Northbridge clock gating enable
281 UINT32 CnbCifClockGateEn:1; ///< CNB CIF clock gating enable
282} CLK_PWR_TIMING_CTRL2_REGISTER;
283
284
285/* Northbridge Capabilities Register D18F3xE8 */
286#define NB_CAPS_REG 0xE8
287#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
288
289/// Northbridge Capabilities PCI Register
290typedef struct {
291 UINT32 DctDualCap:1; ///< Two-channel DRAM capable
292 UINT32 :4; ///< Reserved
293 UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate
294 UINT32 MctCap:1; ///< Memory controller capable
295 UINT32 SvmCapable:1; ///< SVM capable
296 UINT32 HtcCapable:1; ///< HTC capable
297 UINT32 :1; ///< Reserved
298 UINT32 CmpCap:2; ///< CMP capable
299 UINT32 :14; ///< Reserved
300 UINT32 LHtcCapable:1; ///< LHTC capable
301 UINT32 :3; ///< Reserved
302} NB_CAPS_REGISTER;
303
304
305/* Clock Power/Timing Control 3 Register D18F3x128 */
306#define CPTC3_REG 0x128
307#define CPTC3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC3_REG))
308
309/// Clock Power Timing Control 3 PCI Register
310typedef struct {
311 UINT32 C6Vid:7; ///< C6 VID
312 UINT32 :1; ///< Reserved
313 UINT32 NbPsiVid:7; ///< NB PSI_L VID threshold
314 UINT32 NbPsiVidEn:1; ///< NB PSI_L enable
315 UINT32 :16; ///< Reserved
316} CLK_PWR_TIMING_CTRL3_REGISTER;
317
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]318/* Local hardware thermal control register D18F3x138 */
319#define LHTC_REG 0x138
320#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG))
321
322/// Local Hardware Thermal Control PCI Register
323typedef struct {
324 UINT32 LHtcEn:1; ///< Local HTC Enable
325 UINT32 :7; ///< Reserved
326 UINT32 LHtcAct:2; ///< Local HTC Active State
327 UINT32 :2; ///< Reserved
328 UINT32 LHtcActSts:2; ///< Local HTC Active Status
329 UINT32 :2; ///< Reserved
330 UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit
331 UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select
332 UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis
333 UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select
334 UINT32 LHtcLock:1; ///< HTC lock
335} LHTC_REGISTER;
336
337/* Product Information Register D18F3x1FC */
338#define PRODUCT_INFO_REG 0x1FC
339#define PRODUCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRODUCT_INFO_REG))
340
341/// Product Information PCI Register
342typedef struct {
343 UINT32 :2; ///< Reserved
344 UINT32 LowPowerDefault:1; ///< Low Power Default
345 UINT32 :29; ///< Reserved
346} PRODUCT_INFO_REGISTER;
347
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]348
349/* C-state Control 1 Register D18F4x118 */
350#define CSTATE_CTRL1_REG 0x118
351#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
352
353/// C-state Control 1 Register
354typedef struct {
355 UINT32 CstAct0:3; ///< C-state action field 0
356 UINT32 :5; ///< Reserved
357 UINT32 CstAct1:3; ///< C-state action field 1
358 UINT32 :5; ///< Reserved
359 UINT32 CstAct2:3; ///< C-state action field 2
360 UINT32 :5; ///< Reserved
361 UINT32 CstAct3:3; ///< C-state action field 3
362 UINT32 :5; ///< Reserved
363} CSTATE_CTRL1_REGISTER;
364
365
366/* C-state Control 2 Register D18F4x11C */
367#define CSTATE_CTRL2_REG 0x11C
368#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
369
370/// C-state Control 2 Register
371typedef struct {
372 UINT32 CstAct4:3; ///< C-state action field 4
373 UINT32 :5; ///< Reserved
374 UINT32 CstAct5:3; ///< C-state action field 5
375 UINT32 :5; ///< Reserved
376 UINT32 CstAct6:3; ///< C-state action field 6
377 UINT32 :5; ///< Reserved
378 UINT32 CstAct7:3; ///< C-state action field 7
379 UINT32 :5; ///< Reserved
380} CSTATE_CTRL2_REGISTER;
381
382
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]383/* C-state Monitor Control 3 Register D18F4x134 */
384#define CSTATE_MON_CTRL3_REG 0x134
385#define CSTATE_MON_CTRL3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_MON_CTRL3_REG))
386
387/// C-state Monitor Control 3 Register
388typedef struct {
389 UINT32 IntRatePkgC6MaxDepth:4; ///< Interrupt rate monitor PC6 maximum counter depth
390 UINT32 IntRatePkgC6Threshold:4; ///< Interrupt rate monitor PC6 threshold
391 UINT32 IntRatePkgC6BurstLen:3; ///< Interrupt rate monitor PC6 burst length
392 UINT32 IntRatePkgC6DecrRate:5; ///< Interrupt rate monitor PC6 decrement rate
393 UINT32 IntRateCC6MaxDepth:4; ///< Interrupt rate monitor CC6 maximum counter depth
394 UINT32 IntRateCC6Threshold:4; ///< Interrupt rate monitor CC6 threshold
395 UINT32 IntRateCC6BurstLen:3; ///< Interrupt rate monitor CC6 burst length
396 UINT32 IntRateCC6DecrRate:5; ///< Interrupt rate monitor CC6 decrement rate
397} CSTATE_MON_CTRL3_REGISTER;
398
399/* LPMV Scalar 2 Register D18F4x14C */
400#define LPMV_SCALAR2_REG 0x14C
401#define LPMV_SCALAR2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, LPMV_SCALAR2_REG))
402
403/// LPMV Scalar 2 Register
404typedef struct {
405 UINT32 :24; ///< Reserved
406 UINT32 ApmCstExtPol:2; ///< Number of boosted states
407 UINT32 :6; ///< Reserved
408} LPMV_SCALAR2_REGISTER;
409
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]410/* Core Performance Boost Control Register D18F4x15C */
411#define CPB_CTRL_REG 0x15C
412#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
413
414/// Core Performance Boost Control Register
415typedef struct {
416 UINT32 BoostSrc:2; ///< Boost source
417 UINT32 NumBoostStates:3; ///< Number of boosted states
418 UINT32 :24; ///< Reserved
419 UINT32 BoostEnAllCores:1; ///< Boost enable all cores
420 UINT32 :2; ///< Reserved
421} CPB_CTRL_REGISTER;
422
423
424/* CPU State Power Management Dynamic Control 0 Register D18F4x1A8 */
425#define CPU_STATE_PM_CTRL0_REG 0x1A8
426#define CPU_STATE_PM_CTRL0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL0_REG))
427
428/// CPU State Power Management Dynamic Control 0 Register
429typedef struct {
430 UINT32 SingleHaltCpuDid:5; ///< Single hlt CPU DID
431 UINT32 AllHaltCpuDid:5; ///< All hlt CPU DID
432 UINT32 :5; ///< Reserved
433 UINT32 CpuProbEn:1; ///< CPU probe enable
434 UINT32 :1; ///< Reserved
435 UINT32 PService:3; ///< Service P-state
436 UINT32 PServiceTmr:3; ///< Service P-state timer
437 UINT32 PServiceTmrEn:1; ///< Service P-state timer enable
438 UINT32 DramSrEn:1; ///< DRAM self-refresh enable
439 UINT32 MemTriStateEn:1; ///< Memory clock tri-state enable
440 UINT32 DramSrHyst:3; ///< DRAM self-refresh hysteresis time
441 UINT32 DramSrHystEnable:1; ///< DRAM self-refresh hysteresis enable
442 UINT32 :2; ///< Reserved
443} CPU_STATE_PM_CTRL0_REGISTER;
444
445
446/* CPU State Power Management Dynamic Control 1 Register D18F4x1AC */
447#define CPU_STATE_PM_CTRL1_REG 0x1AC
448#define CPU_STATE_PM_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL1_REG))
449
450/// CPU State Power Management Dynamic Control 1 Register
451typedef struct {
452 UINT32 :5; ///< Reserved
453 UINT32 C6Did:5; ///< CC6 divisor
454 UINT32 :6; ///< Reserved
455 UINT32 PstateIdCoreOffExit:3; ///< P-state ID core-off exit
456 UINT32 :7; ///< Reserved
457 UINT32 PkgC6Cap:1; ///< Package C6 capable
458 UINT32 CoreC6Cap:1; ///< Core C6 capable
459 UINT32 PkgC6Dis:1; ///< Package C6 disable
460 UINT32 CoreC6Dis:1; ///< Core C6 disable
461 UINT32 CstPminEn:1; ///< C-state Pmin enable
462 UINT32 :1; ///< Reserved
463} CPU_STATE_PM_CTRL1_REGISTER;
464
465
466/* C6 Base Register D18F4x12C */
467#define C6_BASE_REG 0x12C
468#define C6_BASE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, C6_BASE_REG))
469
470/// C6 Base Register
471typedef struct {
472 UINT32 C6Base:12; ///< C6 base[35:24]
473 UINT32 :20; ///< Reserved
474} C6_BASE_REGISTER;
475
476
477/* NB P-state Config Low Register D18F6x90 */
478#define NB_PSTATE_CFG_LOW_REG 0x90
479#define NB_PSTATE_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_LOW_REG))
480
481/// NB P-state Config Low Register
482typedef struct {
483 UINT32 NbPs1NclkDiv:7; ///< NBP1 NCLK divisor
484 UINT32 :1; ///< Reserved
485 UINT32 NbPs1Vid:7; ///< NBP1 NCLK VID
486 UINT32 :1; ///< Reserved
487 UINT32 NbPs1GnbSlowIgn:1; ///< NB P-state ignore GNB slow signal
488 UINT32 :3; ///< Reserved
489 UINT32 NbPsLock:1; ///< NB P-state lock
490 UINT32 :7; ///< Reserved
491 UINT32 NbPsForceReq:1; ///< NB P-state force request
492 UINT32 NbPsForceSel:1; ///< NB P-state force selection
493 UINT32 NbPsCtrlDis:1; ///< NB P-state control disable
494 UINT32 NbPsCap:1; ///< NB P-state capable
495} NB_PSTATE_CFG_LOW_REGISTER;
496
497
498/* NB P-state Config High Register D18F6x94 */
499#define NB_PSTATE_CFG_HIGH_REG 0x94
500#define NB_PSTATE_CFG_HIGH_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_HIGH_REG))
501
502/// NB P-state Config High Register
503typedef struct {
504 UINT32 CpuPstateThr:3; ///< CPU P-state threshold
505 UINT32 CpuPstateThrEn:1; ///< CPU P-state threshold enable
506 UINT32 NbPs1NoTransOnDma:1; ///< NB P-state no transitions on DMA
507 UINT32 :15; ///< Reserved
508 UINT32 NbPsNonC0Timer:3; ///< NB P-state non-C0 timer
509 UINT32 NbPsC0Timer:3; ///< NB P-state C0 timer
510 UINT32 NbPs1ResTmrMin:3; ///< NBP1 minimum residency timer
511 UINT32 NbPs0ResTmrMin:3; ///< NBP0 minimum residency timer
512} NB_PSTATE_CFG_HIGH_REGISTER;
513
514
515/* NB P-state Control and Status Register D18F6x98 */
516#define NB_PSTATE_CTRL_STS_REG 0x98
517#define NB_PSTATE_CTRL_STS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CTRL_STS_REG))
518
519/// NB P-state Control and Status Register
520typedef struct {
521 UINT32 NbPsTransInFlight:1; ///< NB P-state transition in flight
522 UINT32 NbPs1ActSts:1; ///< NB P-state 1 active status
523 UINT32 NbPs1Act:1; ///< NB P-state 1 active
524 UINT32 :27; ///< Reserved
525 UINT32 NbPsCsrAccSel:1; ///< NB P-state register accessibility select
526 UINT32 NbPsDbgEn:1; ///< NB P-state debug enable
527} NB_PSTATE_CTRL_STS_REGISTER;
528
529/* NCLK Reduction Control D18F6x9C */
530#define NCLK_REDUCTION_CTRL_REG 0x9C
531#define NCLK_REDUCTION_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NCLK_REDUCTION_CTRL_REG))
532
533/// NCLK Reduction Control
534typedef struct {
535 UINT32 NclkRedDiv:7; ///< NCLK reduction divisor
536 UINT32 NclkRedSelfRefrAlways:1; ///< NCLK reduction always self refresh
537 UINT32 NclkRampWithDllRelock:1; ///< NCLK ramp mode
538 UINT32 :23; ///< Reserved
539} NCLK_REDUCTION_CTRL_REGISTER;
540
541/// enum for DSM workaround control
542typedef enum {
543 CC6_DSM_WORK_AROUND_DISABLE = 0, ///< work around disable
544 CC6_DSM_WORK_AROUND_NORMAL_TRAFFIC, ///< work around With Normal Traffic
545 CC6_DSM_WORK_AROUND_HIGH_PRIORITY_CHANNEL, ///< work around With High Priority Channel
546} CC6_DSM_WORK_AROUND;
547
548#endif /* _CPUF14POWERMGMT_H */