Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Family_14 MSR tables with values as defined in BKDG |
| 6 | * |
| 7 | * @xrefitem bom "File Content Label" "Release Content" |
| 8 | * @e project: AGESA |
| 9 | * @e sub-project: CPU |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 10 | * @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 11 | * |
| 12 | */ |
| 13 | /* |
| 14 | ***************************************************************************** |
| 15 | * |
| 16 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 17 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 18 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 19 | * Redistribution and use in source and binary forms, with or without |
| 20 | * modification, are permitted provided that the following conditions are met: |
| 21 | * * Redistributions of source code must retain the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer. |
| 23 | * * Redistributions in binary form must reproduce the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer in the |
| 25 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 26 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 27 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 28 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 29 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 32 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 33 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 34 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 35 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 39 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 40 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "cpuRegisters.h" |
| 51 | #include "Table.h" |
| 52 | #include "Filecode.h" |
| 53 | #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE |
| 54 | |
| 55 | /*---------------------------------------------------------------------------------------- |
| 56 | * D E F I N I T I O N S A N D M A C R O S |
| 57 | *---------------------------------------------------------------------------------------- |
| 58 | */ |
| 59 | |
| 60 | /*---------------------------------------------------------------------------------------- |
| 61 | * T Y P E D E F S A N D S T R U C T U R E S |
| 62 | *---------------------------------------------------------------------------------------- |
| 63 | */ |
| 64 | |
| 65 | /*---------------------------------------------------------------------------------------- |
| 66 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 67 | *---------------------------------------------------------------------------------------- |
| 68 | */ |
| 69 | |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * E X P O R T E D F U N C T I O N S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = |
| 75 | { |
| 76 | |
| 77 | // M S R T a b l e s |
| 78 | // ---------------------- |
| 79 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 80 | // MC0_CTL_MASK (0xC0010044) |
| 81 | // bit[6] = 1, erratum #628 |
| 82 | { |
| 83 | MsrRegister, |
| 84 | { |
| 85 | AMD_FAMILY_14, // CpuFamily |
| 86 | AMD_F14_ON_ALL // CpuRevision |
| 87 | }, |
| 88 | {AMD_PF_ALL}, // platformFeatures |
| 89 | {{ |
| 90 | MSR_MC0_CTL_MASK, // MSR Address |
| 91 | 0x0000000000000040, // OR Mask |
| 92 | 0x0000000000000040, // NAND Mask |
| 93 | }} |
| 94 | }, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 95 | // MSR_TOM2 (0xC001001D) |
| 96 | // bits[63:0] - TOP_MEM2 = 0 |
| 97 | { |
| 98 | MsrRegister, |
| 99 | { |
| 100 | AMD_FAMILY_14, // CpuFamily |
| 101 | AMD_F14_ALL // CpuRevision |
| 102 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 103 | {AMD_PF_ALL}, // platformFeatures |
| 104 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 105 | MSR_TOM2, // MSR Address |
| 106 | 0x0000000000000000, // OR Mask |
| 107 | 0xFFFFFFFFFFFFFFFF, // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 108 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 109 | }, |
| 110 | // MSR_SYS_CFG (0xC0010010) |
| 111 | // bit[21] - MtrrTom2En = 1 |
| 112 | { |
| 113 | MsrRegister, |
| 114 | { |
| 115 | AMD_FAMILY_14, // CpuFamily |
| 116 | AMD_F14_ALL // CpuRevision |
| 117 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 118 | {AMD_PF_ALL}, // platformFeatures |
| 119 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 120 | MSR_SYS_CFG, // MSR Address |
| 121 | (1 << 21), // OR Mask |
| 122 | (1 << 21), // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 123 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 124 | }, |
| 125 | // MSR_CPUID_EXT_FEATS (0xC0011005) |
| 126 | // bit[41] - OSVW = 0 |
| 127 | { |
| 128 | MsrRegister, |
| 129 | { |
| 130 | AMD_FAMILY_14, // CpuFamily |
| 131 | AMD_F14_ALL // CpuRevision |
| 132 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 133 | {AMD_PF_ALL}, // platformFeatures |
| 134 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 135 | MSR_CPUID_EXT_FEATS, // MSR Address |
| 136 | 0x0000000000000000, // OR Mask |
| 137 | 0x0000020000000000, // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 138 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 139 | }, |
| 140 | // MSR_OSVW_ID_Length (0xC0010140) |
| 141 | // bit[15:0] = 4 |
| 142 | { |
| 143 | MsrRegister, |
| 144 | { |
| 145 | AMD_FAMILY_14, // CpuFamily |
| 146 | AMD_F14_ALL // CpuRevision |
| 147 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 148 | {AMD_PF_ALL}, // platformFeatures |
| 149 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 150 | MSR_OSVW_ID_Length, // MSR Address |
| 151 | 0x0000000000000004, // OR Mask |
| 152 | 0x000000000000FFFF, // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 153 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 154 | }, |
| 155 | // MSR_HWCR (0xC0010015) |
| 156 | // Do not set bit[24] = 1, it will be set in AmdInitPost. |
| 157 | |
| 158 | // This MSR should be set after the code that most errata would be applied in |
| 159 | // MSR_MC0_CTL (0x00000400) |
| 160 | // bits[63:0] = 0xFFFFFFFFFFFFFFFF |
| 161 | { |
| 162 | MsrRegister, |
| 163 | { |
| 164 | AMD_FAMILY_14, // CpuFamily |
| 165 | AMD_F14_ALL // CpuRevision |
| 166 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 167 | {AMD_PF_ALL}, // platformFeatures |
| 168 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 169 | MSR_MC0_CTL, // MSR Address |
| 170 | 0xFFFFFFFFFFFFFFFF, // OR Mask |
| 171 | 0xFFFFFFFFFFFFFFFF, // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 172 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 173 | }, |
| 174 | // MSR_LS_CFG (0xC0011020) |
| 175 | // bit[36] Reserved = 1, workaround for erratum #530 |
| 176 | // bit[25] Reserved = 1, workaround for erratum #551 |
| 177 | { |
| 178 | MsrRegister, |
| 179 | { |
| 180 | AMD_FAMILY_14, // CpuFamily |
| 181 | AMD_F14_ALL // CpuRevision |
| 182 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 183 | {AMD_PF_ALL}, // platformFeatures |
| 184 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 185 | MSR_LS_CFG, // MSR Address |
| 186 | 0x0000001002000000, // OR Mask |
| 187 | 0x0000001002000000, // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 188 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 189 | }, |
| 190 | // MSR_DC_CFG (0xC0011022) |
| 191 | // bit[57:56] Reserved = 2 |
| 192 | { |
| 193 | MsrRegister, |
| 194 | { |
| 195 | AMD_FAMILY_14, // CpuFamily |
| 196 | AMD_F14_ALL // CpuRevision |
| 197 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 198 | {AMD_PF_ALL}, // platformFeatures |
| 199 | {{ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 200 | MSR_DC_CFG, // MSR Address |
| 201 | 0x0200000000000000, // OR Mask |
| 202 | 0x0300000000000000, // NAND Mask |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 203 | }} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 204 | } |
| 205 | }; |
| 206 | |
| 207 | CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable = { |
| 208 | AllCores, |
| 209 | (sizeof (F14MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), |
| 210 | (TABLE_ENTRY_FIELDS *) &F14MsrRegisters, |
| 211 | }; |
| 212 | |
| 213 | |