Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD IDS Routines |
| 6 | * |
| 7 | * Contains AMD AGESA Integrated Debug Macros |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: IDS |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | */ |
| 14 | /* |
| 15 | ***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 19 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 29 | * from this software without specific prior written permission. |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 30 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 41 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /* Macros to aid debugging */ |
| 47 | /* These definitions expand to zero (0) bytes of code when disabled */ |
| 48 | |
| 49 | #ifndef _IDS_H_ |
| 50 | #define _IDS_H_ |
| 51 | |
| 52 | #undef FALSE |
| 53 | #undef TRUE |
| 54 | #define FALSE 0 |
| 55 | #define TRUE 1 |
| 56 | // Proto type for optionsids.h |
| 57 | typedef UINT32 IDS_STATUS; ///< Status of IDS function. |
| 58 | #define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful. |
| 59 | #define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed. |
| 60 | |
| 61 | #define IDS_STRINGIZE(a) #a ///< for define stringize macro |
| 62 | /** |
| 63 | * IDS Option Hook Points |
| 64 | * |
| 65 | * These are the values to indicate hook point in AGESA for IDS Options. |
| 66 | * |
| 67 | */ |
| 68 | typedef enum { //vv- for debug reference only |
| 69 | IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. |
| 70 | ///< IDS Object is initialized. |
| 71 | ///< Override CPU Core Leveling Mode. |
| 72 | ///< Set P-State in Post |
| 73 | IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. |
| 74 | IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. |
| 75 | ///< It will be used to control the following tables. |
| 76 | ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) |
| 77 | ///< ACPI SRAT Table |
| 78 | ///< ACPI SLIT Table |
| 79 | ///< ACPI WHEA Table |
| 80 | ///< DMI Table |
| 81 | IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. |
| 82 | IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. |
| 83 | IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. |
| 84 | IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. |
| 85 | ///< Control Interleaving and DRAM memory hole |
| 86 | ///< Override the setting of ECC Control |
| 87 | ///< Override the setting of Online Spare Rank |
| 88 | IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. |
| 89 | IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. |
| 90 | IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. |
| 91 | IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. |
| 92 | IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. |
| 93 | IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore |
| 94 | IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save |
| 95 | IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore |
| 96 | IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training |
| 97 | IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization |
| 98 | IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change |
| 99 | IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset |
| 100 | IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init |
| 101 | IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init |
| 102 | IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS |
| 103 | IDS_UCODE, ///< 16 Enable or Disable microcode patching |
| 104 | IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt |
| 105 | |
| 106 | IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used |
| 107 | IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used |
| 108 | IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used |
| 109 | IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used |
| 110 | IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used |
| 111 | IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used |
| 112 | IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used |
| 113 | IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used |
| 114 | |
| 115 | // All the above timing point is used by BVM, their value should never be changed |
| 116 | IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control |
| 117 | IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# |
| 118 | IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing |
| 119 | ///< Dram Controller, Drive Strength and DQS Timing |
| 120 | IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing |
| 121 | IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged |
| 122 | IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode |
| 123 | IDS_BURST_LENGTH32, ///< 46 override Burst Length32 |
| 124 | IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable |
| 125 | IDS_ECC, ///< 48 override ECC parameter |
| 126 | IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size |
| 127 | IDS_CPU_Early_Override, ///< 4a override CPU early parameter |
| 128 | IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt |
| 129 | IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave |
| 130 | IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery |
| 131 | IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times |
| 132 | IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit |
| 133 | IDS_HT_ASSIST, ///< 50 Override Probe Filter |
| 134 | IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result |
| 135 | IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down |
| 136 | IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement |
| 137 | IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature |
| 138 | IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure |
| 139 | IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support |
| 140 | IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory |
| 141 | IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service |
| 142 | IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake |
| 143 | IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config |
| 144 | IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration |
| 145 | IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep |
| 146 | IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config |
| 147 | IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings |
| 148 | IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature |
| 149 | IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control |
| 150 | IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around |
| 151 | IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register |
| 152 | IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop |
| 153 | IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation |
| 154 | IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions |
| 155 | IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry |
| 156 | IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround |
| 157 | IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit |
| 158 | IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting |
| 159 | IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting |
| 160 | IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg |
| 161 | IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature |
| 162 | IDS_CST_CREATE, ///< 6d Hook for create _CST |
| 163 | IDS_CST_SIZE, ///< 6e Hook for get _CST size |
| 164 | IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO |
| 165 | IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization |
| 166 | IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table |
| 167 | IDS_SKIP_FUSED_MAX_RATE ///< 72 Hook to skip fused max rate cap |
| 168 | } AGESA_IDS_OPTION; |
| 169 | |
| 170 | #include "OptionsIds.h" |
| 171 | #include "Filecode.h" |
| 172 | |
| 173 | /* Initialize IDS controls */ |
| 174 | #ifndef IDSOPT_IDS_ENABLED |
| 175 | #define IDSOPT_IDS_ENABLED FALSE |
| 176 | #endif |
| 177 | |
| 178 | #ifndef IDSOPT_CONTROL_ENABLED |
| 179 | #define IDSOPT_CONTROL_ENABLED FALSE |
| 180 | #endif |
| 181 | |
| 182 | #ifndef IDSOPT_TRACING_ENABLED |
| 183 | #define IDSOPT_TRACING_ENABLED FALSE |
| 184 | #endif |
| 185 | |
| 186 | #ifndef IDSOPT_TRACE_USER_OPTIONS |
| 187 | #define IDSOPT_TRACE_USER_OPTIONS TRUE |
| 188 | #endif |
| 189 | |
| 190 | #ifndef IDSOPT_PERF_ANALYSIS |
| 191 | #define IDSOPT_PERF_ANALYSIS FALSE |
| 192 | #endif |
| 193 | |
| 194 | #ifndef IDSOPT_HEAP_CHECKING |
| 195 | #define IDSOPT_HEAP_CHECKING FALSE |
| 196 | #endif |
| 197 | |
| 198 | #ifndef IDSOPT_ASSERT_ENABLED |
| 199 | #define IDSOPT_ASSERT_ENABLED FALSE |
| 200 | #endif |
| 201 | |
| 202 | #ifndef IDSOPT_ERROR_TRAP_ENABLED |
| 203 | #define IDSOPT_ERROR_TRAP_ENABLED FALSE |
| 204 | #endif |
| 205 | |
| 206 | #ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED |
| 207 | #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE |
| 208 | #endif |
| 209 | |
| 210 | #ifndef IDSOPT_DEBUG_CODE_ENABLED |
| 211 | #define IDSOPT_DEBUG_CODE_ENABLED FALSE |
| 212 | #endif |
| 213 | |
| 214 | #ifndef IDSOPT_C_OPTIMIZATION_DISABLED |
| 215 | #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE |
| 216 | #endif |
| 217 | |
| 218 | #if IDSOPT_IDS_ENABLED == FALSE |
| 219 | #undef IDSOPT_CONTROL_ENABLED |
| 220 | #undef IDSOPT_TRACING_ENABLED |
| 221 | #undef IDSOPT_PERF_ANALYSIS |
| 222 | #undef IDSOPT_HEAP_CHECKING |
| 223 | #undef IDSOPT_ASSERT_ENABLED |
| 224 | #undef IDSOPT_ERROR_TRAP_ENABLED |
| 225 | #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED |
| 226 | #undef IDSOPT_DEBUG_CODE_ENABLED |
| 227 | #undef IDSOPT_TRACE_USER_OPTIONS |
| 228 | |
| 229 | #define IDSOPT_CONTROL_ENABLED FALSE |
| 230 | #define IDSOPT_TRACING_ENABLED FALSE |
| 231 | #define IDSOPT_PERF_ANALYSIS FALSE |
| 232 | #define IDSOPT_HEAP_CHECKING FALSE |
| 233 | #define IDSOPT_ASSERT_ENABLED FALSE |
| 234 | #define IDSOPT_ERROR_TRAP_ENABLED FALSE |
| 235 | #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE |
| 236 | #define IDSOPT_DEBUG_CODE_ENABLED FALSE |
| 237 | #define IDSOPT_TRACE_USER_OPTIONS FALSE |
| 238 | #endif |
| 239 | |
| 240 | /** |
| 241 | * Make a Progress Report to the User. |
| 242 | * |
| 243 | * This Macro is always enabled. The default action is to write the TestPoint value |
| 244 | * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. |
| 245 | * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port |
| 246 | * in OptionsIds.h in their build tip. |
| 247 | * |
| 248 | * @param[in] TestPoint The value for display indicating progress |
| 249 | * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS |
| 250 | * |
| 251 | **/ |
| 252 | |
| 253 | #define AGESA_TESTPOINT(TestPoint, StdHeader) |
| 254 | |
| 255 | #ifndef IDS_DEBUG_PORT |
| 256 | #define IDS_DEBUG_PORT 0x80 |
| 257 | #endif |
| 258 | |
| 259 | /** |
| 260 | * @def STOP_HERE |
| 261 | * (macro) - Causes program to halt. This is @b only for use during active debugging . |
| 262 | * |
| 263 | * Causes the program to halt and display the file number of the source of the |
| 264 | * halt (displayed in decimal). |
| 265 | * |
| 266 | **/ |
| 267 | #if IDSOPT_IDS_ENABLED == TRUE |
| 268 | #ifdef STOP_CODE |
| 269 | #undef STOP_CODE |
| 270 | #endif |
| 271 | #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ |
| 272 | ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ |
| 273 | (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) |
| 274 | #define STOP_HERE |
| 275 | #else |
| 276 | #define STOP_HERE |
| 277 | #endif |
| 278 | |
| 279 | /** |
| 280 | * @def ASSERT |
| 281 | * Test an assertion that the given statement is True. |
| 282 | * |
| 283 | * The statement is evaluated to a boolean value. If the statement is True, |
| 284 | * then no action is taken (no error). If the statement is False, a error stop |
| 285 | * is generated to halt the program. Used for testing for fatal errors that |
| 286 | * must be resolved before production. This is used to do parameter checks, |
| 287 | * bounds checking, range checks and 'sanity' checks. |
| 288 | * |
| 289 | * @param[in] conditional Assert that evaluating this conditional results in TRUE. |
| 290 | * |
| 291 | **/ |
| 292 | #ifndef ASSERT |
| 293 | #if IDSOPT_ASSERT_ENABLED == TRUE |
| 294 | #ifdef STOP_CODE |
| 295 | #undef STOP_CODE |
| 296 | #endif |
| 297 | #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ |
| 298 | ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ |
| 299 | (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) |
| 300 | |
| 301 | #define ASSERT(conditional) |
| 302 | #else |
| 303 | #define ASSERT(conditional) |
| 304 | #endif |
| 305 | #endif |
| 306 | |
| 307 | #if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE |
| 308 | #undef IDSOPT_ERROR_TRAP_ENABLED |
| 309 | #define IDSOPT_ERROR_TRAP_ENABLED TRUE |
| 310 | #define IDS_CAR_CORRUPTION_CHECK(StdHeader) |
| 311 | #else |
| 312 | #define IDS_CAR_CORRUPTION_CHECK(StdHeader) |
| 313 | #endif |
| 314 | /** |
| 315 | * @def DEBUG_CODE |
| 316 | * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable |
| 317 | * |
| 318 | */ |
| 319 | #ifndef DEBUG_CODE |
| 320 | #if IDSOPT_DEBUG_CODE_ENABLED == TRUE |
| 321 | #define DEBUG_CODE(Code) |
| 322 | #else |
| 323 | #define DEBUG_CODE(Code) |
| 324 | #endif |
| 325 | #endif |
| 326 | |
| 327 | /** |
| 328 | * @def IDS_ERROR_TRAP |
| 329 | * Trap AGESA Error events with stop code display. |
| 330 | * |
| 331 | * Works similarly to use of "ASSERT (FALSE);" |
| 332 | * |
| 333 | */ |
| 334 | #if IDSOPT_ERROR_TRAP_ENABLED == TRUE |
| 335 | #ifdef STOP_CODE |
| 336 | #undef STOP_CODE |
| 337 | #endif |
| 338 | #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ |
| 339 | ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ |
| 340 | (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) |
| 341 | |
| 342 | #define IDS_ERROR_TRAP |
| 343 | #else |
| 344 | #define IDS_ERROR_TRAP |
| 345 | #endif |
| 346 | |
| 347 | ///give the extended Macro default value |
| 348 | #ifndef __IDS_EXTENDED__ |
| 349 | #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS |
| 350 | #define IDS_INITIAL_F10_PM_STEP |
| 351 | #define IDS_INITIAL_F12_PM_STEP |
| 352 | #define IDS_INITIAL_F14_PM_STEP |
| 353 | #define IDS_INITIAL_F15_PM_STEP |
| 354 | #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) |
| 355 | #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) |
| 356 | #define IDS_EXTENDED_HEAP_SIZE 0 |
| 357 | #define IDS_EXT_INCLUDE_F10(file) |
| 358 | #define IDS_EXT_INCLUDE_F12(file) |
| 359 | #define IDS_EXT_INCLUDE_F14(file) |
| 360 | #define IDS_EXT_INCLUDE_F15(file) |
| 361 | #define IDS_EXT_INCLUDE(file) |
| 362 | #endif |
| 363 | |
| 364 | #ifndef IDS_NUM_NV_ITEM |
| 365 | #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) |
| 366 | #endif |
| 367 | |
| 368 | #if IDSOPT_CONTROL_ENABLED == TRUE |
| 369 | #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) |
| 370 | |
| 371 | #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) |
| 372 | #else |
| 373 | #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) |
| 374 | |
| 375 | #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) |
| 376 | #endif |
| 377 | |
| 378 | /** |
| 379 | * Macro to add a *skip* hook for IDS options |
| 380 | * |
| 381 | * The default minimal action is to do nothing and there is no any code to increase. |
| 382 | * For debug environments, IDS dispatcher function will be called to perform |
| 383 | * the detailed action and to skip AGESA code if necessary. |
| 384 | * |
| 385 | * @param[in] IdsOption IDS Option ID for this hook point |
| 386 | * @param[in, out] DataPtr Data Pointer to override |
| 387 | * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS |
| 388 | * |
| 389 | * |
| 390 | **/ |
| 391 | |
| 392 | #if IDSOPT_CONTROL_ENABLED == TRUE |
| 393 | #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) |
| 394 | #else |
| 395 | #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) |
| 396 | #endif |
| 397 | |
| 398 | /** |
| 399 | * Macro to add a heap manager routine |
| 400 | * |
| 401 | * when memory is allocated the heap manager actually allocates two extra dwords of data, |
| 402 | * one dword buffer before the actual memory, and one dword afterwards. |
| 403 | * a complete heap walk and check to be performed at any time. |
| 404 | * it would ASSERT if the heap is corrupt |
| 405 | * |
| 406 | * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS |
| 407 | * |
| 408 | * |
| 409 | **/ |
| 410 | |
| 411 | // Heap debug feature |
| 412 | #define SENTINEL_BEFORE_VALUE 0x64616548 // "Head" |
| 413 | #define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail" |
| 414 | #if IDSOPT_IDS_ENABLED == TRUE |
| 415 | #if IDSOPT_HEAP_CHECKING == TRUE |
| 416 | #define SIZE_OF_SENTINEL 0 |
| 417 | #define NUM_OF_SENTINEL 0 |
| 418 | #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) |
| 419 | #define SET_SENTINEL_AFTER(NodePtr) |
| 420 | #define Heap_Check(stdheader) |
| 421 | #else |
| 422 | #define SIZE_OF_SENTINEL 0 |
| 423 | #define NUM_OF_SENTINEL 0 |
| 424 | #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) |
| 425 | #define SET_SENTINEL_AFTER(NodePtr) |
| 426 | #define Heap_Check(stdheader) |
| 427 | #endif |
| 428 | #else |
| 429 | #define SIZE_OF_SENTINEL 0 |
| 430 | #define NUM_OF_SENTINEL 0 |
| 431 | #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) |
| 432 | #define SET_SENTINEL_AFTER(NodePtr) |
| 433 | #define Heap_Check(stdheader) |
| 434 | #endif |
| 435 | |
| 436 | |
| 437 | //Note a is from 0 to 63 |
| 438 | #define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a) |
| 439 | //If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly |
| 440 | //Memory Masks |
| 441 | #define MEM_SETREG DEBUG_PRINT_SHIFT (0) |
| 442 | #define MEM_GETREG DEBUG_PRINT_SHIFT (1) |
| 443 | #define MEM_FLOW DEBUG_PRINT_SHIFT (2) |
| 444 | #define MEM_STATUS DEBUG_PRINT_SHIFT (3) |
| 445 | #define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4) |
| 446 | #define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) |
| 447 | #define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) |
| 448 | #define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) |
| 449 | #define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) |
| 450 | #define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9) |
| 451 | |
| 452 | |
| 453 | |
| 454 | //CPU Masks |
| 455 | #define CPU_TRACE DEBUG_PRINT_SHIFT (10) |
| 456 | #define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11) |
| 457 | #define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12) |
| 458 | #define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13) |
| 459 | #define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14) |
| 460 | #define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15) |
| 461 | #define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16) |
| 462 | #define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17) |
| 463 | #define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18) |
| 464 | #define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19) |
| 465 | |
| 466 | //GNB Masks |
| 467 | #define GNB_TRACE DEBUG_PRINT_SHIFT (20) |
| 468 | #define PCIE_MISC DEBUG_PRINT_SHIFT (21) |
| 469 | #define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22) |
| 470 | #define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23) |
| 471 | #define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24) |
| 472 | #define NB_MISC DEBUG_PRINT_SHIFT (25) |
| 473 | #define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26) |
| 474 | #define GFX_MISC DEBUG_PRINT_SHIFT (27) |
| 475 | #define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28) |
| 476 | #define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29) |
| 477 | |
| 478 | //HT Masks |
| 479 | #define HT_TRACE DEBUG_PRINT_SHIFT (30) |
| 480 | #define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31) |
| 481 | #define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32) |
| 482 | #define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33) |
| 483 | #define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34) |
| 484 | #define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35) |
| 485 | #define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36) |
| 486 | #define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37) |
| 487 | #define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38) |
| 488 | #define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39) |
| 489 | |
| 490 | //FCH Masks |
| 491 | #define FCH_TRACE DEBUG_PRINT_SHIFT (40) |
| 492 | #define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41) |
| 493 | #define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42) |
| 494 | #define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43) |
| 495 | #define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44) |
| 496 | #define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45) |
| 497 | #define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46) |
| 498 | #define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47) |
| 499 | #define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48) |
| 500 | #define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49) |
| 501 | |
| 502 | //Other Masks |
| 503 | #define MAIN_FLOW DEBUG_PRINT_SHIFT (50) |
| 504 | #define EVENT_LOG DEBUG_PRINT_SHIFT (51) |
| 505 | #define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52) |
| 506 | |
| 507 | //Ids Masks |
| 508 | #define IDS_TRACE DEBUG_PRINT_SHIFT (53) |
| 509 | #define IDS_REG DEBUG_PRINT_SHIFT (54) |
| 510 | #define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55) |
| 511 | #define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56) |
| 512 | |
| 513 | //S3 |
| 514 | #define S3_TRACE DEBUG_PRINT_SHIFT (57) |
| 515 | |
| 516 | |
| 517 | //Reserved |
| 518 | #define TRACE_RSV1 DEBUG_PRINT_SHIFT (58) |
| 519 | #define TRACE_RSV2 DEBUG_PRINT_SHIFT (59) |
| 520 | #define TRACE_RSV3 DEBUG_PRINT_SHIFT (60) |
| 521 | #define TRACE_RSV4 DEBUG_PRINT_SHIFT (61) |
| 522 | #define TRACE_RSV5 DEBUG_PRINT_SHIFT (62) |
| 523 | #define TRACE_RSV6 DEBUG_PRINT_SHIFT (63) |
| 524 | |
| 525 | #define GNB_TRACE_DEFAULT 0 |
| 526 | |
| 527 | #define GNB_TRACE_REG 0 |
| 528 | |
| 529 | #define GNB_TRACE_ALL 0 |
| 530 | |
| 531 | #define CPU_TRACE_ALL 0 |
| 532 | |
| 533 | #define MEMORY_TRACE_ALL 0 |
| 534 | |
| 535 | #define HT_TRACE_ALL 0 |
| 536 | |
| 537 | #define FCH_TRACE_ALL 0 |
| 538 | |
| 539 | #define IDS_TRACE_ALL 0 |
| 540 | |
| 541 | #define OTHER_TRACE_ALL 0 |
| 542 | |
| 543 | #define TRACE_MASK_ALL (0ull) |
| 544 | #ifndef IDS_DEBUG_PRINT_MASK |
| 545 | #define IDS_DEBUG_PRINT_MASK 0 |
| 546 | #endif |
| 547 | |
| 548 | |
| 549 | /** |
| 550 | * Macro to add HDT OUT |
| 551 | * |
| 552 | * The default minimal action is to do nothing and there is no any code to increase. |
| 553 | * For debug environments, the debug information can be displayed in HDT or other |
| 554 | * devices. |
| 555 | * |
| 556 | **/ |
| 557 | #if IDSOPT_IDS_ENABLED == TRUE |
| 558 | #if IDSOPT_TRACING_ENABLED == TRUE |
| 559 | #define IDS_HDT_CONSOLE_INIT(x) |
| 560 | #define IDS_HDT_CONSOLE_EXIT(x) |
| 561 | #define IDS_HDT_CONSOLE_S3_EXIT(x) |
| 562 | #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) |
| 563 | |
Kyösti Mälkki | 86ee4db | 2016-06-22 22:50:10 +0300 | [diff] [blame] | 564 | #ifndef __GNUC__ |
| 565 | #pragma warning(disable: 4127) |
| 566 | #define IDS_HDT_CONSOLE(f, s, ...) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 567 | #else |
Kyösti Mälkki | 86ee4db | 2016-06-22 22:50:10 +0300 | [diff] [blame] | 568 | #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 569 | #endif |
| 570 | |
| 571 | #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) |
| 572 | #define IDS_HDT_CONSOLE_ASSERT(x) |
| 573 | #define IDS_FUNCLIST_ADDR NULL |
| 574 | #define IDS_FUNCLIST_EXTERN() |
| 575 | #define IDS_TIMEOUT_CTL(t) |
| 576 | #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) |
| 577 | #define CONSOLE(s, ...) |
| 578 | #else |
| 579 | #define IDS_HDT_CONSOLE_INIT(x) |
| 580 | #define IDS_HDT_CONSOLE_EXIT(x) |
| 581 | #define IDS_HDT_CONSOLE_S3_EXIT(x) |
| 582 | #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) |
| 583 | #define IDS_HDT_CONSOLE(f, s, ...) |
| 584 | #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) |
| 585 | #define IDS_HDT_CONSOLE_ASSERT(x) |
| 586 | #define IDS_FUNCLIST_ADDR NULL |
| 587 | #define IDS_FUNCLIST_EXTERN() |
| 588 | #define IDS_TIMEOUT_CTL(t) |
| 589 | #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) |
| 590 | #define CONSOLE(s, ...) |
| 591 | #endif |
| 592 | #else |
| 593 | #define IDS_HDT_CONSOLE_INIT(x) |
| 594 | #define IDS_HDT_CONSOLE_EXIT(x) |
| 595 | #define IDS_HDT_CONSOLE_S3_EXIT(x) |
| 596 | #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) |
| 597 | #define IDS_HDT_CONSOLE(f, s, ...) |
| 598 | #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) |
| 599 | #define IDS_HDT_CONSOLE_ASSERT(x) |
| 600 | #define IDS_FUNCLIST_ADDR NULL |
| 601 | #define IDS_FUNCLIST_EXTERN() |
| 602 | #define IDS_TIMEOUT_CTL(t) |
| 603 | #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) |
| 604 | #define CONSOLE(s, ...) |
| 605 | #endif |
| 606 | |
| 607 | #define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS |
| 608 | |
| 609 | #if IDSOPT_PERF_ANALYSIS == TRUE |
| 610 | #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) |
| 611 | #define IDS_PERF_ANALYSE(StdHeader) |
| 612 | #define IDS_PERF_TIME_MEASURE(StdHeader) |
| 613 | #else |
| 614 | #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) |
| 615 | #define IDS_PERF_ANALYSE(StdHeader) |
| 616 | #define IDS_PERF_TIME_MEASURE(StdHeader) |
| 617 | #endif |
| 618 | |
| 619 | ///For IDS feat use |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 620 | #define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 621 | #define IDS_BSP_ONLY TRUE |
| 622 | #define IDS_ALL_CORES FALSE |
| 623 | |
| 624 | #define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE |
| 625 | |
| 626 | #define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization. |
| 627 | |
| 628 | #define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table. |
| 629 | #define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table. |
| 630 | #define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config. |
| 631 | #define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig. |
| 632 | #define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config. |
| 633 | #define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config. |
| 634 | #define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override |
| 635 | |
| 636 | /// Function entry for HDT script to call |
| 637 | typedef struct _SCRIPT_FUNCTION { |
Stefan Reinauer | d91ddc8 | 2015-07-30 11:17:40 -0700 | [diff] [blame] | 638 | UINTN FuncAddr; ///< Function address in ROM |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 639 | CHAR8 FuncName[40]; ///< Function name |
| 640 | } SCRIPT_FUNCTION; |
| 641 | |
| 642 | /// Data Structure for Mem ECC parameter override |
| 643 | typedef struct { |
| 644 | IN BOOLEAN CfgEccRedirection; ///< ECC Redirection |
| 645 | IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate |
| 646 | IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate |
| 647 | IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate |
| 648 | IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate |
| 649 | IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate |
| 650 | IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood |
| 651 | } ECC_OVERRIDE_STRUCT; |
| 652 | |
| 653 | |
| 654 | |
| 655 | |
| 656 | /** |
| 657 | * AGESA Test Points |
| 658 | * |
| 659 | * These are the values displayed to the user to indicate progress through boot. |
| 660 | * These can be used in a debug environment to stop the debugger at a specific |
| 661 | * test point: |
| 662 | * For SimNow!, this command |
| 663 | * bi 81 w vb 49 |
| 664 | * will stop the debugger on one of the TracePoints (49 is the TP value in this example). |
| 665 | * |
| 666 | */ |
| 667 | typedef enum { |
| 668 | StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs |
| 669 | |
| 670 | // Memory test points |
| 671 | TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) |
| 672 | TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) |
| 673 | TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) |
| 674 | TpProcMemDramInit, ///< 04 .. DRAM initialization |
| 675 | TpProcMemSPDChecking, ///< 05 .. |
| 676 | TpProcMemModeChecking, ///< 06 .. |
| 677 | TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration |
| 678 | TpProcMemSpdTiming, ///< 08 .. |
| 679 | TpProcMemDramMapping, ///< 09 .. |
| 680 | TpProcMemPlatformSpecificConfig, ///< 0A .. |
| 681 | TPProcMemPhyCompensation, ///< 0B .. |
| 682 | TpProcMemStartDcts, ///< 0C .. |
| 683 | TpProcMemBeforeDramInit, ///< 0D .. (Public interface) |
| 684 | TpProcMemPhyFenceTraining, ///< 0E .. |
| 685 | TpProcMemSynchronizeDcts, ///< 0F .. |
| 686 | TpProcMemSystemMemoryMapping, ///< 10 .. |
| 687 | TpProcMemMtrrConfiguration, ///< 11 .. |
| 688 | TpProcMemDramTraining, ///< 12 .. |
| 689 | TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) |
| 690 | TpProcMemWriteLevelizationTraining, ///< 14 .. |
| 691 | TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start |
| 692 | TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start |
| 693 | TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured |
| 694 | TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL |
| 695 | TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL |
| 696 | TpProcMemReceiverEnableTraining, ///< 1A .. |
| 697 | TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop |
| 698 | TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay |
| 699 | TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern |
| 700 | TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern |
| 701 | TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern |
| 702 | TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel |
| 703 | TpProcMemReceiveDqsTraining, ///< 21 .. |
| 704 | TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay |
| 705 | TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern |
| 706 | TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep |
| 707 | TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay |
| 708 | TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern |
| 709 | TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern |
| 710 | TpProcMemRcvDqsResults, ///< 28 .. Update results |
| 711 | TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window |
| 712 | TpProcMemTransmitDqsTraining, ///< 2A .. |
| 713 | TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep |
| 714 | TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay |
| 715 | TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern |
| 716 | TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern |
| 717 | TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern |
| 718 | TpProcMemTxDqResults, ///< 30 .. Update results |
| 719 | TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window |
| 720 | TpProcMemMaxRdLatencyTraining, ///< 32 .. |
| 721 | TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep |
| 722 | TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay |
| 723 | TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern |
| 724 | TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern |
| 725 | TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern |
| 726 | TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init |
| 727 | TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init |
| 728 | TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init |
| 729 | TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init |
| 730 | TpProcMemEccInitialization, ///< 3C .. ECC initialization |
| 731 | TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init |
| 732 | TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" |
| 733 | TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" |
| 734 | TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" |
| 735 | TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" |
| 736 | TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" |
| 737 | TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" |
| 738 | TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" |
| 739 | TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" |
| 740 | TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit |
| 741 | TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT |
| 742 | TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 |
| 743 | TpProcMemInitMCT, ///< 49 .. Before InitMCT |
| 744 | TpProcMemOtherTiming, ///< 4A.. Before OtherTiming |
| 745 | TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping |
| 746 | TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs |
| 747 | TpProcMemMemClr, ///< 4D .. Before MemClr |
| 748 | TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal |
| 749 | TpProcMemDmi, ///< 4F .. Before DMI |
| 750 | TpProcMemEnd, ///< 50 .. End of memory code |
| 751 | |
| 752 | // CPU test points |
| 753 | TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords |
| 754 | TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt |
| 755 | TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling |
| 756 | TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData |
| 757 | TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea |
| 758 | TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat |
| 759 | TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit |
| 760 | TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing |
| 761 | TpProcCpuSetBrandID, ///< 59 .. Set brand ID |
| 762 | TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC |
| 763 | TpProcCpuLoadUcode, ///< 5B .. Load microcode patch |
| 764 | TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point |
| 765 | TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing |
| 766 | TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point |
| 767 | TpProcCpuCoreLeveling, ///< 5F .. Core Leveling |
| 768 | TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up |
| 769 | TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point |
| 770 | TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling |
| 771 | TpProcCpuBeforeAllocateWheaBuffer, ///< 63 .. Before the WHEA init code calls out to allocate a buffer |
| 772 | TpProcCpuAfterAllocateWheaBuffer, ///< 64 .. After the WHEA init code calls out to allocate a buffer |
| 773 | TpProcCpuBeforeAllocateSratBuffer, ///< 65 .. Before the SRAT init code calls out to allocate a buffer |
| 774 | TpProcCpuAfterAllocateSratBuffer, ///< 66 .. After the SRAT init code calls out to allocate a buffer |
| 775 | TpProcCpuBeforeLocateSsdtBuffer, ///< 67 .. Before the P-state init code calls out to locate a buffer |
| 776 | TpProcCpuAfterLocateSsdtBuffer, ///< 68 .. After the P-state init code calls out to locate a buffer |
| 777 | TpProcCpuBeforeAllocateSsdtBuffer, ///< 69 .. Before the P-state init code calls out to allocate a buffer |
| 778 | TpProcCpuAfterAllocateSsdtBuffer, ///< 6A .. After the P-state init code calls out to allocate a buffer |
| 779 | |
| 780 | // HT test points |
| 781 | TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) |
| 782 | TpProcHtTopology, ///< 72 .. Topology match, routing, begin |
| 783 | TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin |
| 784 | TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin |
| 785 | TpProcHtOptGather, ///< 75 .. Optimization: Gather begin |
| 786 | TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin |
| 787 | TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin |
| 788 | TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin |
| 789 | TpProcHtOptFinish, ///< 79 .. Optimization: Set begin |
| 790 | TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin |
| 791 | TpProcHtTuning, ///< 7B .. Misc Tuning Begin |
| 792 | TpProcHtDone, ///< 7C .. HT Init complete |
| 793 | TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin |
| 794 | TpProcHtApMapDone, ///< 7E .. AP HT: Complete |
| 795 | |
| 796 | StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs |
| 797 | TpNbxxx, ///< 91 . |
| 798 | EndNbTestPoints, ///< 92 End of TP range for NB |
| 799 | |
| 800 | StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs |
| 801 | TpSbxxx, ///< B1 . |
| 802 | EndSbTestPoints, ///< B2 End of TP range for SB |
| 803 | |
| 804 | // Interface test points |
| 805 | TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset |
| 806 | TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset |
| 807 | TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery |
| 808 | TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery |
| 809 | TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly |
| 810 | TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly |
| 811 | TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost |
| 812 | TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost |
| 813 | TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv |
| 814 | TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv |
| 815 | TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid |
| 816 | TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid |
| 817 | TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate |
| 818 | TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate |
| 819 | TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save |
| 820 | TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save |
| 821 | TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume |
| 822 | TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume |
| 823 | TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore |
| 824 | TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore |
| 825 | TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore |
| 826 | TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore |
| 827 | TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog |
| 828 | TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog |
| 829 | TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId |
| 830 | TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId |
| 831 | TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress |
| 832 | TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress |
| 833 | TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore |
| 834 | TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore |
| 835 | TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP |
| 836 | TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP |
| 837 | TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data |
| 838 | TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data |
| 839 | TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer |
| 840 | TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer |
| 841 | TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer |
| 842 | TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer |
| 843 | TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer |
| 844 | TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer |
| 845 | TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP |
| 846 | TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP |
| 847 | TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP |
| 848 | TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP |
| 849 | TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer |
| 850 | TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer |
| 851 | TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer |
| 852 | TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer |
| 853 | TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer |
| 854 | TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer |
| 855 | TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer |
| 856 | TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer |
| 857 | TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer |
| 858 | TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer |
| 859 | TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer |
| 860 | TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer |
| 861 | TpPerfUnit, ///< F8 .. The Unit of performance measure. |
| 862 | EndAgesaTps = 0xFF, ///< Last defined AGESA TP |
| 863 | } AGESA_TP; |
| 864 | |
| 865 | ///Ids Feat description |
| 866 | typedef enum { |
| 867 | IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update |
| 868 | IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate |
| 869 | IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate |
| 870 | IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control |
| 871 | IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size |
| 872 | IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock |
| 873 | IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode |
| 874 | IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length |
| 875 | IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down |
| 876 | IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down |
| 877 | IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter |
| 878 | IDS_FEAT_HDTOUT, ///< Feat for hdt out |
| 879 | IDS_FEAT_HT_SETTING, ///< Feat for Ht setting |
| 880 | IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config |
| 881 | IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature |
| 882 | IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control |
| 883 | IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping |
| 884 | IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy |
| 885 | IDS_FEAT_END = 0xFF ///< End of Common feat |
| 886 | } IDS_FEAT; |
| 887 | |
| 888 | typedef IDS_STATUS IDS_COMMON_FUNC ( |
| 889 | IN OUT VOID *DataPtr, |
| 890 | IN OUT AMD_CONFIG_PARAMS *StdHeader, |
| 891 | IN IDS_NV_ITEM *IdsNvPtr |
| 892 | ); |
| 893 | |
| 894 | typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; |
| 895 | |
| 896 | /// Data Structure of IDS Feature block |
| 897 | typedef struct _IDS_FEAT_STRUCT { |
| 898 | IDS_FEAT IdsFeat; ///< Ids Feat ID |
| 899 | BOOLEAN IsBsp; ///< swith for Bsp check |
| 900 | AGESA_IDS_OPTION IdsOption; ///< IDS option |
| 901 | UINT64 CpuFamily; ///< |
| 902 | PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function |
| 903 | } IDS_FEAT_STRUCT; |
| 904 | |
| 905 | |
| 906 | /// Data Structure of IDS option |
| 907 | typedef struct _IDS_OPTION_STRUCT { |
| 908 | AGESA_IDS_OPTION idsoption; ///< IDS option |
| 909 | PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function |
| 910 | } IDS_OPTION_STRUCT; |
| 911 | |
| 912 | /// Data Structure of IDS option table |
| 913 | typedef struct _IDS_OPTION_STRUCT_TBL { |
| 914 | UINT8 version; ///<Version of IDS option table |
| 915 | UINT16 size; ///<Size of IDS option table |
| 916 | CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure |
| 917 | } IDS_OPTION_STRUCT_TBL; |
| 918 | |
| 919 | #endif // _IDS_H_ |