Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of build option: GNB |
| 6 | * |
| 7 | * Contains AMD AGESA install macros and test conditions. Output is the |
| 8 | * defaults tables reflecting the User's build options selection. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: Options |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 13 | * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _OPTION_GNB_INSTALL_H_ |
| 48 | #define _OPTION_GNB_INSTALL_H_ |
| 49 | |
| 50 | #include "S3SaveState.h" |
| 51 | /* This option is designed to be included into the platform solution install |
| 52 | * file. The platform solution install file will define the options status. |
| 53 | * Check to validate the definition |
| 54 | */ |
| 55 | |
Kyösti Mälkki | ba4e695 | 2017-08-31 15:17:36 +0300 | [diff] [blame] | 56 | #define GNB_TYPE_LN FALSE |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 57 | #define GNB_TYPE_ON OPTION_FAMILY14H |
| 58 | #define GNB_TYPE_KR FALSE |
| 59 | #define GNB_TYPE_TN FALSE |
| 60 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 61 | #include "Gnb.h" |
| 62 | #include "GnbPcie.h" |
| 63 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 64 | #ifndef CFG_IGFX_AS_PCIE_EP |
| 65 | #define CFG_IGFX_AS_PCIE_EP TRUE |
| 66 | #endif |
| 67 | |
| 68 | #ifndef CFG_LCLK_DEEP_SLEEP_EN |
| 69 | #if (GNB_TYPE_ON == TRUE) |
| 70 | #define CFG_LCLK_DEEP_SLEEP_EN TRUE |
| 71 | #else |
| 72 | #define CFG_LCLK_DEEP_SLEEP_EN FALSE |
| 73 | #endif |
| 74 | #endif |
| 75 | |
| 76 | #ifndef CFG_LCLK_DPM_EN |
| 77 | #if (GNB_TYPE_ON == TRUE) |
| 78 | #define CFG_LCLK_DPM_EN TRUE |
| 79 | #else |
| 80 | #define CFG_LCLK_DPM_EN FALSE |
| 81 | #endif |
| 82 | #endif |
| 83 | |
| 84 | #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY |
| 85 | #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE |
| 86 | #endif |
| 87 | |
| 88 | #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE |
| 89 | #if (GNB_TYPE_ON == TRUE) |
| 90 | #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE |
| 91 | #else |
| 92 | #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE |
| 93 | #endif |
| 94 | #endif |
| 95 | |
| 96 | #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE |
| 97 | #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE |
| 98 | #endif |
| 99 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 100 | #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING |
| 101 | #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) |
| 102 | #endif |
| 103 | |
| 104 | #ifndef CFG_GNB_PCIE_LINK_L0_POOLING |
| 105 | #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) |
| 106 | #endif |
| 107 | |
| 108 | #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME |
| 109 | #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) |
| 110 | #endif |
| 111 | |
| 112 | #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME |
| 113 | #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) |
| 114 | #endif |
| 115 | |
| 116 | #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM |
| 117 | #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM |
| 118 | #else |
| 119 | #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard |
| 120 | #endif |
| 121 | |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 122 | CONST GNB_BUILD_OPTIONS GnbBuildOptions = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 123 | CFG_IGFX_AS_PCIE_EP, |
| 124 | CFG_LCLK_DEEP_SLEEP_EN, |
| 125 | CFG_LCLK_DPM_EN, |
| 126 | CFG_GMC_POWER_GATE_STUTTER_ONLY, |
| 127 | CFG_SMU_SCLK_CLOCK_GATING_ENABLE, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 128 | CFG_PCIE_ASPM_BLACK_LIST_ENABLE, |
| 129 | CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, |
| 130 | CFG_GNB_PCIE_LINK_L0_POOLING, |
| 131 | CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, |
| 132 | CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, |
| 133 | CFG_GNB_PCIE_TRAINING_ALGORITHM |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | |
| 137 | |
| 138 | #if (AGESA_ENTRY_INIT_EARLY == TRUE) |
| 139 | //--------------------------------------------------------------------------------------------------- |
| 140 | #ifndef OPTION_NB_EARLY_INIT |
| 141 | #define OPTION_NB_EARLY_INIT TRUE |
| 142 | #endif |
| 143 | #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 144 | OPTION_GNB_FEATURE NbInitAtEarly; |
| 145 | #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly}, |
| 146 | #else |
| 147 | #define OPTION_NBINITATEARLY_ENTRY |
| 148 | #endif |
| 149 | //--------------------------------------------------------------------------------------------------- |
| 150 | // SMU init |
| 151 | #ifndef OPTION_SMU |
| 152 | #define OPTION_SMU TRUE |
| 153 | #endif |
| 154 | #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) |
| 155 | OPTION_GNB_FEATURE F12NbSmuInitFeature; |
| 156 | #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, |
| 157 | #else |
| 158 | #define OPTION_F12NBSMUINITFEATURE_ENTRY |
| 159 | #endif |
| 160 | #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) |
| 161 | OPTION_GNB_FEATURE F14NbSmuInitFeature; |
| 162 | #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, |
| 163 | #else |
| 164 | #define OPTION_F14NBSMUINITFEATURE_ENTRY |
| 165 | #endif |
| 166 | #if (OPTION_SMU == TRUE) && (GNB_TYPE_KR == TRUE) |
| 167 | OPTION_GNB_FEATURE KRNbSmuInitFeature; |
| 168 | #define OPTION_KRNBSMUINITFEATURE_ENTRY {AMD_FAMILY_KR, KRNbSmuInitFeature}, |
| 169 | #else |
| 170 | #define OPTION_KRNBSMUINITFEATURE_ENTRY |
| 171 | #endif |
| 172 | //--------------------------------------------------------------------------------------------------- |
| 173 | #ifndef OPTION_PCIE_CONFIG_INIT |
| 174 | #define OPTION_PCIE_CONFIG_INIT TRUE |
| 175 | #endif |
| 176 | #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 177 | OPTION_GNB_FEATURE PcieConfigurationInit; |
| 178 | #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit}, |
| 179 | #else |
| 180 | #define OPTION_PCIECONFIGURATIONINIT_ENTRY |
| 181 | #endif |
| 182 | //--------------------------------------------------------------------------------------------------- |
| 183 | #ifndef OPTION_PCIE_EARLY_INIT |
| 184 | #define OPTION_PCIE_EARLY_INIT TRUE |
| 185 | #endif |
| 186 | #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 187 | OPTION_GNB_FEATURE PcieInitAtEarly; |
| 188 | #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly}, |
| 189 | #else |
| 190 | #define OPTION_PCIEINITATEARLY_ENTRY |
| 191 | #endif |
| 192 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 193 | CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 194 | OPTION_NBINITATEARLY_ENTRY |
| 195 | OPTION_F12NBSMUINITFEATURE_ENTRY |
| 196 | OPTION_F14NBSMUINITFEATURE_ENTRY |
| 197 | OPTION_KRNBSMUINITFEATURE_ENTRY |
| 198 | OPTION_PCIECONFIGURATIONINIT_ENTRY |
| 199 | OPTION_PCIEINITATEARLY_ENTRY |
| 200 | {0, NULL} |
| 201 | }; |
| 202 | |
| 203 | #endif |
| 204 | |
| 205 | #if (AGESA_ENTRY_INIT_POST == TRUE) |
| 206 | //--------------------------------------------------------------------------------------------------- |
| 207 | #ifndef OPTION_GFX_CONFIG_POST_INIT |
| 208 | #define OPTION_GFX_CONFIG_POST_INIT TRUE |
| 209 | #endif |
| 210 | #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 211 | OPTION_GNB_FEATURE GfxConfigPostInterface; |
| 212 | #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface}, |
| 213 | #else |
| 214 | #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY |
| 215 | #endif |
| 216 | //--------------------------------------------------------------------------------------------------- |
| 217 | #ifndef OPTION_GFX_POST_INIT |
| 218 | #define OPTION_GFX_POST_INIT TRUE |
| 219 | #endif |
| 220 | #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 221 | OPTION_GNB_FEATURE GfxInitAtPost; |
| 222 | #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost}, |
| 223 | #else |
| 224 | #define OPTION_GFXINITATPOST_ENTRY |
| 225 | #endif |
| 226 | //--------------------------------------------------------------------------------------------------- |
| 227 | #ifndef OPTION_NB_POST_INIT |
| 228 | #define OPTION_NB_POST_INIT TRUE |
| 229 | #endif |
| 230 | #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 231 | OPTION_GNB_FEATURE NbInitAtPost; |
| 232 | #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost}, |
| 233 | #else |
| 234 | #define OPTION_NBINITATPOST_ENTRY |
| 235 | #endif |
| 236 | //--------------------------------------------------------------------------------------------------- |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 237 | #ifndef OPTION_PCIE_POST_EALRY_INIT |
| 238 | #define OPTION_PCIE_POST_EALRY_INIT TRUE |
| 239 | #endif |
| 240 | #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) |
| 241 | OPTION_GNB_FEATURE PcieInitAtPostEarly; |
| 242 | #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly}, |
| 243 | #else |
| 244 | #define OPTION_PCIEINITATPOSTEARLY_ENTRY |
| 245 | #endif |
| 246 | //--------------------------------------------------------------------------------------------------- |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 247 | #ifndef OPTION_PCIE_POST_INIT |
| 248 | #define OPTION_PCIE_POST_INIT TRUE |
| 249 | #endif |
| 250 | #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 251 | OPTION_GNB_FEATURE PcieInitAtPost; |
| 252 | #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost}, |
| 253 | #else |
| 254 | #define OPTION_PCIEINITATPOST_ENTRY |
| 255 | #endif |
| 256 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 257 | CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 258 | OPTION_PCIEINITATPOSTEARLY_ENTRY |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 259 | OPTION_GFXCONFIGPOSTINTERFACE_ENTRY |
| 260 | OPTION_GFXINITATPOST_ENTRY |
| 261 | {0, NULL} |
| 262 | }; |
| 263 | |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 264 | CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 265 | OPTION_NBINITATPOST_ENTRY |
| 266 | OPTION_PCIEINITATPOST_ENTRY |
| 267 | {0, NULL} |
| 268 | }; |
| 269 | #endif |
| 270 | |
| 271 | #if (AGESA_ENTRY_INIT_ENV == TRUE) |
| 272 | //--------------------------------------------------------------------------------------------------- |
| 273 | #ifndef OPTION_FUSE_TABLE_INIT |
| 274 | #define OPTION_FUSE_TABLE_INIT TRUE |
| 275 | #endif |
| 276 | #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 277 | OPTION_GNB_FEATURE NbFuseTableFeature; |
| 278 | #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature}, |
| 279 | #else |
| 280 | #define OPTION_NBFUSETABLEFEATURE_ENTRY |
| 281 | #endif |
| 282 | //--------------------------------------------------------------------------------------------------- |
| 283 | #ifndef OPTION_NB_ENV_INIT |
| 284 | #define OPTION_NB_ENV_INIT TRUE |
| 285 | #endif |
| 286 | #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 287 | OPTION_GNB_FEATURE NbInitAtEnv; |
| 288 | #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv}, |
| 289 | #else |
| 290 | #define OPTION_NBINITATENVT_ENTRY |
| 291 | #endif |
| 292 | //--------------------------------------------------------------------------------------------------- |
| 293 | #ifndef OPTION_GFX_CONFIG_ENV_INIT |
| 294 | #define OPTION_GFX_CONFIG_ENV_INIT TRUE |
| 295 | #endif |
| 296 | #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 297 | OPTION_GNB_FEATURE GfxConfigEnvInterface; |
| 298 | #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface}, |
| 299 | #else |
| 300 | #define OPTION_GFXCONFIGENVINTERFACE_ENTRY |
| 301 | #endif |
| 302 | |
| 303 | //--------------------------------------------------------------------------------------------------- |
| 304 | #ifndef OPTION_GFX_ENV_INIT |
| 305 | #define OPTION_GFX_ENV_INIT TRUE |
| 306 | #endif |
| 307 | #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 308 | OPTION_GNB_FEATURE GfxInitAtEnvPost; |
| 309 | #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost}, |
| 310 | #else |
| 311 | #define OPTION_GFXINITATENVPOST_ENTRY |
| 312 | #endif |
| 313 | //--------------------------------------------------------------------------------------------------- |
| 314 | #ifndef OPTION_POWER_GATE |
| 315 | #define OPTION_POWER_GATE TRUE |
| 316 | #endif |
| 317 | #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) |
| 318 | OPTION_GNB_FEATURE F12NbPowerGateFeature; |
| 319 | #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, |
| 320 | #else |
| 321 | #define OPTION_F12NBPOWERGATEFEATURE_ENTRY |
| 322 | #endif |
| 323 | #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) |
| 324 | OPTION_GNB_FEATURE F14NbPowerGateFeature; |
| 325 | #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, |
| 326 | #else |
| 327 | #define OPTION_F14NBPOWERGATEFEATURE_ENTRY |
| 328 | #endif |
| 329 | #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_KR == TRUE) |
| 330 | OPTION_GNB_FEATURE KRNbPowerGateFeature; |
| 331 | #define OPTION_KRNBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_KR, KRNbPowerGateFeature}, |
| 332 | #else |
| 333 | #define OPTION_KRNBPOWERGATEFEATURE_ENTRY |
| 334 | #endif |
| 335 | //--------------------------------------------------------------------------------------------------- |
| 336 | #ifndef OPTION_PCIE_ENV_INIT |
| 337 | #define OPTION_PCIE_ENV_INIT TRUE |
| 338 | #endif |
| 339 | #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 340 | OPTION_GNB_FEATURE PcieInitAtEnv; |
| 341 | #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv}, |
| 342 | #else |
| 343 | #define OPTION_PCIEINITATENV_ENTRY |
| 344 | #endif |
| 345 | //--------------------------------------------------------------------------------------------------- |
| 346 | |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 347 | CONST OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 348 | OPTION_NBFUSETABLEFEATURE_ENTRY |
| 349 | OPTION_NBINITATENVT_ENTRY |
| 350 | OPTION_PCIEINITATENV_ENTRY |
| 351 | OPTION_GFXCONFIGENVINTERFACE_ENTRY |
| 352 | OPTION_GFXINITATENVPOST_ENTRY |
| 353 | OPTION_F12NBPOWERGATEFEATURE_ENTRY |
| 354 | OPTION_F14NBPOWERGATEFEATURE_ENTRY |
| 355 | OPTION_KRNBPOWERGATEFEATURE_ENTRY |
| 356 | {0, NULL} |
| 357 | }; |
| 358 | #endif |
| 359 | |
| 360 | #if (AGESA_ENTRY_INIT_MID == TRUE) |
| 361 | //--------------------------------------------------------------------------------------------------- |
| 362 | #ifndef OPTOIN_GNB_CABLESAFE |
| 363 | #define OPTOIN_GNB_CABLESAFE TRUE |
| 364 | #endif |
| 365 | #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) |
| 366 | OPTION_GNB_FEATURE GnbCableSafeEntry; |
| 367 | #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, |
| 368 | #else |
| 369 | #define OPTION_GNBCABLESAFEENTRY_ENTRY |
| 370 | #endif |
| 371 | //--------------------------------------------------------------------------------------------------- |
| 372 | #ifndef OPTOIN_NB_LCLK_NCLK_RATIO |
| 373 | #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE |
| 374 | #endif |
| 375 | #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) |
| 376 | OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; |
| 377 | #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, |
| 378 | #else |
| 379 | #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY |
| 380 | #endif |
| 381 | #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_KR == TRUE) |
| 382 | OPTION_GNB_FEATURE KRNbLclkNclkRatioFeature; |
| 383 | #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_KR, KRNbLclkNclkRatioFeature}, |
| 384 | #else |
| 385 | #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY |
| 386 | #endif |
| 387 | //--------------------------------------------------------------------------------------------------- |
| 388 | #ifndef OPTION_NB_LCLK_DPM_INIT |
| 389 | #define OPTION_NB_LCLK_DPM_INIT TRUE |
| 390 | #endif |
| 391 | #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 392 | OPTION_GNB_FEATURE NbLclkDpmFeature; |
| 393 | #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature}, |
| 394 | #else |
| 395 | #define OPTION_NBLCLKDPMFEATURE_ENTRY |
| 396 | #endif |
| 397 | //--------------------------------------------------------------------------------------------------- |
| 398 | #ifndef OPTION_PCIE_POWER_GATE |
| 399 | #define OPTION_PCIE_POWER_GATE TRUE |
| 400 | #endif |
| 401 | #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) |
| 402 | OPTION_GNB_FEATURE PciePowerGateFeature; |
| 403 | #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, |
| 404 | #else |
| 405 | #define OPTION_PCIEPOWERGATEFEATURE_ENTRY |
| 406 | #endif |
| 407 | //--------------------------------------------------------------------------------------------------- |
| 408 | #ifndef OPTION_GFX_MID_INIT |
| 409 | #define OPTION_GFX_MID_INIT TRUE |
| 410 | #endif |
| 411 | #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 412 | OPTION_GNB_FEATURE GfxInitAtMidPost; |
| 413 | #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost}, |
| 414 | #else |
| 415 | #define OPTION_GFXINITATMIDPOST_ENTRY |
| 416 | #endif |
| 417 | //--------------------------------------------------------------------------------------------------- |
| 418 | #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT |
| 419 | #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE |
| 420 | #endif |
| 421 | #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 422 | OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; |
| 423 | #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry}, |
| 424 | #else |
| 425 | #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY |
| 426 | #endif |
| 427 | //--------------------------------------------------------------------------------------------------- |
| 428 | #ifndef OPTION_PCIe_MID_INIT |
| 429 | #define OPTION_PCIe_MID_INIT TRUE |
| 430 | #endif |
| 431 | #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 432 | OPTION_GNB_FEATURE PcieInitAtMid; |
| 433 | #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid}, |
| 434 | #else |
| 435 | #define OPTION_PCIEINITATMID_ENTRY |
| 436 | #endif |
| 437 | //--------------------------------------------------------------------------------------------------- |
| 438 | #ifndef OPTION_NB_MID_INIT |
| 439 | #define OPTION_NB_MID_INIT TRUE |
| 440 | #endif |
| 441 | #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 442 | OPTION_GNB_FEATURE NbInitAtLatePost; |
| 443 | #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost}, |
| 444 | #else |
| 445 | #define OPTION_NBINITATLATEPOST_ENTRY |
| 446 | #endif |
| 447 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 448 | CONST OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 449 | OPTION_GFXINITATMIDPOST_ENTRY |
| 450 | OPTION_GFXINTEGRATEDINFOTABLE_ENTRY |
| 451 | OPTION_GNBCABLESAFEENTRY_ENTRY |
| 452 | OPTION_PCIEINITATMID_ENTRY |
| 453 | OPTION_NBINITATLATEPOST_ENTRY |
| 454 | OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY |
| 455 | OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY |
| 456 | OPTION_NBLCLKDPMFEATURE_ENTRY |
| 457 | OPTION_PCIEPOWERGATEFEATURE_ENTRY |
| 458 | {0, NULL} |
| 459 | }; |
| 460 | #endif |
| 461 | |
| 462 | #if (AGESA_ENTRY_INIT_LATE == TRUE) |
| 463 | //--------------------------------------------------------------------------------------------------- |
| 464 | #ifndef OPTION_ALIB |
| 465 | #define OPTION_ALIB FALSE |
| 466 | #endif |
| 467 | #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 468 | OPTION_GNB_FEATURE PcieAlibFeature; |
| 469 | #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature}, |
| 470 | #else |
| 471 | #define OPTION_PCIEALIBFEATURE_ENTRY |
| 472 | #endif |
| 473 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 474 | CONST OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 475 | OPTION_PCIEALIBFEATURE_ENTRY |
| 476 | {0, NULL} |
| 477 | }; |
| 478 | #endif |
| 479 | |
| 480 | #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 481 | S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; |
| 482 | S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; |
| 483 | S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; |
| 484 | #define GNB_S3_DISPATCH_FUNCTION_TABLE \ |
| 485 | {S3DispatchGnbSmuIndirectWrite, NbSmuIndirectWriteS3Script}, \ |
| 486 | {S3DispatchGnbSmuServiceRequest, NbSmuServiceRequestS3Script}, \ |
| 487 | {S3DispatchGnbPcieLateRestore, PcieLateRestoreS3Script}, |
| 488 | #endif |
| 489 | |
| 490 | #endif // _OPTION_GNB_INSTALL_H_ |