Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of all appropriate CPU family specific support. |
| 6 | * |
| 7 | * This file generates the defaults tables for all family specific |
| 8 | * combinations. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: Core |
| 13 | * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $ |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /* Default all CPU Specific Service members to off. They |
| 48 | will be enabled as needed by cross referencing families |
| 49 | with entry points in the family / model install files. */ |
| 50 | #define GET_PSTATE_POWER FALSE |
| 51 | #define GET_PSTATE_FREQ FALSE |
| 52 | #define DISABLE_PSTATE FALSE |
| 53 | #define TRANSITION_PSTATE FALSE |
| 54 | #define PROC_IDD_MAX FALSE |
| 55 | #define GET_TSC_RATE FALSE |
| 56 | #define PSTATE_TRANSITION_LATENCY FALSE |
| 57 | #define GET_PSTATE_REGISTER_INFO FALSE |
| 58 | #define GET_PSTATE_MAX_STATE FALSE |
| 59 | #define SET_PSTATE_LEVELING_REG FALSE |
| 60 | #define GET_NB_FREQ FALSE |
| 61 | #define IS_NBCOF_INIT_NEEDED FALSE |
| 62 | #define AP_INITIAL_LAUNCH FALSE |
| 63 | #define GET_AP_MAILBOX_FROM_HW FALSE |
| 64 | #define SET_AP_CORE_NUMBER FALSE |
| 65 | #define GET_AP_CORE_NUMBER FALSE |
| 66 | #define TRANSFER_AP_CORE_NUMBER FALSE |
| 67 | #define ID_POSITION_INITIAL_APICID FALSE |
| 68 | #define SAVE_FEATURES FALSE |
| 69 | #define WRITE_FEATURES FALSE |
| 70 | #define SET_DOWN_CORE_REG FALSE |
| 71 | #define SET_WARM_RESET_FLAG FALSE |
| 72 | #define GET_WARM_RESET_FLAG FALSE |
| 73 | #define USES_REGISTER_TABLES FALSE |
| 74 | #define BASE_FAMILY_PCI FALSE |
| 75 | #define MODEL_SPECIFIC_PCI FALSE |
| 76 | #define BASE_FAMILY_MSR FALSE |
| 77 | #define MODEL_SPECIFIC_MSR FALSE |
| 78 | #define BRAND_STRING1 FALSE |
| 79 | #define BRAND_STRING2 FALSE |
| 80 | #define BASE_FAMILY_HT_PCI FALSE |
| 81 | #define MODEL_SPECIFIC_HT_PCI FALSE |
| 82 | #define BASE_FAMILY_WORKAROUNDS FALSE |
| 83 | #define GET_PATCHES FALSE |
| 84 | #define GET_PATCHES_EQUIVALENCE_TABLE FALSE |
| 85 | #define GET_CACHE_INFO FALSE |
| 86 | #define GET_SYSTEM_PM_TABLE FALSE |
| 87 | #define GET_WHEA_INIT FALSE |
| 88 | #define GET_CFOH_REG FALSE |
| 89 | #define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE |
| 90 | #define IS_NB_PSTATE_ENABLED FALSE |
| 91 | |
| 92 | /* |
| 93 | * Pull in family specific services based on entry point |
| 94 | */ |
| 95 | #if AGESA_ENTRY_INIT_RESET == TRUE |
| 96 | #undef ID_POSITION_INITIAL_APICID |
| 97 | #define ID_POSITION_INITIAL_APICID TRUE |
| 98 | #undef GET_AP_MAILBOX_FROM_HW |
| 99 | #define GET_AP_MAILBOX_FROM_HW TRUE |
| 100 | #undef SET_WARM_RESET_FLAG |
| 101 | #define SET_WARM_RESET_FLAG TRUE |
| 102 | #undef GET_WARM_RESET_FLAG |
| 103 | #define GET_WARM_RESET_FLAG TRUE |
| 104 | #undef GET_CACHE_INFO |
| 105 | #define GET_CACHE_INFO TRUE |
| 106 | #undef GET_AP_CORE_NUMBER |
| 107 | #define GET_AP_CORE_NUMBER TRUE |
| 108 | #undef TRANSFER_AP_CORE_NUMBER |
| 109 | #define TRANSFER_AP_CORE_NUMBER TRUE |
| 110 | #endif |
| 111 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 112 | #if AGESA_ENTRY_INIT_EARLY == TRUE |
| 113 | #undef TRANSITION_PSTATE |
| 114 | #define TRANSITION_PSTATE TRUE |
| 115 | #undef DISABLE_PSTATE |
| 116 | #define DISABLE_PSTATE TRUE |
| 117 | #undef PROC_IDD_MAX |
| 118 | #define PROC_IDD_MAX TRUE |
| 119 | #undef GET_TSC_RATE |
| 120 | #define GET_TSC_RATE TRUE |
| 121 | #undef GET_NB_FREQ |
| 122 | #define GET_NB_FREQ TRUE |
| 123 | #undef IS_NBCOF_INIT_NEEDED |
| 124 | #define IS_NBCOF_INIT_NEEDED TRUE |
| 125 | #undef AP_INITIAL_LAUNCH |
| 126 | #define AP_INITIAL_LAUNCH TRUE |
| 127 | #undef GET_AP_MAILBOX_FROM_HW |
| 128 | #define GET_AP_MAILBOX_FROM_HW TRUE |
| 129 | #undef SET_AP_CORE_NUMBER |
| 130 | #define SET_AP_CORE_NUMBER TRUE |
| 131 | #undef GET_AP_CORE_NUMBER |
| 132 | #define GET_AP_CORE_NUMBER TRUE |
| 133 | #undef TRANSFER_AP_CORE_NUMBER |
| 134 | #define TRANSFER_AP_CORE_NUMBER TRUE |
| 135 | #undef ID_POSITION_INITIAL_APICID |
| 136 | #define ID_POSITION_INITIAL_APICID TRUE |
| 137 | #undef SET_DOWN_CORE_REG |
| 138 | #define SET_DOWN_CORE_REG TRUE |
| 139 | #undef SET_WARM_RESET_FLAG |
| 140 | #define SET_WARM_RESET_FLAG TRUE |
| 141 | #undef GET_WARM_RESET_FLAG |
| 142 | #define GET_WARM_RESET_FLAG TRUE |
| 143 | #undef USES_REGISTER_TABLES |
| 144 | #define USES_REGISTER_TABLES TRUE |
| 145 | #undef BASE_FAMILY_PCI |
| 146 | #define BASE_FAMILY_PCI TRUE |
| 147 | #undef MODEL_SPECIFIC_PCI |
| 148 | #define MODEL_SPECIFIC_PCI TRUE |
| 149 | #undef BASE_FAMILY_MSR |
| 150 | #define BASE_FAMILY_MSR TRUE |
| 151 | #undef MODEL_SPECIFIC_MSR |
| 152 | #define MODEL_SPECIFIC_MSR TRUE |
| 153 | #undef BRAND_STRING1 |
| 154 | #define BRAND_STRING1 TRUE |
| 155 | #undef BRAND_STRING2 |
| 156 | #define BRAND_STRING2 TRUE |
| 157 | #undef BASE_FAMILY_HT_PCI |
| 158 | #define BASE_FAMILY_HT_PCI TRUE |
| 159 | #undef MODEL_SPECIFIC_HT_PCI |
| 160 | #define MODEL_SPECIFIC_HT_PCI TRUE |
| 161 | #undef BASE_FAMILY_WORKAROUNDS |
| 162 | #define BASE_FAMILY_WORKAROUNDS TRUE |
| 163 | #undef GET_PATCHES |
| 164 | #define GET_PATCHES TRUE |
| 165 | #undef GET_PATCHES_EQUIVALENCE_TABLE |
| 166 | #define GET_PATCHES_EQUIVALENCE_TABLE TRUE |
| 167 | #undef GET_SYSTEM_PM_TABLE |
| 168 | #define GET_SYSTEM_PM_TABLE TRUE |
| 169 | #undef GET_CACHE_INFO |
| 170 | #define GET_CACHE_INFO TRUE |
| 171 | #undef GET_PLATFORM_TYPE_SPECIFIC_INFO |
| 172 | #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE |
| 173 | #undef IS_NB_PSTATE_ENABLED |
| 174 | #define IS_NB_PSTATE_ENABLED TRUE |
| 175 | #endif |
| 176 | |
| 177 | #if AGESA_ENTRY_INIT_POST == TRUE |
| 178 | #undef ID_POSITION_INITIAL_APICID |
| 179 | #define ID_POSITION_INITIAL_APICID TRUE |
| 180 | #undef GET_PSTATE_POWER |
| 181 | #define GET_PSTATE_POWER TRUE |
| 182 | #undef GET_PSTATE_FREQ |
| 183 | #define GET_PSTATE_FREQ TRUE |
| 184 | #undef TRANSITION_PSTATE |
| 185 | #define TRANSITION_PSTATE TRUE |
| 186 | #undef PROC_IDD_MAX |
| 187 | #define PROC_IDD_MAX TRUE |
| 188 | #undef GET_AP_CORE_NUMBER |
| 189 | #define GET_AP_CORE_NUMBER TRUE |
| 190 | #undef GET_PSTATE_REGISTER_INFO |
| 191 | #define GET_PSTATE_REGISTER_INFO TRUE |
| 192 | #undef GET_PSTATE_MAX_STATE |
| 193 | #define GET_PSTATE_MAX_STATE TRUE |
| 194 | #undef SET_PSTATE_LEVELING_REG |
| 195 | #define SET_PSTATE_LEVELING_REG TRUE |
| 196 | #undef SET_WARM_RESET_FLAG |
| 197 | #define SET_WARM_RESET_FLAG TRUE |
| 198 | #undef GET_WARM_RESET_FLAG |
| 199 | #define GET_WARM_RESET_FLAG TRUE |
| 200 | #undef SAVE_FEATURES |
| 201 | #define SAVE_FEATURES TRUE |
| 202 | #undef WRITE_FEATURES |
| 203 | #define WRITE_FEATURES TRUE |
| 204 | #undef GET_CFOH_REG |
| 205 | #define GET_CFOH_REG TRUE |
| 206 | #undef IS_NB_PSTATE_ENABLED |
| 207 | #define IS_NB_PSTATE_ENABLED TRUE |
| 208 | #endif |
| 209 | |
| 210 | #if AGESA_ENTRY_INIT_ENV == TRUE |
| 211 | #endif |
| 212 | |
| 213 | #if AGESA_ENTRY_INIT_MID == TRUE |
| 214 | #endif |
| 215 | |
| 216 | #if AGESA_ENTRY_INIT_LATE == TRUE |
| 217 | #undef GET_AP_CORE_NUMBER |
| 218 | #define GET_AP_CORE_NUMBER TRUE |
| 219 | #undef GET_PSTATE_FREQ |
| 220 | #define GET_PSTATE_FREQ TRUE |
| 221 | #undef TRANSITION_PSTATE |
| 222 | #define TRANSITION_PSTATE TRUE |
| 223 | #undef PSTATE_TRANSITION_LATENCY |
| 224 | #define PSTATE_TRANSITION_LATENCY TRUE |
| 225 | #undef GET_WHEA_INIT |
| 226 | #define GET_WHEA_INIT TRUE |
| 227 | #undef GET_PLATFORM_TYPE_SPECIFIC_INFO |
| 228 | #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE |
| 229 | #undef GET_TSC_RATE |
| 230 | #define GET_TSC_RATE TRUE |
| 231 | #undef BRAND_STRING1 |
| 232 | #define BRAND_STRING1 TRUE |
| 233 | #undef BRAND_STRING2 |
| 234 | #define BRAND_STRING2 TRUE |
| 235 | #endif |
| 236 | |
| 237 | #if AGESA_ENTRY_INIT_S3SAVE == TRUE |
| 238 | #endif |
| 239 | |
| 240 | #if AGESA_ENTRY_INIT_RESUME == TRUE |
| 241 | #undef GET_CFOH_REG |
| 242 | #define GET_CFOH_REG TRUE |
| 243 | #endif |
| 244 | |
| 245 | #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE |
| 246 | #endif |
| 247 | |
| 248 | #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE |
| 249 | #undef ID_POSITION_INITIAL_APICID |
| 250 | #define ID_POSITION_INITIAL_APICID TRUE |
| 251 | #endif |
| 252 | |
| 253 | /* |
| 254 | * Initialize PCI MMIO mask to 0 |
| 255 | */ |
| 256 | #define FAMILY_MMIO_BASE_MASK (0ull) |
| 257 | |
| 258 | |
| 259 | /* |
| 260 | * Initialize all families to disabled |
| 261 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 262 | #define OPT_F14_TABLE |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 263 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 264 | #define OPT_F14_ID_TABLE |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 265 | |
| 266 | |
| 267 | /* |
| 268 | * Install family specific support |
| 269 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 270 | |
| 271 | #if (OPTION_FAMILY14H == TRUE) |
| 272 | #include "OptionFamily14hInstall.h" |
| 273 | #endif |
| 274 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 275 | /* |
| 276 | * Process PCI MMIO mask |
| 277 | */ |
| 278 | |
| 279 | // If size is 0, but base is not, break the build. |
| 280 | #if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) |
| 281 | #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 |
| 282 | #endif |
| 283 | |
| 284 | // If base is 0, but size is not, break the build. |
| 285 | #if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) |
| 286 | #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater |
| 287 | #endif |
| 288 | |
| 289 | #if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) |
| 290 | // Both are non-zero, begin further processing. |
| 291 | |
| 292 | // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. |
| 293 | #if (CFG_PCI_MMIO_BASE < 0x800000) |
| 294 | #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater |
| 295 | #endif |
| 296 | |
| 297 | // Break the build if the address is too high for the enabled families. |
| 298 | #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) |
| 299 | #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families |
| 300 | #endif |
| 301 | |
| 302 | // If the size parameter is not valid, break the build. |
| 303 | #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) |
| 304 | #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) |
| 305 | #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 |
| 306 | #endif |
| 307 | #endif |
| 308 | |
| 309 | #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) |
| 310 | // If the base is not aligned according to size, break the build. |
| 311 | #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) |
| 312 | #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size |
| 313 | #endif |
| 314 | #undef PCI_MMIO_ALIGNMENT |
| 315 | #endif |
| 316 | |
| 317 | /* |
| 318 | * Process sockets / modules |
| 319 | */ |
| 320 | #ifndef ADVCFG_PLATFORM_SOCKETS |
| 321 | #error BLDOPT Set Family supported sockets. |
| 322 | #endif |
| 323 | #ifndef ADVCFG_PLATFORM_MODULES |
| 324 | #error BLDOPT Set Family supported modules. |
| 325 | #endif |
| 326 | |
| 327 | CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = |
| 328 | { |
| 329 | ADVCFG_PLATFORM_SOCKETS, |
| 330 | ADVCFG_PLATFORM_MODULES |
| 331 | }; |
| 332 | |
| 333 | /* |
| 334 | * Instantiate global data needed for processor identification |
| 335 | */ |
| 336 | CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] = |
| 337 | { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 338 | OPT_F14_TABLE |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 339 | }; |
| 340 | |
| 341 | CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable = |
| 342 | { |
| 343 | (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), |
| 344 | &CpuSupportedFamiliesArray[0] |
| 345 | }; |
| 346 | |
| 347 | |
| 348 | CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = |
| 349 | { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 350 | OPT_F14_ID_TABLE |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 351 | }; |
| 352 | |
| 353 | CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = |
| 354 | { |
| 355 | (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), |
| 356 | CpuSupportedFamilyIdArray |
| 357 | }; |