blob: b2dfe129710fb18bf5f5aecbb0a2a2c31ffdb4cf [file] [log] [blame]
Sean Rhodesecda7752022-07-04 14:18:52 +01001config BOARD_STARLABS_STARBOOK_SERIES
Sean Rhodes17441a32021-07-05 16:03:15 +01002 def_bool n
3 select DRIVERS_I2C_HID
4 select EC_STARLABS_ITE
5 select EC_STARLABS_FAN
6 select HAVE_ACPI_RESUME
7 select HAVE_ACPI_TABLES
8 select HAVE_CMOS_DEFAULT
9 select HAVE_OPTION_TABLE
10 select INTEL_GMA_HAVE_VBT
Sean Rhodes12636222022-11-07 22:04:52 +000011 select INTEL_LPSS_UART_FOR_CONSOLE
Elyes Haouasdf4fa452023-01-25 08:54:11 +010012 select MAINBOARD_HAS_TPM2
Sean Rhodes6bfca1b2023-02-06 09:23:47 +000013 select NO_S0IX_SUPPORT
Sean Rhodes17441a32021-07-05 16:03:15 +010014 select NO_UART_ON_SUPERIO
15 select SOC_INTEL_COMMON_BLOCK_HDA_VERB
16 select SYSTEM_TYPE_LAPTOP
17
Sean Rhodesab5b7b32021-10-22 14:33:27 +010018config BOARD_STARLABS_LABTOP_KBL
19 select BOARD_ROMSIZE_KB_8192
Sean Rhodesecda7752022-07-04 14:18:52 +010020 select BOARD_STARLABS_STARBOOK_SERIES
Sean Rhodesca22e6c2022-08-01 21:07:12 +010021 select CRB_TPM
Sean Rhodesab5b7b32021-10-22 14:33:27 +010022 select HAVE_INTEL_PTT
23 select HAVE_SPD_IN_CBFS
24 select MAINBOARD_HAS_LIBGFXINIT
25 select SOC_INTEL_KABYLAKE
26 select SPI_FLASH_GIGADEVICE
27
Sean Rhodese96ade62021-10-18 21:07:20 +010028config BOARD_STARLABS_LABTOP_CML
29 select BOARD_ROMSIZE_KB_16384
Sean Rhodesecda7752022-07-04 14:18:52 +010030 select BOARD_STARLABS_STARBOOK_SERIES
Sean Rhodesb608db92022-05-06 10:03:41 +010031 select EC_STARLABS_MAX_CHARGE
Sean Rhodese96ade62021-10-18 21:07:20 +010032 select EC_STARLABS_NEED_ITE_BIN
33 select HAVE_INTEL_PTT
34 select HAVE_SPD_IN_CBFS
Jes B. Klinkec6b041a12022-04-19 14:00:33 -070035 select CRB_TPM
Sean Rhodese96ade62021-10-18 21:07:20 +010036 select MAINBOARD_HAS_LIBGFXINIT
Sean Rhodese96ade62021-10-18 21:07:20 +010037 select SOC_INTEL_COMETLAKE_1
38 select SPI_FLASH_WINBOND
39
Sean Rhodes17441a32021-07-05 16:03:15 +010040config BOARD_STARLABS_STARBOOK_TGL
41 select BOARD_ROMSIZE_KB_16384
Sean Rhodesecda7752022-07-04 14:18:52 +010042 select BOARD_STARLABS_STARBOOK_SERIES
Sean Rhodesdc522d22022-10-03 11:19:52 +010043 select DRIVERS_INTEL_PMC
Sean Rhodes17441a32021-07-05 16:03:15 +010044 select DRIVERS_INTEL_USB4_RETIMER
45 select EC_STARLABS_KBL_LEVELS
Sean Rhodes4d1bf7b2022-02-17 13:55:34 +000046 select EC_STARLABS_MAX_CHARGE
Sean Rhodes17441a32021-07-05 16:03:15 +010047 select EC_STARLABS_NEED_ITE_BIN
Jes B. Klinkec6b041a12022-04-19 14:00:33 -070048 select MEMORY_MAPPED_TPM
Sean Rhodes17441a32021-07-05 16:03:15 +010049 select SOC_INTEL_COMMON_BLOCK_TCSS
50 select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
51 select SOC_INTEL_TIGERLAKE
Sean Rhodes17441a32021-07-05 16:03:15 +010052 select SPI_FLASH_WINBOND
Sean Rhodesf26d76b2022-07-31 20:16:21 +010053 select TPM_MEASURED_BOOT
Sean Rhodes17441a32021-07-05 16:03:15 +010054
Ben-StarLabsb2db3652022-07-12 12:43:27 +010055config BOARD_STARLABS_STARBOOK_ADL
56 select BOARD_ROMSIZE_KB_32768
57 select BOARD_STARLABS_STARBOOK_SERIES
58 select DRIVERS_INTEL_PMC
59 select EC_STARLABS_KBL_LEVELS
60 select EC_STARLABS_MAX_CHARGE
Ben-StarLabsb2db3652022-07-12 12:43:27 +010061 select EC_STARLABS_NEED_ITE_BIN
62 select MEMORY_MAPPED_TPM
Ben-StarLabsb2db3652022-07-12 12:43:27 +010063 select SOC_INTEL_ALDERLAKE
64 select SOC_INTEL_ALDERLAKE_PCH_P
Ben-StarLabsb2db3652022-07-12 12:43:27 +010065 select SPI_FLASH_WINBOND
66 select TPM_MEASURED_BOOT
67 select PCIEXP_SUPPORT_RESIZABLE_BARS
68
Sean Rhodesecda7752022-07-04 14:18:52 +010069if BOARD_STARLABS_STARBOOK_SERIES
Sean Rhodes17441a32021-07-05 16:03:15 +010070
Sean Rhodes2eb2dce2022-05-26 20:56:14 +010071config CCD_PORT
72 int
73 default 6 if BOARD_STARLABS_LABTOP_CML
Ben-StarLabsb2db3652022-07-12 12:43:27 +010074 default 4 if BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes2eb2dce2022-05-26 20:56:14 +010075 default 3
76
Sean Rhodes976ca5e2022-07-31 07:55:37 +010077config CMOS_DEFAULT_FILE
78 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default" if BOARD_STARLABS_STARBOOK_TGL
79
80config CMOS_LAYOUT_FILE
81 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout" if BOARD_STARLABS_STARBOOK_TGL
82
Sean Rhodes12636222022-11-07 22:04:52 +000083config CONSOLE_SERIAL
84 default n if !EDK2_DEBUG
85
Sean Rhodes17441a32021-07-05 16:03:15 +010086config DEVICETREE
87 default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
88
Sean Rhodesab5b7b32021-10-22 14:33:27 +010089config DIMM_SPD_SIZE
Ben-StarLabsb2db3652022-07-12 12:43:27 +010090 default 512
Sean Rhodesab5b7b32021-10-22 14:33:27 +010091
Sean Rhodes17441a32021-07-05 16:03:15 +010092config DRIVER_TPM_SPI_CHIP
93 default 2
94
Sean Rhodes58f6a5d2021-12-19 21:22:15 +000095config EC_GPE_SCI
Ben-StarLabsb2db3652022-07-12 12:43:27 +010096 default 0x6e if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes58f6a5d2021-12-19 21:22:15 +000097 default 0x50
98
Sean Rhodes17441a32021-07-05 16:03:15 +010099config EC_STARLABS_ADD_ITE_BIN
100 default y
101
102config EC_STARLABS_ITE_BIN_PATH
103 string
104 depends on EC_STARLABS_NEED_ITE_BIN
Sean Rhodesecda7752022-07-04 14:18:52 +0100105 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
Sean Rhodes17441a32021-07-05 16:03:15 +0100106
107config EC_VARIANT_DIR
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100108 default "kbl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_KBL
Sean Rhodese96ade62021-10-18 21:07:20 +0100109 default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML
110 default "tgl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_TGL
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100111 default "adl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes17441a32021-07-05 16:03:15 +0100112
113config FMDFILE
114 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
115
116config IFD_BIN_PATH
117 string
118 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
119
120config MAINBOARD_DIR
Sean Rhodesecda7752022-07-04 14:18:52 +0100121 default "starlabs/starbook"
Sean Rhodes17441a32021-07-05 16:03:15 +0100122
123config MAINBOARD_FAMILY
124 string
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100125 default "L3" if BOARD_STARLABS_LABTOP_KBL
Sean Rhodese96ade62021-10-18 21:07:20 +0100126 default "L4" if BOARD_STARLABS_LABTOP_CML
127 default "B5" if BOARD_STARLABS_STARBOOK_TGL
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100128 default "B6-I" if BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes17441a32021-07-05 16:03:15 +0100129
130config MAINBOARD_PART_NUMBER
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100131 default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL
Sean Rhodese96ade62021-10-18 21:07:20 +0100132 default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML
133 default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100134 default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes17441a32021-07-05 16:03:15 +0100135
136config MAINBOARD_SMBIOS_PRODUCT_NAME
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100137 default "StarBook" if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL
Sean Rhodese96ade62021-10-18 21:07:20 +0100138 default "LabTop"
Sean Rhodes17441a32021-07-05 16:03:15 +0100139
140config ME_BIN_PATH
141 string
142 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
143
Sean Rhodes38c99b52022-07-13 10:11:44 +0100144config EDK2_BOOTSPLASH_FILE
Sean Rhodes17441a32021-07-05 16:03:15 +0100145 string
Sean Rhodes17441a32021-07-05 16:03:15 +0100146 default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
147
Sean Rhodesdb8ef012023-03-27 10:59:02 +0100148config PCIEXP_ASPM
149 bool
150 default n
151 help
152 FSP is already taking care of ASPM, which is configured through the devicetree in coreboot
153 on Alderlake Platforms. Disable it to save some boot time.
154
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100155config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
156 default 32
157
Sean Rhodesdb8ef012023-03-27 10:59:02 +0100158config PCIEXP_L1_SUB_STATE
159 bool
160 default n
161 help
162 Enabling PCIe L1 sub states is already done in FSP.
163 Disable it to save some boot time.
164
165config PCIEXP_CLK_PM
166 bool
167 default n
168 help
169 Enabling PCIe clock power management is already done in FSP.
170 Disable it to save some boot time
171
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100172config SOC_INTEL_CSE_SEND_EOP_EARLY
173 default n if BOARD_STARLABS_STARBOOK_ADL
174
Sean Rhodes17441a32021-07-05 16:03:15 +0100175config UART_FOR_CONSOLE
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100176 default 0 if BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes17441a32021-07-05 16:03:15 +0100177 default 2
178
179config USE_PM_ACPI_TIMER
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100180 default n if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes17441a32021-07-05 16:03:15 +0100181
182config VARIANT_DIR
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100183 default "kbl" if BOARD_STARLABS_LABTOP_KBL
Sean Rhodese96ade62021-10-18 21:07:20 +0100184 default "cml" if BOARD_STARLABS_LABTOP_CML
185 default "tgl" if BOARD_STARLABS_STARBOOK_TGL
Ben-StarLabsb2db3652022-07-12 12:43:27 +0100186 default "adl" if BOARD_STARLABS_STARBOOK_ADL
Sean Rhodes17441a32021-07-05 16:03:15 +0100187
188endif