Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * Copyright (C) 2017 Alexander Couzens <lynxis@fe80.eu> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <string.h> |
| 21 | #include <lib.h> |
| 22 | #include <timestamp.h> |
| 23 | #include <arch/byteorder.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <device/pnp_def.h> |
| 27 | #include <cpu/x86/lapic.h> |
| 28 | #include <pc80/mc146818rtc.h> |
| 29 | #include <arch/acpi.h> |
| 30 | #include <cbmem.h> |
| 31 | #include <console/console.h> |
| 32 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 33 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 34 | #include <southbridge/intel/bd82x6x/pch.h> |
| 35 | #include <southbridge/intel/common/gpio.h> |
| 36 | #include <arch/cpu.h> |
| 37 | #include <cpu/x86/msr.h> |
| 38 | #include <cbfs.h> |
| 39 | |
| 40 | void pch_enable_lpc(void) |
| 41 | { |
| 42 | /* X230 EC Decode Range Port60/64, Port62/66 */ |
| 43 | /* Enable EC, PS/2 Keyboard/Mouse */ |
| 44 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 45 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| 46 | COMA_LPC_EN); |
| 47 | |
| 48 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); |
| 49 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); |
| 50 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); |
| 51 | |
| 52 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 53 | |
| 54 | pci_write_config32(PCH_LPC_DEV, 0xac, |
| 55 | 0x80010000); |
| 56 | } |
| 57 | |
| 58 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 59 | /* enabled, current, OC pin */ |
| 60 | { 0, 3, 0 }, /* P00 disconnected */ |
| 61 | { 1, 1, 1 }, /* P01 left or right */ |
| 62 | { 0, 1, 3 }, /* P02 disconnected */ |
| 63 | { 1, 3, -1 },/* P03 WWAN */ |
| 64 | { 0, 1, 2 }, /* P04 disconnected */ |
| 65 | { 0, 1, -1 },/* P05 disconnected */ |
| 66 | { 0, 1, -1 },/* P06 disconnected */ |
| 67 | { 0, 2, -1 },/* P07 disconnected */ |
| 68 | { 0, 1, -1 },/* P08 disconnected */ |
| 69 | { 1, 2, 5 }, /* P09 left or right */ |
| 70 | { 1, 3, -1 },/* P10 FPR */ |
| 71 | { 1, 3, -1 },/* P11 Bluetooth */ |
| 72 | { 1, 1, -1 },/* P12 WLAN */ |
| 73 | { 1, 1, -1 },/* P13 Camera */ |
| 74 | }; |
| 75 | |
| 76 | static uint8_t *get_spd_data(int spd_index) |
| 77 | { |
| 78 | uint8_t *spd_file; |
| 79 | size_t spd_file_len; |
| 80 | |
| 81 | printk(BIOS_DEBUG, "spd index %d\n", spd_index); |
| 82 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 83 | &spd_file_len); |
| 84 | if (!spd_file) |
| 85 | die("SPD data not found."); |
| 86 | |
| 87 | if (spd_file_len < spd_index * 256) |
| 88 | die("Missing SPD data."); |
| 89 | |
| 90 | return spd_file + spd_index * 256; |
| 91 | } |
| 92 | |
| 93 | void rcba_config(void) |
| 94 | { |
| 95 | } |
| 96 | |
| 97 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 98 | { |
| 99 | uint8_t *memory; |
| 100 | const int spd_gpio_vector[] = {25, 45, -1}; |
| 101 | int spd_index = get_gpios(spd_gpio_vector); |
| 102 | |
| 103 | /* 4gb model = 0, 8gb model = 1 */ |
| 104 | /* int extended_memory_version = get_gpio(44); */ |
| 105 | /* TODO: how do they differ? Guess only one slot is connected */ |
| 106 | |
| 107 | /* |
| 108 | * GPIO45 GPIO25 |
| 109 | * 0 0 elpida |
| 110 | * 0 1 hynix |
| 111 | * 1 0 samsung |
| 112 | * 1 1 reserved |
| 113 | */ |
| 114 | |
| 115 | /* we only support elpida. Because the spd data is missing */ |
| 116 | if (spd_index != 0) |
| 117 | die("Unsupported Memory. Please add your SPD dump to coreboot."); |
| 118 | |
| 119 | memory = get_spd_data(spd_index); |
| 120 | memcpy(&spd[0], memory, 256); |
| 121 | memcpy(&spd[2], memory, 256); |
| 122 | } |
| 123 | |
| 124 | void mainboard_early_init(int s3resume) |
| 125 | { |
| 126 | } |
| 127 | |
| 128 | void mainboard_config_superio(void) |
| 129 | { |
| 130 | } |