blob: 2047a78ea8e128b80e09aa79a93632ffade8ba92 [file] [log] [blame]
Edward O'Callaghan956c2982014-03-16 17:09:58 +11001chip northbridge/intel/sandybridge
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Edward O'Callaghan956c2982014-03-16 17:09:58 +11005
6 # Enable DisplayPort Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "0" # LVDS
11 register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
12 register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
13 register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
Edward O'Callaghan5fcae802014-07-29 14:42:26 +100014 register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
15 register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +020016 register "gfx.use_spread_spectrum_clock" = "1"
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +020017 register "gfx.link_frequency_270_mhz" = "1"
Edward O'Callaghan5fcae802014-07-29 14:42:26 +100018 register "gpu_cpu_backlight" = "0x1155"
19 register "gpu_pch_backlight" = "0x11551155"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110020
Patrick Rudolph7bddd302016-06-11 18:39:35 +020021 # Override fuse bits that hard-code the value to 666 Mhz
22 register "max_mem_clock_mhz" = "933"
23
Edward O'Callaghan956c2982014-03-16 17:09:58 +110024 device cpu_cluster 0 on
25 chip cpu/intel/socket_rPGA989
26 device lapic 0 on end
27 end
28 chip cpu/intel/model_206ax
29 # Magic APIC ID to locate this chip
30 device lapic 0xACAC off end
31
Edward O'Callaghan956c2982014-03-16 17:09:58 +110032 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
33 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
34 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
35
36 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
37 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
38 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
39 end
40 end
41
Patrick Rudolph266a1f72016-06-09 18:13:34 +020042 register "pci_mmio_size" = "2048"
43
Edward O'Callaghan956c2982014-03-16 17:09:58 +110044 device domain 0 on
45 device pci 00.0 on end # host bridge
Edward O'Callaghana8126432014-09-13 06:53:20 +100046 device pci 01.0 on end # PCIe Bridge for discrete graphics
Edward O'Callaghan956c2982014-03-16 17:09:58 +110047 device pci 02.0 on end # vga controller
48
49 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Edward O'Callaghan956c2982014-03-16 17:09:58 +110050 # GPI routing
51 # 0 No effect (default)
52 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
53 # 2 SCI (if corresponding GPIO_EN bit is also set)
54 register "alt_gp_smi_en" = "0x0000"
55 register "gpi1_routing" = "2"
Nicolas Reineckeb0922f02015-02-01 02:53:35 +010056 register "gpi13_routing" = "2"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110057
Edward O'Callaghancf6f9b92014-09-13 06:06:05 +100058 # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
59 register "sata_port_map" = "0x3f"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110060 # Set max SATA speed to 6.0 Gb/s
61 register "sata_interface_speed_support" = "0x3"
62
63 register "gen1_dec" = "0x7c1601"
64 register "gen2_dec" = "0x0c15e1"
65 register "gen4_dec" = "0x0c06a1"
66
67 # Enable zero-based linear PCIe root port functions
68 register "pcie_port_coalesce" = "1"
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020069 register "c2_latency" = "101" # c2 not supported
70 register "p_cnt_throttling_supported" = "1"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110071
Vladimir Serbinenko36fa5b82014-10-28 23:43:20 +010072 register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
73
Nicolas Reineckebcff3bd2015-03-31 01:40:46 +020074 register "xhci_switchable_ports" = "0xf"
75 register "superspeed_capable_ports" = "0xf"
76 register "xhci_overcurrent_mapping" = "0x4000201"
77
Patrick Rudolphc670a412017-04-28 17:28:32 +020078 register "spi_uvscc" = "0x2005"
79 register "spi_lvscc" = "0x2005"
80
Edward O'Callaghan956c2982014-03-16 17:09:58 +110081 device pci 14.0 on end # USB 3.0 Controller
82 device pci 16.0 on end # Management Engine Interface 1
83 device pci 16.1 off end # Management Engine Interface 2
84 device pci 16.2 off end # Management Engine IDE-R
85 device pci 16.3 off end # Management Engine KT
86 device pci 19.0 on end # Intel Gigabit Ethernet
87 device pci 1a.0 on end # USB2 EHCI #2
88 device pci 1b.0 on end # High Definition Audio
89 device pci 1c.0 on end # PCIe Port #1
90 device pci 1c.1 on end # PCIe Port #2
91 device pci 1c.2 on end # PCIe Port #3 (expresscard)
92 device pci 1c.3 off end # PCIe Port #4
93 device pci 1c.4 off end # PCIe Port #5
94 device pci 1c.5 off end # PCIe Port #6
95 device pci 1c.6 off end # PCIe Port #7
96 device pci 1c.7 off end # PCIe Port #8
97 device pci 1d.0 on end # USB2 EHCI #1
98 device pci 1e.0 off end # PCI bridge
99 device pci 1f.0 on #LPC bridge
100 chip ec/lenovo/pmh7
101 device pnp ff.1 on # dummy
102 end
103 register "backlight_enable" = "0x01"
104 register "dock_event_enable" = "0x01"
105 end
106
Philipp Deppenwiese3d02b9c2015-06-03 23:09:36 +0200107 chip drivers/pc80/tpm
108 device pnp 0c31.0 on end
109 end
110
Edward O'Callaghan956c2982014-03-16 17:09:58 +1100111 chip ec/lenovo/h8
112 device pnp ff.2 on # dummy
113 io 0x60 = 0x62
114 io 0x62 = 0x66
115 io 0x64 = 0x1600
116 io 0x66 = 0x1604
117 end
118
Edward O'Callaghanfe365ac2014-03-16 17:24:18 +1100119 register "config0" = "0xa7"
Edward O'Callaghan956c2982014-03-16 17:09:58 +1100120 register "config1" = "0x09"
121 register "config2" = "0xa0"
Edward O'Callaghanfe365ac2014-03-16 17:24:18 +1100122 register "config3" = "0xc2"
Edward O'Callaghan956c2982014-03-16 17:09:58 +1100123
124 register "has_keyboard_backlight" = "1"
125
126 register "beepmask0" = "0x00"
127 register "beepmask1" = "0x86"
128 register "has_power_management_beeps" = "0"
129 register "event2_enable" = "0xff"
130 register "event3_enable" = "0xff"
131 register "event4_enable" = "0xd0"
132 register "event5_enable" = "0xfc"
133 register "event6_enable" = "0x00"
134 register "event7_enable" = "0x01"
135 register "event8_enable" = "0x7b"
136 register "event9_enable" = "0xff"
137 register "eventa_enable" = "0x01"
138 register "eventb_enable" = "0x00"
139 register "eventc_enable" = "0xff"
140 register "eventd_enable" = "0xff"
141 register "evente_enable" = "0x0d"
142 end
143 end # LPC bridge
144 device pci 1f.2 on end # SATA Controller 1
145 device pci 1f.3 on
146 # eeprom, 8 virtual devices, same chip
147 chip drivers/i2c/at24rf08c
148 device i2c 54 on end
149 device i2c 55 on end
150 device i2c 56 on end
151 device i2c 57 on end
152 device i2c 5c on end
153 device i2c 5d on end
154 device i2c 5e on end
155 device i2c 5f on end
156 end
157 end # SMBus
158 device pci 1f.5 off end # SATA Controller 2
159 device pci 1f.6 on end # Thermal
160 end
161 end
162end