blob: 43d8264e3d75d39462581ce8eb7280cc22c2b9a8 [file] [log] [blame]
Edward O'Callaghan956c2982014-03-16 17:09:58 +11001chip northbridge/intel/sandybridge
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Edward O'Callaghan956c2982014-03-16 17:09:58 +11005
6 # Enable DisplayPort Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "0" # LVDS
11 register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
12 register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
13 register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
Edward O'Callaghan5fcae802014-07-29 14:42:26 +100014 register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
15 register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +020016 register "gfx.use_spread_spectrum_clock" = "1"
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +020017 register "gfx.link_frequency_270_mhz" = "1"
Edward O'Callaghan5fcae802014-07-29 14:42:26 +100018 register "gpu_cpu_backlight" = "0x1155"
19 register "gpu_pch_backlight" = "0x11551155"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110020
21 device cpu_cluster 0 on
22 chip cpu/intel/socket_rPGA989
23 device lapic 0 on end
24 end
25 chip cpu/intel/model_206ax
26 # Magic APIC ID to locate this chip
27 device lapic 0xACAC off end
28
Edward O'Callaghan956c2982014-03-16 17:09:58 +110029 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
30 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
31 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
32
33 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
34 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
35 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
36 end
37 end
38
Patrick Rudolph266a1f72016-06-09 18:13:34 +020039 register "pci_mmio_size" = "2048"
40
Edward O'Callaghan956c2982014-03-16 17:09:58 +110041 device domain 0 on
42 device pci 00.0 on end # host bridge
Edward O'Callaghana8126432014-09-13 06:53:20 +100043 device pci 01.0 on end # PCIe Bridge for discrete graphics
Edward O'Callaghan956c2982014-03-16 17:09:58 +110044 device pci 02.0 on end # vga controller
45
46 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Edward O'Callaghan956c2982014-03-16 17:09:58 +110047 # GPI routing
48 # 0 No effect (default)
49 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
50 # 2 SCI (if corresponding GPIO_EN bit is also set)
51 register "alt_gp_smi_en" = "0x0000"
52 register "gpi1_routing" = "2"
Nicolas Reineckeb0922f02015-02-01 02:53:35 +010053 register "gpi13_routing" = "2"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110054
Edward O'Callaghancf6f9b92014-09-13 06:06:05 +100055 # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
56 register "sata_port_map" = "0x3f"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110057 # Set max SATA speed to 6.0 Gb/s
58 register "sata_interface_speed_support" = "0x3"
59
60 register "gen1_dec" = "0x7c1601"
61 register "gen2_dec" = "0x0c15e1"
62 register "gen4_dec" = "0x0c06a1"
63
64 # Enable zero-based linear PCIe root port functions
65 register "pcie_port_coalesce" = "1"
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020066 register "c2_latency" = "101" # c2 not supported
67 register "p_cnt_throttling_supported" = "1"
Edward O'Callaghan956c2982014-03-16 17:09:58 +110068
Vladimir Serbinenko36fa5b82014-10-28 23:43:20 +010069 register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
70
Nicolas Reineckebcff3bd2015-03-31 01:40:46 +020071 register "xhci_switchable_ports" = "0xf"
72 register "superspeed_capable_ports" = "0xf"
73 register "xhci_overcurrent_mapping" = "0x4000201"
74
Edward O'Callaghan956c2982014-03-16 17:09:58 +110075 device pci 14.0 on end # USB 3.0 Controller
76 device pci 16.0 on end # Management Engine Interface 1
77 device pci 16.1 off end # Management Engine Interface 2
78 device pci 16.2 off end # Management Engine IDE-R
79 device pci 16.3 off end # Management Engine KT
80 device pci 19.0 on end # Intel Gigabit Ethernet
81 device pci 1a.0 on end # USB2 EHCI #2
82 device pci 1b.0 on end # High Definition Audio
83 device pci 1c.0 on end # PCIe Port #1
84 device pci 1c.1 on end # PCIe Port #2
85 device pci 1c.2 on end # PCIe Port #3 (expresscard)
86 device pci 1c.3 off end # PCIe Port #4
87 device pci 1c.4 off end # PCIe Port #5
88 device pci 1c.5 off end # PCIe Port #6
89 device pci 1c.6 off end # PCIe Port #7
90 device pci 1c.7 off end # PCIe Port #8
91 device pci 1d.0 on end # USB2 EHCI #1
92 device pci 1e.0 off end # PCI bridge
93 device pci 1f.0 on #LPC bridge
94 chip ec/lenovo/pmh7
95 device pnp ff.1 on # dummy
96 end
97 register "backlight_enable" = "0x01"
98 register "dock_event_enable" = "0x01"
99 end
100
Philipp Deppenwiese3d02b9c2015-06-03 23:09:36 +0200101 chip drivers/pc80/tpm
102 device pnp 0c31.0 on end
103 end
104
Edward O'Callaghan956c2982014-03-16 17:09:58 +1100105 chip ec/lenovo/h8
106 device pnp ff.2 on # dummy
107 io 0x60 = 0x62
108 io 0x62 = 0x66
109 io 0x64 = 0x1600
110 io 0x66 = 0x1604
111 end
112
Edward O'Callaghanfe365ac2014-03-16 17:24:18 +1100113 register "config0" = "0xa7"
Edward O'Callaghan956c2982014-03-16 17:09:58 +1100114 register "config1" = "0x09"
115 register "config2" = "0xa0"
Edward O'Callaghanfe365ac2014-03-16 17:24:18 +1100116 register "config3" = "0xc2"
Edward O'Callaghan956c2982014-03-16 17:09:58 +1100117
118 register "has_keyboard_backlight" = "1"
119
120 register "beepmask0" = "0x00"
121 register "beepmask1" = "0x86"
122 register "has_power_management_beeps" = "0"
123 register "event2_enable" = "0xff"
124 register "event3_enable" = "0xff"
125 register "event4_enable" = "0xd0"
126 register "event5_enable" = "0xfc"
127 register "event6_enable" = "0x00"
128 register "event7_enable" = "0x01"
129 register "event8_enable" = "0x7b"
130 register "event9_enable" = "0xff"
131 register "eventa_enable" = "0x01"
132 register "eventb_enable" = "0x00"
133 register "eventc_enable" = "0xff"
134 register "eventd_enable" = "0xff"
135 register "evente_enable" = "0x0d"
136 end
137 end # LPC bridge
138 device pci 1f.2 on end # SATA Controller 1
139 device pci 1f.3 on
140 # eeprom, 8 virtual devices, same chip
141 chip drivers/i2c/at24rf08c
142 device i2c 54 on end
143 device i2c 55 on end
144 device i2c 56 on end
145 device i2c 57 on end
146 device i2c 5c on end
147 device i2c 5d on end
148 device i2c 5e on end
149 device i2c 5f on end
150 end
151 end # SMBus
152 device pci 1f.5 off end # SATA Controller 2
153 device pci 1f.6 on end # Thermal
154 end
155 end
156end