Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Alderlake support |
| 5 | |
| 6 | if SOC_INTEL_ALDERLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 11 | select ARCH_ALL_STAGES_X86_32 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
| 14 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame^] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 18 | select FSP_M_XIP |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 19 | select GENERIC_GPIO_LIB |
| 20 | select HAVE_FSP_GOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 21 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 22 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 23 | select IDT_IN_EVERY_STAGE |
| 24 | select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | select INTEL_GMA_ACPI |
| 26 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 27 | select IOAPIC |
Subrata Banik | 0aed4e5 | 2020-10-12 17:27:31 +0530 | [diff] [blame] | 28 | select INTEL_TME |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 29 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | select PARALLEL_MP |
| 31 | select PARALLEL_MP_AP_WORK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 32 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 33 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 34 | select FSP_PEIM_TO_PEIM_INTERFACE |
| 35 | select REG_SCRIPT |
| 36 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 37 | select PMC_LOW_POWER_MODE_PROGRAM |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 38 | select SOC_INTEL_COMMON |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 39 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 45 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 46 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 51 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_PCH_BASE |
| 53 | select SOC_INTEL_COMMON_RESET |
| 54 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 55 | select SSE2 |
| 56 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 57 | select TSC_MONOTONIC_TIMER |
| 58 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 59 | select UDK_202005_BINDING |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 60 | select DISPLAY_FSP_VERSION_INFO |
| 61 | select HECI_DISABLE_USING_SMM |
| 62 | |
| 63 | config MAX_CPUS |
| 64 | int |
| 65 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 66 | |
| 67 | config DCACHE_RAM_BASE |
| 68 | default 0xfef00000 |
| 69 | |
| 70 | config DCACHE_RAM_SIZE |
| 71 | default 0x80000 |
| 72 | help |
| 73 | The size of the cache-as-ram region required during bootblock |
| 74 | and/or romstage. |
| 75 | |
| 76 | config DCACHE_BSP_STACK_SIZE |
| 77 | hex |
| 78 | default 0x40400 |
| 79 | help |
| 80 | The amount of anticipated stack usage in CAR by bootblock and |
| 81 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 82 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 83 | (~1KiB). |
| 84 | |
| 85 | config FSP_TEMP_RAM_SIZE |
| 86 | hex |
| 87 | default 0x20000 |
| 88 | help |
| 89 | The amount of anticipated heap usage in CAR by FSP. |
| 90 | Refer to Platform FSP integration guide document to know |
| 91 | the exact FSP requirement for Heap setup. |
| 92 | |
| 93 | config IFD_CHIPSET |
| 94 | string |
| 95 | default "adl" |
| 96 | |
| 97 | config IED_REGION_SIZE |
| 98 | hex |
| 99 | default 0x400000 |
| 100 | |
| 101 | config HEAP_SIZE |
| 102 | hex |
| 103 | default 0x10000 |
| 104 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 105 | config MAX_ROOT_PORTS |
| 106 | int |
| 107 | default 12 |
| 108 | |
| 109 | config MAX_PCIE_CLOCKS |
| 110 | int |
| 111 | default 12 |
| 112 | |
| 113 | config SMM_TSEG_SIZE |
| 114 | hex |
| 115 | default 0x800000 |
| 116 | |
| 117 | config SMM_RESERVED_SIZE |
| 118 | hex |
| 119 | default 0x200000 |
| 120 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 121 | config PCR_BASE_ADDRESS |
| 122 | hex |
| 123 | default 0xfd000000 |
| 124 | help |
| 125 | This option allows you to select MMIO Base Address of sideband bus. |
| 126 | |
| 127 | config MMCONF_BASE_ADDRESS |
| 128 | hex |
| 129 | default 0xc0000000 |
| 130 | |
| 131 | config CPU_BCLK_MHZ |
| 132 | int |
| 133 | default 100 |
| 134 | |
| 135 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 136 | int |
| 137 | default 120 |
| 138 | |
| 139 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 140 | int |
| 141 | default 133 |
| 142 | |
| 143 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 144 | int |
| 145 | default 7 |
| 146 | |
| 147 | config SOC_INTEL_I2C_DEV_MAX |
| 148 | int |
| 149 | default 6 |
| 150 | |
| 151 | config SOC_INTEL_UART_DEV_MAX |
| 152 | int |
| 153 | default 7 |
| 154 | |
| 155 | config CONSOLE_UART_BASE_ADDRESS |
| 156 | hex |
| 157 | default 0xfe032000 |
| 158 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 159 | |
| 160 | # Clock divider parameters for 115200 baud rate |
| 161 | # Baudrate = (UART source clcok * M) /(N *16) |
| 162 | # ADL UART source clock: 120MHz |
| 163 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 164 | hex |
| 165 | default 0x25a |
| 166 | |
| 167 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 168 | hex |
| 169 | default 0x7fff |
| 170 | |
| 171 | config CHROMEOS |
| 172 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 173 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 174 | config VBOOT |
| 175 | select VBOOT_SEPARATE_VERSTAGE |
| 176 | select VBOOT_MUST_REQUEST_DISPLAY |
| 177 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 178 | select VBOOT_VBNV_CMOS |
| 179 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 180 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 181 | config C_ENV_BOOTBLOCK_SIZE |
| 182 | hex |
| 183 | default 0xC000 |
| 184 | |
| 185 | config CBFS_SIZE |
| 186 | hex |
| 187 | default 0x200000 |
| 188 | |
| 189 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 190 | hex |
| 191 | default 0x1400 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 192 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 193 | config FSP_HEADER_PATH |
| 194 | string "Location of FSP headers" |
| 195 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 196 | |
| 197 | config FSP_FD_PATH |
| 198 | string |
| 199 | depends on FSP_USE_REPO |
| 200 | default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 201 | |
| 202 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 203 | int "Debug Consent for ADL" |
| 204 | # USB DBC is more common for developers so make this default to 3 if |
| 205 | # SOC_INTEL_DEBUG_CONSENT=y |
| 206 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 207 | default 0 |
| 208 | help |
| 209 | This is to control debug interface on SOC. |
| 210 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 211 | PlatformDebugConsent in FspmUpd.h has the details. |
| 212 | |
| 213 | Desired platform debug type are |
| 214 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 215 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 216 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 217 | endif |