Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | # Enable Enhanced Intel SpeedStep |
| 3 | register "eist_enable" = "1" |
| 4 | |
| 5 | register "cpu_pl2_4_cfg" = "baseline" |
| 6 | |
| 7 | register "gen1_dec" = "0x00fc0201" |
| 8 | register "gen2_dec" = "0x007c0a01" |
| 9 | register "gen3_dec" = "0x000c03e1" |
| 10 | register "gen4_dec" = "0x001c02e1" |
| 11 | |
| 12 | # GPIO |
| 13 | register "PchUnlockGpioPads" = "1" |
| 14 | register "gpe0_dw0" = "0x2" |
| 15 | register "gpe0_dw1" = "0x3" |
| 16 | register "gpe0_dw2" = "0xd" |
| 17 | |
| 18 | # FSP configuration |
| 19 | register "SaGv" = "SaGv_Enabled" |
| 20 | register "ScsEmmcHs400Enabled" = "1" |
| 21 | |
| 22 | # Enable eDP device |
| 23 | register "DdiPortEdp" = "1" # Display Port |
| 24 | |
| 25 | # Enable HPD for DDI ports B/C |
| 26 | register "DdiPortBHpd" = "1" # HDMI |
| 27 | register "DdiPortCHpd" = "1" # USB Type-C |
| 28 | |
| 29 | # Enable DDC for DDI port B |
| 30 | register "DdiPortBDdc" = "1" # HDMI |
| 31 | |
| 32 | register "PchHdaAudioLinkHda" = "1" |
| 33 | |
| 34 | # Misc |
| 35 | register "AcousticNoiseMitigation" = "1" |
| 36 | |
| 37 | # Power |
| 38 | register "PchPmSlpS3MinAssert" = "3" # 50ms |
| 39 | register "PchPmSlpS4MinAssert" = "1" # 1s |
| 40 | register "PchPmSlpSusMinAssert" = "2" # 500ms |
| 41 | register "PchPmSlpAMinAssert" = "4" # 2s |
| 42 | |
| 43 | register "tcc_offset" = "20" # TCC of 80C |
| 44 | |
| 45 | # Enable SERIRQ continuous |
| 46 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 47 | |
| 48 | register "SkipExtGfxScan" = "1" |
| 49 | |
| 50 | register "enable_c6dram" = "1" |
| 51 | |
| 52 | register "SataPortsEnable[0]" = "1" |
| 53 | register "SataPortsEnable[2]" = "1" |
| 54 | |
| 55 | register "PcieRpEnable[4]" = "1" # LAN1 |
| 56 | register "PcieRpEnable[5]" = "1" # LAN2 |
| 57 | register "PcieRpEnable[6]" = "1" # LAN3 |
| 58 | register "PcieRpEnable[7]" = "1" # LAN4 |
| 59 | register "PcieRpEnable[8]" = "1" # LAN5 |
| 60 | register "PcieRpEnable[9]" = "1" # LAN6 |
| 61 | register "PcieRpEnable[11]" = "1" # M.2 WiFi |
| 62 | register "PcieRpEnable[12]" = "1" # M.2 NVMe x4 |
| 63 | |
| 64 | # Enable Advanced Error Reporting for RP 5-10, 12, 13 |
| 65 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 66 | register "PcieRpAdvancedErrorReporting[5]" = "1" |
| 67 | register "PcieRpAdvancedErrorReporting[6]" = "1" |
| 68 | register "PcieRpAdvancedErrorReporting[7]" = "1" |
| 69 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 70 | register "PcieRpAdvancedErrorReporting[9]" = "1" |
| 71 | register "PcieRpAdvancedErrorReporting[11]" = "1" |
| 72 | register "PcieRpAdvancedErrorReporting[12]" = "1" |
| 73 | |
| 74 | # Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13 |
| 75 | register "PcieRpLtrEnable[4]" = "1" |
| 76 | register "PcieRpLtrEnable[5]" = "1" |
| 77 | register "PcieRpLtrEnable[6]" = "1" |
| 78 | register "PcieRpLtrEnable[7]" = "1" |
| 79 | register "PcieRpLtrEnable[8]" = "1" |
| 80 | register "PcieRpLtrEnable[9]" = "1" |
| 81 | register "PcieRpLtrEnable[11]" = "1" |
| 82 | register "PcieRpLtrEnable[12]" = "1" |
| 83 | |
| 84 | register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" |
| 85 | register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" |
| 86 | register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" |
| 87 | register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" |
| 88 | register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" |
| 89 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" |
| 90 | |
| 91 | # USB related |
| 92 | register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ |
| 93 | USB_PORT_WAKE_ENABLE(2) | \ |
| 94 | USB_PORT_WAKE_ENABLE(3) | \ |
| 95 | USB_PORT_WAKE_ENABLE(4) | \ |
| 96 | USB_PORT_WAKE_ENABLE(5) | \ |
| 97 | USB_PORT_WAKE_ENABLE(6) | \ |
| 98 | USB_PORT_WAKE_ENABLE(7) | \ |
| 99 | USB_PORT_WAKE_ENABLE(8) | \ |
| 100 | USB_PORT_WAKE_ENABLE(9)" |
| 101 | |
| 102 | register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ |
| 103 | USB_PORT_WAKE_ENABLE(2) | \ |
| 104 | USB_PORT_WAKE_ENABLE(3) | \ |
| 105 | USB_PORT_WAKE_ENABLE(4)" |
| 106 | |
| 107 | register "PchUsb2PhySusPgDisable" = "1" |
| 108 | |
| 109 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" |
| 110 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" |
| 111 | register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" |
| 112 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" |
| 113 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" |
| 114 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M2 WiFi |
| 115 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" |
| 116 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" |
| 117 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # 4G/LTE |
| 118 | register "usb2_ports[9]" = "USB2_PORT_EMPTY" |
| 119 | |
| 120 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 121 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 122 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 123 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 124 | register "usb3_ports[4]" = "USB3_PORT_EMPTY" |
| 125 | register "usb3_ports[5]" = "USB3_PORT_EMPTY" |
| 126 | |
| 127 | register "SerialIoDevMode" = "{ |
| 128 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 129 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 130 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 131 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 132 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 133 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 134 | [PchSerialIoIndexSPI0] = PchSerialIoDisabled, |
| 135 | [PchSerialIoIndexSPI1] = PchSerialIoDisabled, |
| 136 | [PchSerialIoIndexSPI2] = PchSerialIoDisabled, |
| 137 | [PchSerialIoIndexUART0] = PchSerialIoDisabled, |
| 138 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 139 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 140 | }" |
| 141 | |
| 142 | device cpu_cluster 0 on end |
| 143 | device domain 0 on |
| 144 | device pci 00.0 on end # Host Bridge |
| 145 | device pci 02.0 on end # Integrated Graphics Device |
| 146 | device pci 04.0 on end # SA Thermal device |
| 147 | device pci 08.0 off end # Gaussian Mixture Model |
| 148 | device pci 12.0 on end # Thermal Subsystem |
| 149 | device pci 12.5 off end # UFS SCS |
| 150 | device pci 12.6 off end # GSPI #2 |
| 151 | device pci 14.0 on end # USB xHCI |
| 152 | device pci 14.1 off end # USB xDCI (OTG) |
| 153 | device pci 14.5 off end # SDCard |
| 154 | device pci 15.0 off end # I2C #0 |
| 155 | device pci 15.1 off end # I2C #1 |
| 156 | device pci 15.2 off end # I2C #2 |
| 157 | device pci 15.3 off end # I2C #3 |
| 158 | device pci 16.0 on end # Management Engine Interface 1 |
| 159 | device pci 16.1 off end # Management Engine Interface 2 |
| 160 | device pci 16.2 off end # Management Engine IDE-R |
| 161 | device pci 16.3 off end # Management Engine KT Redirection |
| 162 | device pci 16.4 off end # Management Engine Interface 3 |
| 163 | device pci 16.5 off end # Management Engine Interface 4 |
| 164 | device pci 17.0 on end # SATA |
| 165 | device pci 19.0 off end # I2C #4 |
| 166 | device pci 19.1 off end # I2C #5 |
| 167 | device pci 19.2 off end # UART #2 |
| 168 | device pci 1a.0 on end # eMMC |
| 169 | device pci 1c.0 off end # PCI Express Port 1 |
| 170 | device pci 1c.1 off end # PCI Express Port 2 |
| 171 | device pci 1c.2 off end # PCI Express Port 3 |
| 172 | device pci 1c.3 off end # PCI Express Port 4 |
| 173 | device pci 1c.4 on end # PCI Express Port 5 LAN1 |
| 174 | device pci 1c.5 on end # PCI Express Port 6 LAN2 |
| 175 | device pci 1c.6 on end # PCI Express Port 7 LAN3 |
| 176 | device pci 1c.7 on end # PCI Express Port 8 LAN4 |
| 177 | device pci 1d.0 on end # PCI Express Port 9 LAN5 |
| 178 | device pci 1d.1 on end # PCI Express Port 10 LAN6 |
| 179 | device pci 1d.2 off end # PCI Express Port 11 |
| 180 | device pci 1d.3 on end # PCI Express Port 12 M.2 WiFi |
| 181 | smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" |
| 182 | "M.2/E 2230 (M2_WIFI2)" "SlotDataBusWidth1X" |
| 183 | device pci 1d.4 on # PCI Express Port 13 NVMe |
| 184 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 185 | "M.2/M 2280 (J1)" "SlotDataBusWidth4X" |
| 186 | end |
| 187 | device pci 1d.5 off end # PCI Express Port 14 |
| 188 | device pci 1d.6 off end # PCI Express Port 15 |
| 189 | device pci 1d.7 off end # PCI Express Port 16 |
| 190 | device pci 1e.0 off end # UART #0 |
| 191 | device pci 1e.1 off end # UART #1 |
| 192 | device pci 1e.2 off end # GSPI #0 |
| 193 | device pci 1e.3 off end # GSPI #1 |
| 194 | device pci 1f.0 on |
Michał Żygowski | d99de5d | 2023-04-03 13:25:17 +0200 | [diff] [blame^] | 195 | chip superio/ite/it8784e |
| 196 | register "TMPIN1.mode" = "THERMAL_RESISTOR" |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 197 | register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" |
Michał Żygowski | d99de5d | 2023-04-03 13:25:17 +0200 | [diff] [blame^] | 198 | register "TMPIN3.mode" = "THERMAL_PECI" |
| 199 | register "TMPIN3.offset" = "0x63" |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 200 | register "ec.vin_mask" = "VIN_ALL" |
| 201 | register "ec.smbus_24mhz" = "1" |
| 202 | register "ec.smbus_en" = "1" |
| 203 | # FAN1 is CPU fan (connector on board) |
| 204 | register "FAN1.mode" = "FAN_SMART_AUTOMATIC" |
Michał Żygowski | d99de5d | 2023-04-03 13:25:17 +0200 | [diff] [blame^] | 205 | register "FAN1.smart.tmpin" = " 3" |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 206 | register "FAN1.smart.tmp_off" = "40" |
| 207 | register "FAN1.smart.tmp_start" = "60" |
| 208 | register "FAN1.smart.tmp_full" = "85" |
| 209 | register "FAN1.smart.tmp_delta" = " 2" |
| 210 | register "FAN1.smart.pwm_start" = "20" |
| 211 | register "FAN1.smart.slope" = "24" |
| 212 | register "FAN2.mode" = "FAN_MODE_OFF" |
| 213 | register "FAN3.mode" = "FAN_MODE_OFF" |
| 214 | device pnp 2e.1 on # COM 1 |
| 215 | io 0x60 = 0x3f8 |
| 216 | irq 0x70 = 4 |
| 217 | end |
Michał Żygowski | d99de5d | 2023-04-03 13:25:17 +0200 | [diff] [blame^] | 218 | device pnp 2e.2 on end # COM 2 |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 219 | device pnp 2e.3 off end # Printer Port |
| 220 | device pnp 2e.4 on # Environment Controller |
| 221 | io 0x60 = 0xa40 |
| 222 | io 0x62 = 0xa30 |
| 223 | irq 0x70 = 9 |
Michał Żygowski | d99de5d | 2023-04-03 13:25:17 +0200 | [diff] [blame^] | 224 | irq 0xf0 = 0x80 # clear 3VSB status |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 225 | end |
| 226 | device pnp 2e.5 off end # Keyboard |
| 227 | device pnp 2e.6 off end # Mouse |
| 228 | device pnp 2e.7 off end # GPIO |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 229 | device pnp 2e.a off end # CIR |
Michał Żygowski | ef886c4 | 2022-09-29 00:58:43 +0200 | [diff] [blame] | 230 | end |
| 231 | chip drivers/pc80/tpm |
| 232 | device pnp 0c31.0 on end |
| 233 | end |
| 234 | end # LPC Interface |
| 235 | device pci 1f.1 hidden end # P2SB |
| 236 | device pci 1f.2 hidden end # Power Management Controller |
| 237 | device pci 1f.3 on end # Intel HDA |
| 238 | device pci 1f.4 on end # SMBus |
| 239 | device pci 1f.5 on end # PCH SPI |
| 240 | device pci 1f.6 off end # GbE |
| 241 | end |
| 242 | end |