| Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-3.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <gpio.h> |
| 6 | |
| 7 | static const struct mb_cfg baseboard_memcfg = { |
| 8 | .type = MEM_TYPE_LP5X, |
| 9 | |
| 10 | .rcomp = { |
| 11 | /* Baseboard uses only 100ohm Rcomp resistors */ |
| 12 | .resistor = 100, |
| 13 | }, |
| 14 | |
| 15 | /* DQ byte map */ |
| 16 | .lpx_dq_map = { |
| 17 | .ddr0 = { |
| 18 | .dq0 = { 7, 1, 2, 0, 3, 6, 5, 4 }, |
| 19 | .dq1 = { 13, 12, 14, 15, 8, 9, 10, 11 }, |
| 20 | }, |
| 21 | .ddr1 = { |
| 22 | .dq0 = { 10, 9, 11, 8, 15, 13, 14, 12 }, |
| 23 | .dq1 = { 6, 0, 7, 4, 3, 1, 2, 5 }, |
| 24 | }, |
| 25 | .ddr2 = { |
| 26 | .dq0 = { 11, 10, 8, 9, 12, 15, 14, 13 }, |
| 27 | .dq1 = { 7, 0, 6, 5, 3, 2, 1, 4 }, |
| 28 | }, |
| 29 | .ddr3 = { |
| 30 | .dq0 = { 13, 10, 8, 9, 14, 11, 15, 12 }, |
| 31 | .dq1 = { 1, 6, 4, 7, 0, 5, 2, 3 }, |
| 32 | }, |
| 33 | .ddr4 = { |
| 34 | .dq0 = { 10, 11, 9, 12, 13, 14, 15, 8 }, |
| 35 | .dq1 = { 6, 7, 4, 5, 1, 0, 3, 2 }, |
| 36 | }, |
| 37 | .ddr5 = { |
| 38 | .dq0 = { 0, 5, 3, 6, 1, 4, 2, 7 }, |
| 39 | .dq1 = { 8, 11, 10, 9, 15, 14, 13, 12 }, |
| 40 | }, |
| 41 | .ddr6 = { |
| 42 | .dq0 = { 1, 3, 0, 2, 6, 5, 7, 4 }, |
| 43 | .dq1 = { 13, 15, 14, 12, 11, 10, 8, 9 }, |
| 44 | }, |
| 45 | .ddr7 = { |
| 46 | .dq0 = { 10, 9, 11, 8, 12, 15, 14, 13 }, |
| 47 | .dq1 = { 6, 4, 7, 5, 2, 1, 0, 3 }, |
| 48 | }, |
| 49 | }, |
| 50 | |
| 51 | /* DQS CPU<>DRAM map */ |
| 52 | .lpx_dqs_map = { |
| 53 | .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, |
| 54 | .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, |
| 55 | .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, |
| 56 | .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, |
| 57 | .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, |
| 58 | .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, |
| 59 | .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, |
| 60 | .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, |
| 61 | }, |
| 62 | |
| 63 | .lp5x_config = { |
| 64 | .ccc_config = 0x66, |
| 65 | }, |
| 66 | |
| 67 | .ect = 1, /* Early Command Training */ |
| 68 | }; |
| 69 | |
| 70 | const struct mb_cfg *__weak variant_memory_params(void) |
| 71 | { |
| 72 | return &baseboard_memcfg; |
| 73 | } |
| 74 | |
| 75 | int __weak variant_memory_sku(void) |
| 76 | { |
| 77 | gpio_t spd_gpios[] = { |
| 78 | GPIO_MEM_CONFIG_0, |
| 79 | GPIO_MEM_CONFIG_1, |
| 80 | GPIO_MEM_CONFIG_2, |
| 81 | GPIO_MEM_CONFIG_3, |
| 82 | }; |
| 83 | |
| 84 | return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); |
| 85 | } |
| 86 | |
| 87 | bool __weak variant_is_half_populated(void) |
| 88 | { |
| 89 | return gpio_get(GPIO_MEM_CH_SEL); |
| 90 | } |
| 91 | |
| 92 | void __weak variant_get_spd_info(struct mem_spd *spd_info) |
| 93 | { |
| 94 | spd_info->topo = MEM_TOPO_MEMORY_DOWN; |
| 95 | spd_info->cbfs_index = variant_memory_sku(); |
| 96 | } |