Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <fsp/util.h> |
| 7 | #include <intelblocks/acpi.h> |
| 8 | #include <intelblocks/cfg.h> |
MAULIK V VAGHELA | ed6f7e4 | 2022-02-22 19:59:42 +0530 | [diff] [blame] | 9 | #include <intelblocks/cse.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 10 | #include <intelblocks/gpio.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 11 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 12 | #include <intelblocks/itss.h> |
| 13 | #include <intelblocks/pcie_rp.h> |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 14 | #include <intelblocks/systemagent.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | #include <intelblocks/xdci.h> |
Michał Żygowski | 9b0f169 | 2022-05-05 13:21:01 +0200 | [diff] [blame] | 16 | #include <soc/hsphy.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <soc/intel/common/vbt.h> |
| 18 | #include <soc/itss.h> |
| 19 | #include <soc/pci_devs.h> |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 20 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <soc/ramstage.h> |
| 22 | #include <soc/soc_chip.h> |
| 23 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | #if CONFIG(HAVE_ACPI_TABLES) |
| 25 | const char *soc_acpi_name(const struct device *dev) |
| 26 | { |
| 27 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 28 | return "PCI0"; |
| 29 | |
| 30 | if (dev->path.type == DEVICE_PATH_USB) { |
| 31 | switch (dev->path.usb.port_type) { |
| 32 | case 0: |
| 33 | /* Root Hub */ |
| 34 | return "RHUB"; |
| 35 | case 2: |
| 36 | /* USB2 ports */ |
| 37 | switch (dev->path.usb.port_id) { |
| 38 | case 0: return "HS01"; |
| 39 | case 1: return "HS02"; |
| 40 | case 2: return "HS03"; |
| 41 | case 3: return "HS04"; |
| 42 | case 4: return "HS05"; |
| 43 | case 5: return "HS06"; |
| 44 | case 6: return "HS07"; |
| 45 | case 7: return "HS08"; |
| 46 | case 8: return "HS09"; |
| 47 | case 9: return "HS10"; |
Michał Żygowski | 3f205a4 | 2022-04-15 18:17:46 +0200 | [diff] [blame] | 48 | case 10: return "HS11"; |
| 49 | case 11: return "HS12"; |
| 50 | case 12: return "HS13"; |
| 51 | case 13: return "HS14"; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 52 | } |
| 53 | break; |
| 54 | case 3: |
| 55 | /* USB3 ports */ |
| 56 | switch (dev->path.usb.port_id) { |
| 57 | case 0: return "SS01"; |
| 58 | case 1: return "SS02"; |
| 59 | case 2: return "SS03"; |
| 60 | case 3: return "SS04"; |
Michał Żygowski | 3f205a4 | 2022-04-15 18:17:46 +0200 | [diff] [blame] | 61 | case 4: return "SS05"; |
| 62 | case 5: return "SS06"; |
| 63 | case 6: return "SS07"; |
| 64 | case 7: return "SS08"; |
| 65 | case 8: return "SS09"; |
| 66 | case 9: return "SS10"; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 67 | } |
| 68 | break; |
| 69 | } |
| 70 | return NULL; |
| 71 | } |
| 72 | if (dev->path.type != DEVICE_PATH_PCI) |
| 73 | return NULL; |
| 74 | |
| 75 | switch (dev->path.pci.devfn) { |
| 76 | case SA_DEVFN_ROOT: return "MCHC"; |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 77 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) |
| 78 | case SA_DEVFN_CPU_PCIE1_0: return "PEG1"; |
| 79 | case SA_DEVFN_CPU_PCIE1_1: return "PEG2"; |
| 80 | case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; |
| 81 | #else |
Tim Wawrzynczak | cf39336 | 2021-12-16 15:01:44 -0700 | [diff] [blame] | 82 | case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; |
| 83 | case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; |
| 84 | case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 85 | #endif |
Wisley Chen | cd80721 | 2021-08-31 18:27:13 +0600 | [diff] [blame] | 86 | case SA_DEVFN_IGD: return "GFX0"; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 87 | case SA_DEVFN_TCSS_XHCI: return "TXHC"; |
| 88 | case SA_DEVFN_TCSS_XDCI: return "TXDC"; |
| 89 | case SA_DEVFN_TCSS_DMA0: return "TDM0"; |
| 90 | case SA_DEVFN_TCSS_DMA1: return "TDM1"; |
| 91 | case SA_DEVFN_TBT0: return "TRP0"; |
| 92 | case SA_DEVFN_TBT1: return "TRP1"; |
| 93 | case SA_DEVFN_TBT2: return "TRP2"; |
| 94 | case SA_DEVFN_TBT3: return "TRP3"; |
| 95 | case SA_DEVFN_IPU: return "IPU0"; |
Tarun Tuli | d8d5228 | 2022-05-03 20:34:32 +0000 | [diff] [blame] | 96 | case SA_DEVFN_DPTF: return "DPTF"; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 97 | case PCH_DEVFN_ISH: return "ISHB"; |
| 98 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 99 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 100 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 101 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 102 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 103 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 104 | case PCH_DEVFN_I2C5: return "I2C5"; |
Varshit B Pandya | 339f0e7 | 2021-07-14 11:08:23 +0530 | [diff] [blame] | 105 | case PCH_DEVFN_I2C6: return "I2C6"; |
| 106 | case PCH_DEVFN_I2C7: return "I2C7"; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 107 | case PCH_DEVFN_SATA: return "SATA"; |
| 108 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 109 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 110 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 111 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 112 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 113 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 114 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 115 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 116 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 117 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 118 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 119 | case PCH_DEVFN_PCIE12: return "RP12"; |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 120 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 121 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 122 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 123 | case PCH_DEVFN_PCIE16: return "RP16"; |
| 124 | case PCH_DEVFN_PCIE17: return "RP17"; |
| 125 | case PCH_DEVFN_PCIE18: return "RP18"; |
| 126 | case PCH_DEVFN_PCIE19: return "RP19"; |
| 127 | case PCH_DEVFN_PCIE20: return "RP20"; |
| 128 | case PCH_DEVFN_PCIE21: return "RP21"; |
| 129 | case PCH_DEVFN_PCIE22: return "RP22"; |
| 130 | case PCH_DEVFN_PCIE23: return "RP23"; |
| 131 | case PCH_DEVFN_PCIE24: return "RP24"; |
| 132 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) |
| 133 | /* Avoid conflicts with PCH-N eMMC */ |
| 134 | case PCH_DEVFN_PCIE25: return "RP25"; |
| 135 | case PCH_DEVFN_PCIE26: return "RP26"; |
| 136 | case PCH_DEVFN_PCIE27: return "RP27"; |
| 137 | case PCH_DEVFN_PCIE28: return "RP28"; |
| 138 | #endif |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 139 | case PCH_DEVFN_PMC: return "PMC"; |
| 140 | case PCH_DEVFN_UART0: return "UAR0"; |
| 141 | case PCH_DEVFN_UART1: return "UAR1"; |
| 142 | case PCH_DEVFN_UART2: return "UAR2"; |
| 143 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 144 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 145 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 146 | case PCH_DEVFN_GSPI3: return "SPI3"; |
| 147 | /* Keeping ACPI device name coherent with ec.asl */ |
| 148 | case PCH_DEVFN_ESPI: return "LPCB"; |
| 149 | case PCH_DEVFN_HDA: return "HDAS"; |
| 150 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 151 | case PCH_DEVFN_GBE: return "GLAN"; |
Tarun Tuli | d8d5228 | 2022-05-03 20:34:32 +0000 | [diff] [blame] | 152 | case PCH_DEVFN_SRAM: return "SRAM"; |
| 153 | case PCH_DEVFN_SPI: return "FSPI"; |
| 154 | case PCH_DEVFN_CSE: return "HEC1"; |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 155 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 156 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 157 | #endif |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | return NULL; |
| 161 | } |
| 162 | #endif |
| 163 | |
| 164 | /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
| 165 | static void soc_fill_gpio_pm_configuration(void) |
| 166 | { |
| 167 | uint8_t value[TOTAL_GPIO_COMM]; |
| 168 | const config_t *config = config_of_soc(); |
| 169 | |
| 170 | if (config->gpio_override_pm) |
Angel Pons | 0c0d492 | 2021-04-05 13:02:45 +0200 | [diff] [blame] | 171 | memcpy(value, config->gpio_pm, sizeof(value)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 172 | else |
Angel Pons | 0c0d492 | 2021-04-05 13:02:45 +0200 | [diff] [blame] | 173 | memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 174 | |
| 175 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 176 | } |
| 177 | |
| 178 | void soc_init_pre_device(void *chip_info) |
| 179 | { |
Michał Żygowski | 9b0f169 | 2022-05-05 13:21:01 +0200 | [diff] [blame] | 180 | /* HSPHY FW needs to be loaded before FSP silicon init */ |
| 181 | load_and_init_hsphy(); |
| 182 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 183 | /* Perform silicon specific init. */ |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 184 | fsp_silicon_init(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 185 | |
| 186 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 187 | fsp_display_fvi_version_hob(); |
| 188 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 189 | soc_fill_gpio_pm_configuration(); |
| 190 | |
| 191 | /* Swap enabled PCI ports in device tree if needed. */ |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 192 | pcie_rp_update_devicetree(get_pch_pcie_rp_table()); |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 193 | |
| 194 | /* Swap enabled TBT root ports in device tree if needed. */ |
| 195 | pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); |
MAULIK V VAGHELA | ed6f7e4 | 2022-02-22 19:59:42 +0530 | [diff] [blame] | 196 | |
| 197 | /* |
| 198 | * Earlier when coreboot used to send EOP at late as possible caused |
| 199 | * issue of delayed response from CSE since CSE was busy loading payload. |
| 200 | * To resolve the issue, EOP should be sent earlier than current sequence |
| 201 | * in the boot sequence at BS_DEV_INIT. |
| 202 | * Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and |
| 203 | * current boot sequence) to reduce message response time from CSE hence moving |
| 204 | * sending EOP to earlier stage. |
| 205 | */ |
| 206 | if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) { |
| 207 | printk(BIOS_INFO, "Sending EOP early from SoC\n"); |
| 208 | cse_send_end_of_post(); |
| 209 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 210 | } |
| 211 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 212 | static void cpu_fill_ssdt(const struct device *dev) |
| 213 | { |
| 214 | if (!generate_pin_irq_map()) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 215 | printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 216 | |
| 217 | generate_cpu_entries(dev); |
| 218 | } |
| 219 | |
| 220 | static void cpu_set_north_irqs(struct device *dev) |
| 221 | { |
| 222 | irq_program_non_pch(); |
| 223 | } |
| 224 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 225 | static struct device_operations pci_domain_ops = { |
| 226 | .read_resources = &pci_domain_read_resources, |
| 227 | .set_resources = &pci_domain_set_resources, |
| 228 | .scan_bus = &pci_domain_scan_bus, |
| 229 | #if CONFIG(HAVE_ACPI_TABLES) |
| 230 | .acpi_name = &soc_acpi_name, |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 231 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 232 | #endif |
| 233 | }; |
| 234 | |
| 235 | static struct device_operations cpu_bus_ops = { |
| 236 | .read_resources = noop_read_resources, |
| 237 | .set_resources = noop_set_resources, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 238 | .enable_resources = cpu_set_north_irqs, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 239 | #if CONFIG(HAVE_ACPI_TABLES) |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 240 | .acpi_fill_ssdt = cpu_fill_ssdt, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 241 | #endif |
| 242 | }; |
| 243 | |
| 244 | static void soc_enable(struct device *dev) |
| 245 | { |
| 246 | /* |
| 247 | * Set the operations if it is a special bus type or a hidden PCI |
| 248 | * device. |
| 249 | */ |
| 250 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 251 | dev->ops = &pci_domain_ops; |
| 252 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 253 | dev->ops = &cpu_bus_ops; |
| 254 | else if (dev->path.type == DEVICE_PATH_PCI && |
| 255 | dev->path.pci.devfn == PCH_DEVFN_PMC) |
| 256 | dev->ops = &pmc_ops; |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 257 | else if (dev->path.type == DEVICE_PATH_GPIO) |
| 258 | block_gpio_enable(dev); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | struct chip_operations soc_intel_alderlake_ops = { |
| 262 | CHIP_NAME("Intel Alderlake") |
| 263 | .enable_dev = &soc_enable, |
| 264 | .init = &soc_init_pre_device, |
| 265 | }; |