soc/intel/alderlake: Add minimal ACPI support for PEG ports
Add minimal Device entries with just an _ADR for each of the PEG ports
for P and M chipsets (N does not have any PEG ports).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index ae28d18..1fa78fb 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -61,6 +61,9 @@
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
+ case SA_DEVFN_CPU_PCIE1_0: return "PEG2";
+ case SA_DEVFN_CPU_PCIE6_0: return "PEG0";
+ case SA_DEVFN_CPU_PCIE6_2: return "PEG1";
case SA_DEVFN_IGD: return "GFX0";
case SA_DEVFN_TCSS_XHCI: return "TXHC";
case SA_DEVFN_TCSS_XDCI: return "TXDC";