Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
| 4 | #include <acpi/acpi_device.h> |
| 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <intelblocks/pmc.h> |
| 11 | #include <intelblocks/pmc_ipc.h> |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
| 13 | #include <soc/iomap.h> |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | |
| 16 | /* |
| 17 | * The "ExternalFacingPort" and "HotPlugSupportInD3" properties are defined at |
| 18 | * https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports |
| 19 | */ |
| 20 | #define PCIE_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" |
| 21 | #define PCIE_EXTERNAL_PORT_PROPERTY "ExternalFacingPort" |
| 22 | |
| 23 | #define PCIE_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" |
| 24 | #define PCIE_HOTPLUG_IN_D3_PROPERTY "HotPlugSupportInD3" |
| 25 | |
| 26 | /* |
| 27 | * This UUID and the resulting ACPI Device Property is defined by the |
| 28 | * Power Management for Storage Hardware Devices: |
| 29 | * |
| 30 | * https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro |
| 31 | */ |
| 32 | #define PCIE_RTD3_STORAGE_UUID "5025030F-842F-4AB4-A561-99A5189762D0" |
| 33 | #define PCIE_RTD3_STORAGE_PROPERTY "StorageD3Enable" |
| 34 | |
| 35 | /* PCIe Root Port registers for link status and L23 control. */ |
| 36 | #define PCH_PCIE_CFG_LSTS 0x52 /* Link Status Register */ |
| 37 | #define PCH_PCIE_CFG_SPR 0xe0 /* Scratchpad */ |
| 38 | #define PCH_PCIE_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ |
| 39 | #define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ |
| 40 | |
| 41 | /* ACPI register names corresponding to PCIe root port registers. */ |
| 42 | #define ACPI_REG_PCI_LINK_ACTIVE "LASX" /* Link active status */ |
| 43 | #define ACPI_REG_PCI_L23_RDY_ENTRY "L23E" /* L23_Rdy Entry Request */ |
| 44 | #define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ |
| 45 | #define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ |
| 46 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 47 | /* ACPI path to the mutex that protects accesses to PMC ModPhy power gating registers */ |
| 48 | #define RTD3_MUTEX_PATH "\\_SB.PCI0.R3MX" |
| 49 | |
| 50 | enum modphy_pg_state { |
| 51 | PG_DISABLE = 0, |
| 52 | PG_ENABLE = 1, |
| 53 | }; |
| 54 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 55 | /* Called from _ON to get PCIe link back to active state. */ |
| 56 | static void pcie_rtd3_acpi_l23_exit(void) |
| 57 | { |
| 58 | /* Skip if port is not in L2/L3. */ |
| 59 | acpigen_write_if_lequal_namestr_int(ACPI_REG_PCI_L23_SAVE_STATE, 1); |
| 60 | |
| 61 | /* Initiate L2/L3 Ready To Detect transition. */ |
| 62 | acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_DETECT); |
| 63 | |
| 64 | /* Wait for transition to detect. */ |
| 65 | acpigen_write_delay_until_namestr_int(320, ACPI_REG_PCI_L23_RDY_DETECT, 0); |
| 66 | |
| 67 | acpigen_write_store_int_to_namestr(0, ACPI_REG_PCI_L23_SAVE_STATE); |
| 68 | |
| 69 | /* Once in detect, wait for link active. */ |
| 70 | acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_LINK_ACTIVE, 1); |
| 71 | |
| 72 | acpigen_pop_len(); /* If */ |
| 73 | } |
| 74 | |
| 75 | /* Called from _OFF to put PCIe link into L2/L3 state. */ |
| 76 | static void pcie_rtd3_acpi_l23_entry(void) |
| 77 | { |
| 78 | /* Initiate L2/L3 Entry request. */ |
| 79 | acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_ENTRY); |
| 80 | |
| 81 | /* Wait for L2/L3 Entry request to clear. */ |
| 82 | acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_L23_RDY_ENTRY, 0); |
| 83 | |
| 84 | acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); |
| 85 | } |
| 86 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 87 | /* Called from _ON/_OFF to disable/enable ModPHY power gating */ |
| 88 | static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp, enum modphy_pg_state state) |
| 89 | { |
| 90 | /* Enter the critical section */ |
| 91 | acpigen_emit_ext_op(ACQUIRE_OP); |
| 92 | acpigen_emit_namestring(RTD3_MUTEX_PATH); |
| 93 | acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); |
| 94 | |
| 95 | acpigen_write_store_int_to_namestr(state, "EMPG"); |
| 96 | acpigen_write_delay_until_namestr_int(100, "AMPG", state); |
| 97 | |
| 98 | /* Exit the critical section */ |
| 99 | acpigen_emit_ext_op(RELEASE_OP); |
| 100 | acpigen_emit_namestring(RTD3_MUTEX_PATH); |
| 101 | } |
| 102 | |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 103 | /* Method to enter L2/L3 */ |
| 104 | static void pcie_rtd3_acpi_method_dl23(void) |
| 105 | { |
| 106 | acpigen_write_method_serialized("DL23", 0); |
| 107 | pcie_rtd3_acpi_l23_entry(); |
| 108 | acpigen_pop_len(); /* Method */ |
| 109 | } |
| 110 | |
| 111 | /* Method to exit L2/L3 */ |
| 112 | static void pcie_rtd3_acpi_method_l23d(void) |
| 113 | { |
| 114 | acpigen_write_method_serialized("L23D", 0); |
| 115 | pcie_rtd3_acpi_l23_exit(); |
| 116 | acpigen_pop_len(); /* Method */ |
| 117 | } |
| 118 | |
| 119 | /* Method to disable PCH modPHY power gating */ |
| 120 | static void pcie_rtd3_acpi_method_pds0(unsigned int pcie_rp) |
| 121 | { |
| 122 | acpigen_write_method_serialized("PSD0", 0); |
| 123 | pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); |
| 124 | acpigen_pop_len(); /* Method */ |
| 125 | } |
| 126 | |
| 127 | /* Method to enable/disable the source clock */ |
| 128 | static void pcie_rtd3_acpi_method_srck(unsigned int pcie_rp, |
| 129 | const struct soc_intel_common_block_pcie_rtd3_config *config) |
| 130 | { |
| 131 | acpigen_write_method_serialized("SRCK", 1); |
| 132 | |
| 133 | if (config->srcclk_pin >= 0) { |
| 134 | acpigen_write_if_lequal_op_op(ARG0_OP, 0); |
| 135 | pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); |
| 136 | acpigen_write_else(); |
| 137 | pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); |
| 138 | acpigen_pop_len(); /* If */ |
| 139 | } |
| 140 | acpigen_pop_len(); /* Method */ |
| 141 | } |
| 142 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 143 | static void |
| 144 | pcie_rtd3_acpi_method_on(unsigned int pcie_rp, |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 145 | const struct soc_intel_common_block_pcie_rtd3_config *config, |
| 146 | enum pcie_rp_type rp_type) |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 147 | { |
| 148 | acpigen_write_method_serialized("_ON", 0); |
| 149 | |
Cliff Huang | d1a7416 | 2022-01-21 14:54:32 -0800 | [diff] [blame] | 150 | /* When this feature is enabled, ONSK indicates if the previous _OFF was |
| 151 | * skipped. If so, since the device was not in Off state, and the current |
| 152 | * _ON can be skipped as well. |
| 153 | */ |
| 154 | if (config->skip_on_off_support) |
| 155 | acpigen_write_if_lequal_namestr_int("ONSK", 0); |
| 156 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 157 | /* Disable modPHY power gating for PCH RPs. */ |
| 158 | if (rp_type == PCIE_RP_PCH) |
| 159 | pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); |
| 160 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 161 | /* Assert enable GPIO to turn on device power. */ |
| 162 | if (config->enable_gpio.pin_count) { |
| 163 | acpigen_enable_tx_gpio(&config->enable_gpio); |
| 164 | if (config->enable_delay_ms) |
| 165 | acpigen_write_sleep(config->enable_delay_ms); |
| 166 | } |
| 167 | |
| 168 | /* Enable SRCCLK for root port if pin is defined. */ |
| 169 | if (config->srcclk_pin >= 0) |
| 170 | pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); |
| 171 | |
| 172 | /* De-assert reset GPIO to bring device out of reset. */ |
| 173 | if (config->reset_gpio.pin_count) { |
| 174 | acpigen_disable_tx_gpio(&config->reset_gpio); |
| 175 | if (config->reset_delay_ms) |
| 176 | acpigen_write_sleep(config->reset_delay_ms); |
| 177 | } |
| 178 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 179 | /* Trigger L23 ready exit flow unless disabled by config. */ |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 180 | if (!config->disable_l23) |
| 181 | pcie_rtd3_acpi_l23_exit(); |
| 182 | |
Cliff Huang | d1a7416 | 2022-01-21 14:54:32 -0800 | [diff] [blame] | 183 | if (config->skip_on_off_support) { |
| 184 | /* If current _ON is skipped, ONSK is decremented so that _ON will be |
| 185 | * executed normally until _OFF is skipped again. |
| 186 | */ |
| 187 | acpigen_write_else(); |
| 188 | acpigen_emit_byte(DECREMENT_OP); |
| 189 | acpigen_emit_namestring("ONSK"); |
| 190 | |
| 191 | acpigen_pop_len(); /* Else */ |
| 192 | } |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 193 | acpigen_pop_len(); /* Method */ |
| 194 | } |
| 195 | |
| 196 | static void |
| 197 | pcie_rtd3_acpi_method_off(int pcie_rp, |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 198 | const struct soc_intel_common_block_pcie_rtd3_config *config, |
| 199 | enum pcie_rp_type rp_type) |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 200 | { |
| 201 | acpigen_write_method_serialized("_OFF", 0); |
| 202 | |
Cliff Huang | d1a7416 | 2022-01-21 14:54:32 -0800 | [diff] [blame] | 203 | /* When this feature is enabled, ONSK is checked to see if the device |
| 204 | * wants _OFF to be skipped for once. ONSK is normally incremented in the |
| 205 | * device method, such as reset _RST, which is invoked during driver reload. |
| 206 | * In such case, _OFF needs to be avoided at the end of driver removal. |
| 207 | */ |
| 208 | if (config->skip_on_off_support) |
| 209 | acpigen_write_if_lequal_namestr_int("OFSK", 0); |
| 210 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 211 | /* Trigger L23 ready entry flow unless disabled by config. */ |
| 212 | if (!config->disable_l23) |
| 213 | pcie_rtd3_acpi_l23_entry(); |
| 214 | |
| 215 | /* Assert reset GPIO to place device into reset. */ |
| 216 | if (config->reset_gpio.pin_count) { |
| 217 | acpigen_enable_tx_gpio(&config->reset_gpio); |
| 218 | if (config->reset_off_delay_ms) |
| 219 | acpigen_write_sleep(config->reset_off_delay_ms); |
| 220 | } |
| 221 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 222 | /* Enable modPHY power gating for PCH RPs */ |
| 223 | if (rp_type == PCIE_RP_PCH) |
| 224 | pcie_rtd3_enable_modphy_pg(pcie_rp, PG_ENABLE); |
| 225 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 226 | /* Disable SRCCLK for this root port if pin is defined. */ |
| 227 | if (config->srcclk_pin >= 0) |
| 228 | pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); |
| 229 | |
| 230 | /* De-assert enable GPIO to turn off device power. */ |
| 231 | if (config->enable_gpio.pin_count) { |
| 232 | acpigen_disable_tx_gpio(&config->enable_gpio); |
| 233 | if (config->enable_off_delay_ms) |
| 234 | acpigen_write_sleep(config->enable_off_delay_ms); |
| 235 | } |
| 236 | |
Cliff Huang | d1a7416 | 2022-01-21 14:54:32 -0800 | [diff] [blame] | 237 | if (config->skip_on_off_support) { |
| 238 | /* If current _OFF is skipped, ONSK is incremented so that the |
| 239 | * following _ON will also be skipped. In addition, OFSK is decremented |
| 240 | * so that next _OFF will be executed normally until the device method |
| 241 | * increments OFSK again. |
| 242 | */ |
| 243 | acpigen_write_else(); |
| 244 | /* OFSK-- */ |
| 245 | acpigen_emit_byte(DECREMENT_OP); |
| 246 | acpigen_emit_namestring("OFSK"); |
| 247 | /* ONSK++ */ |
| 248 | acpigen_emit_byte(INCREMENT_OP); |
| 249 | acpigen_emit_namestring("ONSK"); |
| 250 | |
| 251 | acpigen_pop_len(); /* Else */ |
| 252 | } |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 253 | acpigen_pop_len(); /* Method */ |
| 254 | } |
| 255 | |
| 256 | static void |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 257 | pcie_rtd3_acpi_method_status(const struct soc_intel_common_block_pcie_rtd3_config *config) |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 258 | { |
| 259 | const struct acpi_gpio *gpio; |
| 260 | |
| 261 | acpigen_write_method("_STA", 0); |
| 262 | |
| 263 | /* Use enable GPIO for status if provided, otherwise use reset GPIO. */ |
| 264 | if (config->enable_gpio.pin_count) |
| 265 | gpio = &config->enable_gpio; |
| 266 | else |
| 267 | gpio = &config->reset_gpio; |
| 268 | |
| 269 | /* Read current GPIO value into Local0. */ |
| 270 | acpigen_get_tx_gpio(gpio); |
| 271 | |
| 272 | /* Ensure check works for both active low and active high GPIOs. */ |
| 273 | acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); |
| 274 | |
| 275 | acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); |
| 276 | acpigen_write_return_op(ZERO_OP); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 277 | acpigen_write_else(); |
| 278 | acpigen_write_return_op(ONE_OP); |
| 279 | acpigen_pop_len(); /* Else */ |
| 280 | |
| 281 | acpigen_pop_len(); /* Method */ |
| 282 | } |
| 283 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 284 | static void write_modphy_opregion(unsigned int pcie_rp) |
| 285 | { |
| 286 | /* The register containing the Power Gate enable sequence bits is at |
| 287 | PCH_PWRM_BASE + 0x10D0, and the bits to check for sequence completion are at |
| 288 | PCH_PWRM_BASE + 0x10D4. */ |
| 289 | const struct opregion opregion = OPREGION("PMCP", SYSTEMMEMORY, |
| 290 | PCH_PWRM_BASE_ADDRESS + 0x1000, 0xff); |
| 291 | const struct fieldlist fieldlist[] = { |
| 292 | FIELDLIST_OFFSET(0xD0), |
| 293 | FIELDLIST_RESERVED(pcie_rp), |
| 294 | FIELDLIST_NAMESTR("EMPG", 1), /* Enable ModPHY Power Gate */ |
| 295 | FIELDLIST_OFFSET(0xD4), |
| 296 | FIELDLIST_RESERVED(pcie_rp), |
| 297 | FIELDLIST_NAMESTR("AMPG", 1), /* Is ModPHY Power Gate active? */ |
| 298 | }; |
| 299 | |
| 300 | acpigen_write_opregion(&opregion); |
| 301 | acpigen_write_field("PMCP", fieldlist, ARRAY_SIZE(fieldlist), |
| 302 | FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); |
| 303 | } |
| 304 | |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 305 | static int get_pcie_rp_pmc_idx(enum pcie_rp_type rp_type, const struct device *dev) |
| 306 | { |
| 307 | int idx = -1; |
| 308 | |
| 309 | switch (rp_type) { |
| 310 | case PCIE_RP_PCH: |
| 311 | /* Read port number of root port that this device is attached to. */ |
| 312 | idx = pci_read_config8(dev, PCH_PCIE_CFG_LCAP_PN); |
| 313 | |
| 314 | /* Port number is 1-based, PMC IPC method expects 0-based. */ |
| 315 | idx--; |
| 316 | break; |
| 317 | case PCIE_RP_CPU: |
| 318 | /* CPU RPs are indexed by their "virtual wire index" to the PCH */ |
| 319 | idx = soc_get_cpu_rp_vw_idx(dev); |
| 320 | break; |
| 321 | default: |
| 322 | break; |
| 323 | } |
| 324 | |
| 325 | return idx; |
| 326 | } |
| 327 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 328 | static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) |
| 329 | { |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 330 | static bool mutex_created = false; |
| 331 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 332 | const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); |
| 333 | static const char *const power_res_states[] = {"_PR0"}; |
| 334 | const struct device *parent = dev->bus->dev; |
| 335 | const char *scope = acpi_device_path(parent); |
| 336 | const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff); |
| 337 | const struct fieldlist fieldlist[] = { |
| 338 | FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS), |
| 339 | FIELDLIST_RESERVED(13), |
| 340 | FIELDLIST_NAMESTR(ACPI_REG_PCI_LINK_ACTIVE, 1), |
| 341 | FIELDLIST_OFFSET(PCH_PCIE_CFG_SPR), |
| 342 | FIELDLIST_RESERVED(7), |
| 343 | FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_SAVE_STATE, 1), |
| 344 | FIELDLIST_OFFSET(PCH_PCIE_CFG_RPPGEN), |
| 345 | FIELDLIST_RESERVED(2), |
| 346 | FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1), |
| 347 | FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1), |
| 348 | }; |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 349 | int pcie_rp; |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 350 | struct acpi_dp *dsd, *pkg; |
| 351 | |
| 352 | if (!is_dev_enabled(parent)) { |
| 353 | printk(BIOS_ERR, "%s: root port not enabled\n", __func__); |
| 354 | return; |
| 355 | } |
| 356 | if (!scope) { |
| 357 | printk(BIOS_ERR, "%s: root port scope not found\n", __func__); |
| 358 | return; |
| 359 | } |
| 360 | if (!config->enable_gpio.pin_count && !config->reset_gpio.pin_count) { |
| 361 | printk(BIOS_ERR, "%s: Enable and/or Reset GPIO required for %s.\n", |
| 362 | __func__, scope); |
| 363 | return; |
| 364 | } |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 365 | if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCK_SRC) { |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 366 | printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, |
| 367 | config->srcclk_pin, scope); |
| 368 | return; |
| 369 | } |
| 370 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 371 | const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 372 | pcie_rp = get_pcie_rp_pmc_idx(rp_type, parent); |
Tim Wawrzynczak | b3cd55b | 2022-01-20 14:06:29 -0700 | [diff] [blame] | 373 | if (pcie_rp < 0) { |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 374 | printk(BIOS_ERR, "%s: Unknown PCIe root port\n", __func__); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 375 | return; |
| 376 | } |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 377 | if (config->disable_l23) { |
Angel Pons | d85319a | 2022-02-13 13:35:20 +0100 | [diff] [blame^] | 378 | if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_L23) { |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 379 | printk(BIOS_ERR, "%s: Can not export L23 methods\n", __func__); |
| 380 | return; |
| 381 | } |
| 382 | } |
| 383 | if (rp_type != PCIE_RP_PCH) { |
Angel Pons | d85319a | 2022-02-13 13:35:20 +0100 | [diff] [blame^] | 384 | if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_PSD0) { |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 385 | printk(BIOS_ERR, "%s: Can not export PSD0 method\n", __func__); |
| 386 | return; |
| 387 | } |
| 388 | } |
| 389 | if (config->srcclk_pin == 0) { |
Angel Pons | d85319a | 2022-02-13 13:35:20 +0100 | [diff] [blame^] | 390 | if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_SRCK) { |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 391 | printk(BIOS_ERR, "%s: Can not export SRCK method\n", __func__); |
| 392 | return; |
| 393 | } |
| 394 | } |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 395 | |
| 396 | printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), |
| 397 | config->desc ?: dev->chip_ops->name); |
| 398 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 399 | /* Create a mutex for exclusive access to the PMC registers. */ |
| 400 | if (rp_type == PCIE_RP_PCH && !mutex_created) { |
| 401 | acpigen_write_scope("\\_SB.PCI0"); |
| 402 | acpigen_write_mutex("R3MX", 0); |
| 403 | acpigen_write_scope_end(); |
| 404 | mutex_created = true; |
| 405 | } |
| 406 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 407 | /* The RTD3 power resource is added to the root port, not the device. */ |
| 408 | acpigen_write_scope(scope); |
| 409 | |
| 410 | if (config->desc) |
| 411 | acpigen_write_name_string("_DDN", config->desc); |
| 412 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 413 | /* Create OpRegions for MMIO accesses. */ |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 414 | acpigen_write_opregion(&opregion); |
| 415 | acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), |
| 416 | FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); |
| 417 | |
Angel Pons | d85319a | 2022-02-13 13:35:20 +0100 | [diff] [blame^] | 418 | if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_L23) { |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 419 | pcie_rtd3_acpi_method_dl23(); |
| 420 | pcie_rtd3_acpi_method_l23d(); |
| 421 | } |
| 422 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 423 | /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ |
| 424 | if (rp_type == PCIE_RP_PCH) |
| 425 | write_modphy_opregion(pcie_rp); |
| 426 | |
Angel Pons | d85319a | 2022-02-13 13:35:20 +0100 | [diff] [blame^] | 427 | if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_PSD0) |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 428 | pcie_rtd3_acpi_method_pds0(pcie_rp); |
| 429 | |
Angel Pons | d85319a | 2022-02-13 13:35:20 +0100 | [diff] [blame^] | 430 | if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_SRCK) |
Cliff Huang | 4bc9ac7 | 2022-01-21 00:23:15 -0800 | [diff] [blame] | 431 | pcie_rtd3_acpi_method_srck(pcie_rp, config); |
| 432 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 433 | /* ACPI Power Resource for controlling the attached device power. */ |
| 434 | acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); |
Cliff Huang | d1a7416 | 2022-01-21 14:54:32 -0800 | [diff] [blame] | 435 | |
| 436 | if (config->skip_on_off_support) { |
| 437 | /* OFSK: 0 = _OFF Method will be executed normally when called; |
| 438 | * >1 = _OFF will be skipped. |
| 439 | * _OFF Method to decrement OFSK and increment ONSK if the |
| 440 | * current execution is skipped. |
| 441 | * ONSK: 0 = _ON Method will be executed normally when called; |
| 442 | * >1 = _ONF will be skipped. |
| 443 | * _ON Method to decrement ONSK if the current execution is |
| 444 | * skipped. |
| 445 | */ |
| 446 | acpigen_write_name_integer("ONSK", 0); |
| 447 | acpigen_write_name_integer("OFSK", 0); |
| 448 | } |
| 449 | |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 450 | pcie_rtd3_acpi_method_status(config); |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 451 | pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); |
| 452 | pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 453 | acpigen_pop_len(); /* PowerResource */ |
| 454 | |
| 455 | /* Indicate to the OS that device supports hotplug in D3. */ |
| 456 | dsd = acpi_dp_new_table("_DSD"); |
| 457 | pkg = acpi_dp_new_table(PCIE_HOTPLUG_IN_D3_UUID); |
| 458 | acpi_dp_add_integer(pkg, PCIE_HOTPLUG_IN_D3_PROPERTY, 1); |
| 459 | acpi_dp_add_package(dsd, pkg); |
| 460 | |
| 461 | /* Indicate to the OS if the device provides an External facing port. */ |
| 462 | if (config->is_external) { |
| 463 | pkg = acpi_dp_new_table(PCIE_EXTERNAL_PORT_UUID); |
| 464 | acpi_dp_add_integer(pkg, PCIE_EXTERNAL_PORT_PROPERTY, 1); |
| 465 | acpi_dp_add_package(dsd, pkg); |
| 466 | } |
| 467 | acpi_dp_write(dsd); |
| 468 | |
| 469 | /* |
| 470 | * Check the sibling device on the root port to see if it is storage class and add the |
| 471 | * property for the OS to enable storage D3, or allow it to be enabled by config. |
| 472 | */ |
| 473 | if (config->is_storage |
| 474 | || (dev->sibling && (dev->sibling->class >> 16) == PCI_BASE_CLASS_STORAGE)) { |
| 475 | acpigen_write_device(acpi_device_name(dev)); |
| 476 | acpigen_write_ADR(0); |
| 477 | acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); |
Tim Wawrzynczak | 6108321 | 2021-08-05 09:40:19 -0600 | [diff] [blame] | 478 | acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 479 | |
| 480 | dsd = acpi_dp_new_table("_DSD"); |
| 481 | pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID); |
| 482 | acpi_dp_add_integer(pkg, PCIE_RTD3_STORAGE_PROPERTY, 1); |
| 483 | acpi_dp_add_package(dsd, pkg); |
| 484 | acpi_dp_write(dsd); |
| 485 | |
| 486 | acpigen_pop_len(); /* Device */ |
| 487 | |
| 488 | printk(BIOS_INFO, "%s: Added StorageD3Enable property\n", scope); |
| 489 | } |
| 490 | |
| 491 | acpigen_pop_len(); /* Scope */ |
| 492 | } |
| 493 | |
| 494 | static const char *pcie_rtd3_acpi_name(const struct device *dev) |
| 495 | { |
| 496 | /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ |
| 497 | return "PXSX"; |
| 498 | } |
| 499 | |
| 500 | static struct device_operations pcie_rtd3_ops = { |
| 501 | .read_resources = noop_read_resources, |
| 502 | .set_resources = noop_set_resources, |
| 503 | .acpi_fill_ssdt = pcie_rtd3_acpi_fill_ssdt, |
| 504 | .acpi_name = pcie_rtd3_acpi_name, |
| 505 | }; |
| 506 | |
| 507 | static void pcie_rtd3_acpi_enable(struct device *dev) |
| 508 | { |
| 509 | dev->ops = &pcie_rtd3_ops; |
| 510 | } |
| 511 | |
| 512 | struct chip_operations soc_intel_common_block_pcie_rtd3_ops = { |
| 513 | CHIP_NAME("Intel PCIe Runtime D3") |
| 514 | .enable_dev = pcie_rtd3_acpi_enable |
| 515 | }; |