blob: 334959c7bfdea961401700254bd76bde09862674 [file] [log] [blame]
Wisley Chen02255912022-08-18 16:07:14 +06001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#include <baseboard/gpio.h>
4#include <baseboard/variants.h>
5#include <commonlib/helpers.h>
6#include <soc/gpio.h>
Shon Wang31f502a2023-04-07 15:19:51 +08007#include <fw_config.h>
Wisley Chen02255912022-08-18 16:07:14 +06008
9/* Pad configuration in ramstage */
10static const struct pad_config override_gpio_table[] = {
11 /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
12 PAD_CFG_GPO(GPP_A21, 0, DEEP),
13 /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
14 PAD_CFG_GPO(GPP_A22, 1, DEEP),
15
16 /* B5 : SOC_I2C_SUB_SDA ==> NC */
17 PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
18 /* B6 : SOC_I2C_SUB_SCL ==> NC */
19 PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
20
21 /* D3 : WCAM_RST_L ==> NC */
22 PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
23 /* D15 : EN_PP2800_WCAM_X ==> NC */
24 PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
25 /* D16 : EN_PP1800_PP1200_WCAM_X ==> NC */
26 PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
27 /* D17 : NC ==> SD_WAKE_N */
28 PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
29
30 /* E20 : DDP2_CTRLCLK ==> NC */
31 PAD_NC(GPP_E20, NONE),
32 /* E21 : DDP2_CTRLDATA ==> NC */
33 PAD_NC(GPP_E21, NONE),
34
35 /* F6 : CNV_PA_BLANKING ==> NC */
36 PAD_NC(GPP_F6, NONE),
37 /* F12 : GSXDOUT ==> NC */
38 PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
39 /* F13 : GSXSLOAD ==> NC */
40 PAD_NC(GPP_F13, NONE),
41 /* F15 : GSXSRESET# ==> NC */
42 PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
43
44 /* H8 : CNV_MFUART2_RXD ==> NC */
45 PAD_NC(GPP_H8, NONE),
46 /* H9 : CNV_MFUART2_TXD ==> NC */
47 PAD_NC(GPP_H9, NONE),
48 /* H19 : SRCCLKREQ4# ==> NC */
49 PAD_NC(GPP_H19, NONE),
50 /* H22 : IMGCLKOUT3 ==> NC */
51 PAD_NC(GPP_H22, NONE),
52 /* H23 : GPP_H23 ==> NC */
53 PAD_NC(GPP_H23, NONE),
54
55 /* R6 : DMIC_CLK_A_1A ==> NC */
56 PAD_NC(GPP_R6, NONE),
57 /* R7 : DMIC_DATA_1A ==> NC */
58 PAD_NC(GPP_R7, NONE),
59};
60
Shon Wang31f502a2023-04-07 15:19:51 +080061/* Pad configuration in ramstage for yavilla */
62static const struct pad_config override_gpio_table_yavilla[] = {
63 /* A8 : WWAN_RF_DISABLE_ODL */
64 PAD_CFG_GPO(GPP_A8, 1, DEEP),
65 /* A18 : NC ==> HDMI_HPD_SRC */
66 PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
67 /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
68 PAD_CFG_GPO(GPP_A21, 0, DEEP),
69 /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
70 PAD_CFG_GPO(GPP_A22, 1, DEEP),
71
72 /* D6 : WWAN_EN */
73 PAD_CFG_GPO(GPP_D6, 1, DEEP),
74 /* D8 : SD_CLKREQ_ODL ==> NC */
75 PAD_NC(GPP_D8, NONE),
76
77 /* F6 : CNV_PA_BLANKING ==> NC */
78 PAD_NC(GPP_F6, NONE),
79 /* F12 : WWAN_RST_ODL */
80 PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
81 /* F23 : V1P05EXT_CTRL ==> NC */
82 PAD_NC(GPP_F23, NONE),
83
84 /* H8 : CNV_MFUART2_RXD ==> NC */
85 PAD_NC(GPP_H8, NONE),
86 /* H9 : CNV_MFUART2_TXD ==> NC */
87 PAD_NC(GPP_H9, NONE),
88 /* H12 : SD_PERST_L ==> NC */
89 PAD_NC(GPP_H12, NONE),
90 /* H13 : EN_PP3300_SD_X ==> NC */
91 PAD_NC(GPP_H13, NONE),
92 /* H15 : HDMI_SRC_SCL */
93 PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
94 /* H17 : HDMI_SRC_SDA */
95 PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
96 /* H19 : SRCCLKREQ4# ==> NC */
97 PAD_NC(GPP_H19, NONE),
98 /* H23 : WWAN_SAR_DETECT_ODL */
99 PAD_CFG_GPO(GPP_H23, 1, DEEP),
100};
101
Wisley Chen02255912022-08-18 16:07:14 +0600102/* Early pad configuration in bootblock */
103static const struct pad_config early_gpio_table[] = {
104 /* H12 : UART0_RTS# ==> SD_PERST_L */
105 PAD_CFG_GPO(GPP_H12, 0, DEEP),
106 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
107 PAD_CFG_GPO(GPP_H20, 0, DEEP),
108 /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
109 PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
110 /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
111 PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
112 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
113 PAD_CFG_GPI(GPP_F18, NONE, DEEP),
114 /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
115 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
116 /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
117 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
118 /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
119 PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
120 /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
121 PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
122 /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
123 PAD_CFG_GPO(GPP_B11, 1, DEEP),
124 /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
125 PAD_CFG_GPO(GPP_H13, 1, DEEP),
126};
127
Shon Wang31f502a2023-04-07 15:19:51 +0800128/* Early pad configuration in bootblock for yavilla */
129static const struct pad_config early_gpio_table_yavilla[] = {
130 /* D6 : WWAN_EN */
131 PAD_CFG_GPO(GPP_D6, 0, DEEP),
132 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
133 PAD_CFG_GPO(GPP_H20, 0, DEEP),
134 /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
135 PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
136 /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
137 PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
138 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
139 PAD_CFG_GPI(GPP_F18, NONE, DEEP),
140 /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
141 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
142 /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
143 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
144 /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
145 PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
146 /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
147 PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
148 /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
149 PAD_CFG_GPO(GPP_B11, 1, DEEP),
150 /* F12 : WWAN_RST_ODL */
151 PAD_CFG_GPO(GPP_F12, 0, DEEP),
152};
153
Wisley Chen02255912022-08-18 16:07:14 +0600154static const struct pad_config romstage_gpio_table[] = {
Matt DeVillierd7d74f12023-04-27 09:55:51 -0500155 /* Enable touchscreen, hold in reset */
156 /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
157 PAD_CFG_GPO(GPP_C0, 1, DEEP),
158 /* C1 : SMBDATA ==> USI_RST_L */
159 PAD_CFG_GPO(GPP_C1, 0, DEEP),
160
Wisley Chen02255912022-08-18 16:07:14 +0600161 /* H12 : UART0_RTS# ==> SD_PERST_L */
162 PAD_CFG_GPO(GPP_H12, 1, DEEP),
163 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
164 PAD_CFG_GPO(GPP_H20, 1, DEEP),
165};
166
Shon Wang31f502a2023-04-07 15:19:51 +0800167static const struct pad_config romstage_gpio_table_yavilla[] = {
168 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
169 PAD_CFG_GPO(GPP_H20, 1, DEEP),
170};
171
Wisley Chen02255912022-08-18 16:07:14 +0600172const struct pad_config *variant_gpio_override_table(size_t *num)
173{
Shon Wang31f502a2023-04-07 15:19:51 +0800174 if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
175 *num = ARRAY_SIZE(override_gpio_table_yavilla);
176 return override_gpio_table_yavilla;
177 }
Wisley Chen02255912022-08-18 16:07:14 +0600178 *num = ARRAY_SIZE(override_gpio_table);
179 return override_gpio_table;
180}
181
182const struct pad_config *variant_early_gpio_table(size_t *num)
183{
Shon Wang31f502a2023-04-07 15:19:51 +0800184 if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
185 *num = ARRAY_SIZE(early_gpio_table_yavilla);
186 return early_gpio_table_yavilla;
187 }
Wisley Chen02255912022-08-18 16:07:14 +0600188 *num = ARRAY_SIZE(early_gpio_table);
189 return early_gpio_table;
190}
191
192const struct pad_config *variant_romstage_gpio_table(size_t *num)
193{
Shon Wang31f502a2023-04-07 15:19:51 +0800194 if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
195 *num = ARRAY_SIZE(romstage_gpio_table_yavilla);
196 return romstage_gpio_table_yavilla;
197 }
Wisley Chen02255912022-08-18 16:07:14 +0600198 *num = ARRAY_SIZE(romstage_gpio_table);
199 return romstage_gpio_table;
200}