YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
| 6 | #include <soc/gpio.h> |
| 7 | |
| 8 | /* Pad configuration in ramstage */ |
| 9 | static const struct pad_config override_gpio_table[] = { |
| 10 | /* A6 : ESPI_ALERT1# ==> NC */ |
| 11 | PAD_NC(GPP_A6, NONE), |
| 12 | /* A7 : SRCCLK_OE7# ==> NC */ |
| 13 | PAD_NC(GPP_A7, NONE), |
| 14 | /* A14 : USB_OC1# ==> NC */ |
| 15 | PAD_NC(GPP_A14, NONE), |
| 16 | /* A15 : USB_OC2# ==> NC */ |
| 17 | PAD_NC(GPP_A15, NONE), |
| 18 | /* A21 : DDPC_CTRCLK ==> NC */ |
| 19 | PAD_NC(GPP_A21, NONE), |
| 20 | /* A22 : DDPC_CTRLDATA ==> NC */ |
| 21 | PAD_NC(GPP_A22, NONE), |
| 22 | |
Ariel Fang | 6dfc0ae | 2021-12-14 19:29:34 +0800 | [diff] [blame] | 23 | /* B2 : VRALERT# ==> NC */ |
| 24 | PAD_NC(GPP_B2, NONE), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 25 | /* B3 : PROC_GP2 ==> eMMC_PERST_L */ |
Casper Chang | 7a7a5337 | 2022-03-01 13:13:20 +0800 | [diff] [blame] | 26 | PAD_CFG_GPO(GPP_B3, 1, DEEP), |
Subrata Banik | da28277 | 2022-01-31 14:31:33 +0530 | [diff] [blame] | 27 | /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 28 | PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), |
| 29 | /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 30 | PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), |
Ariel Fang | 6dfc0ae | 2021-12-14 19:29:34 +0800 | [diff] [blame] | 31 | /* B15 : TIME_SYNC0 ==> NC */ |
Eric Lai | 6c10007 | 2022-02-08 11:11:50 +0800 | [diff] [blame] | 32 | PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 33 | |
| 34 | /* C3 : SML0CLK ==> NC */ |
| 35 | PAD_NC(GPP_C3, NONE), |
| 36 | /* C4 : SML0DATA ==> NC */ |
| 37 | PAD_NC(GPP_C4, NONE), |
| 38 | |
Ariel Fang | 6dfc0ae | 2021-12-14 19:29:34 +0800 | [diff] [blame] | 39 | /* D3 : ISH_GP3 ==> NC */ |
Eric Lai | 6c10007 | 2022-02-08 11:11:50 +0800 | [diff] [blame] | 40 | PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 41 | /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ |
| 42 | PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), |
| 43 | /* D6 : SRCCLKREQ1# ==> NC */ |
| 44 | PAD_NC(GPP_D6, NONE), |
| 45 | /* D13 : ISH_UART0_RXD ==> NC */ |
Eric Lai | 6c10007 | 2022-02-08 11:11:50 +0800 | [diff] [blame] | 46 | PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 47 | /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ |
Eric Lai | 6c10007 | 2022-02-08 11:11:50 +0800 | [diff] [blame] | 48 | PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 49 | /* D18 : UART1_TXD ==> SD_PE_RST_L */ |
Eric Lai | 6c10007 | 2022-02-08 11:11:50 +0800 | [diff] [blame] | 50 | PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 51 | |
| 52 | /* E3 : PROC_GP0 ==> NC */ |
| 53 | PAD_NC(GPP_E3, NONE), |
| 54 | /* E7 : PROC_GP1 ==> NC */ |
| 55 | PAD_NC(GPP_E7, NONE), |
Casper Chang | f7abb4f | 2022-03-09 16:48:58 +0800 | [diff] [blame] | 56 | /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ |
| 57 | PAD_CFG_GPO(GPP_E20, 1, DEEP), |
Ariel Fang | 6dfc0ae | 2021-12-14 19:29:34 +0800 | [diff] [blame] | 58 | /* E21 : DDP2_CTRLDATA ==> NC */ |
| 59 | PAD_NC(GPP_E21, NONE), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 60 | |
| 61 | /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ |
| 62 | PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), |
| 63 | /* F20 : EXT_PWR_GATE# ==> NC */ |
| 64 | PAD_NC(GPP_F20, NONE), |
| 65 | |
| 66 | /* H19 : SRCCLKREQ4# ==> NC */ |
| 67 | PAD_NC(GPP_H19, NONE), |
| 68 | /* H21 : IMGCLKOUT2 ==> NC */ |
| 69 | PAD_NC(GPP_H21, NONE), |
| 70 | /* H22 : IMGCLKOUT3 ==> NC */ |
| 71 | PAD_NC(GPP_H22, NONE), |
| 72 | /* H23 : SRCCLKREQ5# ==> NC */ |
| 73 | PAD_NC(GPP_H23, NONE), |
| 74 | |
| 75 | /* S6 : SNDW3_CLK ==> NC */ |
| 76 | PAD_NC(GPP_S6, NONE), |
| 77 | /* S7 : SNDW3_DATA ==> NC */ |
| 78 | PAD_NC(GPP_S7, NONE), |
| 79 | |
| 80 | /* T2 : GPP_T2 ==> eMMC_CFG */ |
| 81 | PAD_CFG_GPI(GPP_T2, NONE, DEEP), |
| 82 | |
| 83 | /* GPD11: LANPHYC ==> NC */ |
| 84 | PAD_NC(GPD11, NONE), |
| 85 | }; |
| 86 | |
| 87 | /* Early pad configuration in bootblock */ |
| 88 | static const struct pad_config early_gpio_table[] = { |
| 89 | /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ |
| 90 | PAD_CFG_GPO(GPP_A12, 1, DEEP), |
| 91 | /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ |
| 92 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
Casper Chang | 7a7a5337 | 2022-03-01 13:13:20 +0800 | [diff] [blame] | 93 | /* B3 : PROC_GP2 ==> eMMC_PERST_L */ |
| 94 | PAD_CFG_GPO(GPP_B3, 0, DEEP), |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 95 | /* B4 : PROC_GP3 ==> SSD_PERST_L */ |
| 96 | PAD_CFG_GPO(GPP_B4, 0, DEEP), |
| 97 | /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 98 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), |
| 99 | /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 100 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), |
| 101 | /* |
| 102 | * D1 : ISH_GP1 ==> FP_RST_ODL |
| 103 | * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. |
| 104 | * To ensure proper power sequencing for the FPMCU device, reset signal is driven low |
| 105 | * early on in bootblock, followed by enabling of power. Reset signal is deasserted |
| 106 | * later on in ramstage. Since reset signal is asserted in bootblock, it results in |
| 107 | * FPMCU not working after a S3 resume. This is a known issue. |
| 108 | */ |
| 109 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 110 | /* D2 : ISH_GP2 ==> EN_FP_PWR */ |
| 111 | PAD_CFG_GPO(GPP_D2, 1, DEEP), |
| 112 | /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ |
| 113 | PAD_CFG_GPO(GPP_D11, 1, DEEP), |
| 114 | /* D18 : UART1_TXD ==> SD_PE_RST_L */ |
| 115 | PAD_CFG_GPO(GPP_D18, 0, PLTRST), |
| 116 | /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/ |
| 117 | PAD_CFG_GPO(GPP_E0, 0, DEEP), |
| 118 | /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |
| 119 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 120 | /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/ |
| 121 | PAD_CFG_GPO(GPP_E16, 0, DEEP), |
| 122 | /* E15 : RSVD_TP ==> PCH_WP_OD */ |
| 123 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
| 124 | /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ |
| 125 | PAD_CFG_GPO(GPP_E20, 1, DEEP), |
| 126 | /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ |
| 127 | PAD_CFG_GPO(GPP_F21, 0, DEEP), |
| 128 | /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ |
| 129 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
| 130 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 131 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 132 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 133 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
| 134 | /* H13 : I2C7_SCL ==> EN_PP3300_SD */ |
| 135 | PAD_CFG_GPO(GPP_H13, 1, PLTRST), |
| 136 | }; |
| 137 | |
| 138 | static const struct pad_config romstage_gpio_table[] = { |
| 139 | /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ |
| 140 | PAD_CFG_GPO(GPP_A12, 1, DEEP), |
Tarun Tuli | 2b523ce | 2022-08-29 13:39:58 -0400 | [diff] [blame] | 141 | |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 142 | /* B4 : PROC_GP3 ==> SSD_PERST_L */ |
| 143 | PAD_CFG_GPO(GPP_B4, 1, DEEP), |
Tarun Tuli | 2b523ce | 2022-08-29 13:39:58 -0400 | [diff] [blame] | 144 | |
Matt DeVillier | d7d74f1 | 2023-04-27 09:55:51 -0500 | [diff] [blame^] | 145 | /* Enable touchscreen, hold in reset */ |
| 146 | /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ |
| 147 | PAD_CFG_GPO(GPP_C0, 1, DEEP), |
| 148 | /* C1 : SMBDATA ==> USI_RST_L */ |
| 149 | PAD_CFG_GPO(GPP_C1, 0, DEEP), |
| 150 | |
Tarun Tuli | 2b523ce | 2022-08-29 13:39:58 -0400 | [diff] [blame] | 151 | /* D1 : ISH_GP1 ==> FP_RST_ODL */ |
| 152 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 153 | /* D2 : ISH_GP2 ==> EN_FP_PWR */ |
| 154 | PAD_CFG_GPO(GPP_D2, 0, DEEP), |
| 155 | |
YH Lin | 6ba7bee | 2021-11-29 09:44:01 -0800 | [diff] [blame] | 156 | /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ |
| 157 | PAD_CFG_GPO(GPP_F21, 1, DEEP), |
| 158 | }; |
| 159 | |
| 160 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 161 | { |
| 162 | *num = ARRAY_SIZE(override_gpio_table); |
| 163 | return override_gpio_table; |
| 164 | } |
| 165 | |
| 166 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 167 | { |
| 168 | *num = ARRAY_SIZE(early_gpio_table); |
| 169 | return early_gpio_table; |
| 170 | } |
| 171 | |
| 172 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 173 | { |
| 174 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 175 | return romstage_gpio_table; |
| 176 | } |