Michał Żygowski | e622587 | 2022-10-15 16:35:31 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef SOC_INTEL_COMMON_BLOCK_VTD_H |
| 4 | #define SOC_INTEL_COMMON_BLOCK_VTD_H |
| 5 | |
Jincheng Li | d6c58b7 | 2024-06-02 20:53:25 +0800 | [diff] [blame^] | 6 | #include <device/mmio.h> |
Michał Żygowski | e622587 | 2022-10-15 16:35:31 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
Jincheng Li | d6c58b7 | 2024-06-02 20:53:25 +0800 | [diff] [blame^] | 9 | /* VT-d specification: https://cdrdv2.intel.com/v1/dl/getContent/671081 */ |
| 10 | #define VER_REG 0x0 |
| 11 | #define CAP_REG 0x8 |
| 12 | #define CAP_PMR_LO BIT(5) |
| 13 | #define CAP_PMR_HI BIT(6) |
| 14 | #define PMEN_REG 0x64 |
| 15 | #define PMEN_EPM BIT(31) |
| 16 | #define PMEN_PRS BIT(0) |
| 17 | #define PLMBASE_REG 0x68 |
| 18 | #define PLMLIMIT_REG 0x6C |
| 19 | #define PHMBASE_REG 0x70 |
| 20 | #define PHMLIMIT_REG 0x78 |
| 21 | |
| 22 | static __always_inline uint32_t vtd_read32(uintptr_t vtd_base, uint32_t reg) |
| 23 | { |
| 24 | return read32p(vtd_base + reg); |
| 25 | } |
| 26 | |
| 27 | static __always_inline void vtd_write32(uintptr_t vtd_base, uint32_t reg, uint32_t value) |
| 28 | { |
| 29 | return write32p(vtd_base + reg, value); |
| 30 | } |
| 31 | |
| 32 | static __always_inline uint64_t vtd_read64(uintptr_t vtd_base, uint32_t reg) |
| 33 | { |
| 34 | return read64p(vtd_base + reg); |
| 35 | } |
| 36 | |
| 37 | static __always_inline void vtd_write64(uintptr_t vtd_base, uint32_t reg, uint64_t value) |
| 38 | { |
| 39 | return write64p(vtd_base + reg, value); |
| 40 | } |
| 41 | |
Michał Żygowski | e622587 | 2022-10-15 16:35:31 +0200 | [diff] [blame] | 42 | /* |
| 43 | * Enable DMA protection by setting PMR registers in VT-d for whole DRAM memory. |
| 44 | */ |
| 45 | void vtd_enable_dma_protection(void); |
| 46 | /* |
| 47 | * Get DMA buffer base and size. |
| 48 | */ |
| 49 | void *vtd_get_dma_buffer(size_t *size); |
| 50 | |
| 51 | #endif /* SOC_INTEL_COMMON_BLOCK_VTD_H */ |