| Michał Żygowski | d627f7b | 2022-10-28 15:44:48 +0200 | [diff] [blame^] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_INTEL_COMMON_BLOCK_OC_WDT |
| 4 | bool |
| 5 | depends on SOC_INTEL_COMMON_BLOCK_PMC |
| 6 | help |
| 7 | Intel Processor common Overclocking Watchdog support |
| 8 | |
| 9 | config SOC_INTEL_COMMON_OC_WDT_ENABLE |
| 10 | bool "Enable overclocking watchdog during boot" |
| 11 | depends on SOC_INTEL_COMMON_BLOCK_OC_WDT |
| 12 | help |
| 13 | Enables Intel chipset Overclocking Watchdog to count during system |
| 14 | boot. The platform will reset during lockups if watchdog is not |
| 15 | reloaded. Software/firmware is responsible for feeding the watchdog. |
| 16 | |
| 17 | If unsure, say N. |
| 18 | |
| 19 | config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS |
| 20 | int |
| 21 | depends on SOC_INTEL_COMMON_OC_WDT_ENABLE |
| 22 | range 70 1024 |
| 23 | default 600 |
| 24 | help |
| 25 | The Intel chipset Overclocking Watchdog timeout value in seconds. |
| 26 | coreboot will preload the watchdog with the timeout value specified |
| 27 | in this option. Specify a high enough value so that the platform |
| 28 | will have a chance to perform full memory training and boot. Default |
| 29 | is 10 minutes. Boards and SoCs may override this value. |
| 30 | |
| 31 | config SOC_INTEL_COMMON_OC_WDT_RELOAD_IN_PERIODIC_SMI |
| 32 | bool "Reload the overclocking watchdog using periodic SMI" |
| 33 | depends on SOC_INTEL_COMMON_OC_WDT_ENABLE |
| 34 | depends on SOC_INTEL_COMMON_BLOCK_SMM |
| 35 | default y |
| 36 | help |
| 37 | Enables Intel chipset Overclocking Watchdog reloading in the periodic |
| 38 | SMI handler. Without this option the platform will keep power cycling |
| 39 | unless the OS drivers are installed for this watchdog. |
| 40 | |
| 41 | If unsure, say Y. |