Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 1 | chip soc/intel/elkhartlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
| 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
| 11 | register "pmc_gpe0_dw0" = "GPP_B" |
| 12 | register "pmc_gpe0_dw1" = "GPP_F" |
| 13 | register "pmc_gpe0_dw2" = "GPP_E" |
| 14 | |
| 15 | # FSP configuration |
| 16 | register "SaGv" = "SaGv_Disabled" |
| 17 | |
| 18 | # Enable IBECC for the complete memory |
| 19 | register "ibecc" = "{ |
| 20 | .enable = 1, |
| 21 | .mode = IBECC_ALL |
| 22 | }" |
| 23 | |
| 24 | # USB related UPDs |
| 25 | register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135 |
| 26 | register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # X125/X135 |
| 27 | register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155 |
| 28 | register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155 |
| 29 | register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB Panel |
| 30 | register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB Panel |
| 31 | register "usb2_ports[6]" = "USB2_PORT_EMPTY" |
| 32 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" |
| 33 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" |
| 34 | register "usb2_ports[9]" = "USB2_PORT_EMPTY" |
| 35 | |
| 36 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 |
| 37 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 |
| 38 | register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED |
| 39 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED |
| 40 | |
| 41 | # Skip the CPU replacement check |
| 42 | register "SkipCpuReplacementCheck" = "1" |
| 43 | |
| 44 | # PCIe root ports related UPDs |
| 45 | register "PcieRpEnable[1]" = "1" |
Jan Samek | a1a8f58 | 2022-12-01 14:52:51 +0100 | [diff] [blame] | 46 | register "PcieRpEnable[2]" = "1" |
| 47 | register "PcieRpEnable[4]" = "1" |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 48 | |
| 49 | register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" |
| 50 | register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" |
Jan Samek | a1a8f58 | 2022-12-01 14:52:51 +0100 | [diff] [blame] | 51 | register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 52 | register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" |
Jan Samek | a1a8f58 | 2022-12-01 14:52:51 +0100 | [diff] [blame] | 53 | register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" |
| 54 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 55 | |
| 56 | register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" |
| 57 | register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" |
| 58 | register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" |
| 59 | register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" |
| 60 | register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" |
| 61 | register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" |
| 62 | |
| 63 | # Disable all L1 substates for PCIe root ports |
| 64 | register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" |
Jan Samek | a1a8f58 | 2022-12-01 14:52:51 +0100 | [diff] [blame] | 65 | register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" |
| 66 | register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 67 | |
| 68 | # Disable LTR for all PCIe root ports |
| 69 | register "PcieRpLtrDisable[1]" = "true" |
Jan Samek | a1a8f58 | 2022-12-01 14:52:51 +0100 | [diff] [blame] | 70 | register "PcieRpLtrDisable[2]" = "true" |
| 71 | register "PcieRpLtrDisable[4]" = "true" |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 72 | |
| 73 | # Storage (SDCARD/EMMC) related UPDs |
| 74 | register "ScsEmmcHs400Enabled" = "0" |
| 75 | register "ScsEmmcDdr50Enabled" = "1" |
| 76 | register "SdCardPowerEnableActiveHigh" = "1" |
| 77 | |
| 78 | # GPIO for SD card detect |
| 79 | register "sdcard_cd_gpio" = "GPP_G5" |
| 80 | |
| 81 | # LPSS Serial IO (I2C/UART/GSPI) related UPDs |
| 82 | register "SerialIoI2cMode" = "{ |
| 83 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 84 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 85 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 86 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 87 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 88 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 89 | [PchSerialIoIndexI2C6] = PchSerialIoDisabled, |
| 90 | [PchSerialIoIndexI2C7] = PchSerialIoDisabled, |
| 91 | }" |
| 92 | |
| 93 | register "SerialIoUartMode" = "{ |
| 94 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 95 | [PchSerialIoIndexUART1] = PchSerialIoPci, |
| 96 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 97 | }" |
| 98 | |
| 99 | register "SerialIoUartDmaEnable" = "{ |
| 100 | [PchSerialIoIndexUART0] = 1, |
| 101 | [PchSerialIoIndexUART1] = 1, |
| 102 | [PchSerialIoIndexUART2] = 1, |
| 103 | }" |
| 104 | |
| 105 | # TSN GBE related UPDs |
| 106 | register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps" |
| 107 | register "PchTsnGbeSgmiiEnable" = "1" |
| 108 | register "PseDmaOwn[0]" = "Host_Owned" |
| 109 | register "PseDmaOwn[1]" = "Host_Owned" |
| 110 | register "pch_tsn_phy_irq_edge" = "RISING_EDGE" |
| 111 | register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE" |
| 112 | register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE" |
| 113 | |
| 114 | register "common_soc_config" = "{ |
| 115 | .i2c[1] = { |
| 116 | .speed = I2C_SPEED_STANDARD, |
| 117 | .speed_config[0] = { |
| 118 | .speed = I2C_SPEED_STANDARD, |
| 119 | .scl_hcnt = 0x1e1, |
| 120 | .scl_lcnt = 0x1f4, |
| 121 | .sda_hold = 0x64 |
| 122 | }, |
| 123 | }, |
| 124 | .i2c[2] = { |
| 125 | .speed = I2C_SPEED_STANDARD, |
| 126 | .speed_config[0] = { |
| 127 | .speed = I2C_SPEED_STANDARD, |
| 128 | .scl_hcnt = 0x1df, |
| 129 | .scl_lcnt = 0x1f4, |
| 130 | .sda_hold = 0x64 |
| 131 | }, |
| 132 | }, |
| 133 | }" |
| 134 | |
| 135 | # FIVR related settings |
| 136 | register "fivr" = "{ |
| 137 | .fivr_config_en = true, |
| 138 | .vcc_low_high_us = 50, |
| 139 | }" |
| 140 | |
| 141 | # Disable L1 prefetcher for real-time demands |
| 142 | register "L1_prefetcher_disable" = "true" |
| 143 | |
| 144 | device domain 0 on |
| 145 | device pci 00.0 on end # Host Bridge |
| 146 | device pci 02.0 on end # Integrated Graphics Device |
| 147 | |
| 148 | device pci 14.0 on end # USB3.1 xHCI |
| 149 | |
| 150 | device pci 15.0 on end # I2C0 |
| 151 | device pci 15.1 on # I2C1 |
| 152 | # Enable external RTC chip |
| 153 | chip drivers/i2c/rv3028c7 |
| 154 | register "bus_speed" = "I2C_SPEED_STANDARD" |
| 155 | register "set_user_date" = "1" |
| 156 | register "user_year" = "04" |
| 157 | register "user_month" = "07" |
| 158 | register "user_day" = "01" |
| 159 | register "user_weekday" = "4" |
| 160 | register "bckup_sw_mode" = "BACKUP_SW_LEVEL" |
| 161 | register "cap_charge" = "CHARGE_OFF" |
| 162 | device i2c 0x52 on end # RTC RV3028-C7 |
| 163 | end |
| 164 | end |
| 165 | device pci 15.2 on # I2C2 |
Jan Samek | d624453 | 2022-12-02 12:44:24 +0100 | [diff] [blame^] | 166 | # Enable external display bridge (eDP to LVDS) |
| 167 | chip drivers/i2c/ptn3460 |
| 168 | device i2c 0x20 on end # PTN3460 DP2LVDS Bridge |
| 169 | end |
| 170 | # Add dummy I2C device to limit BUS speed to 100 kHz in OS |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 171 | chip drivers/i2c/generic |
| 172 | register "hid" = ""PRP0001"" |
| 173 | register "speed" = "I2C_SPEED_STANDARD" |
| 174 | device i2c 0x7f on end |
| 175 | end |
| 176 | end |
| 177 | device pci 15.3 on end # I2C3 |
| 178 | |
| 179 | device pci 16.0 hidden end # Management Engine Interface 1 |
| 180 | |
| 181 | device pci 19.0 on end # I2C4 |
| 182 | device pci 19.1 on end # I2C5 |
| 183 | device pci 19.2 on end # UART2 |
| 184 | |
| 185 | device pci 1a.0 on end # eMMC |
| 186 | device pci 1a.1 on end # SD |
| 187 | |
Jan Samek | a1a8f58 | 2022-12-01 14:52:51 +0100 | [diff] [blame] | 188 | device pci 1c.1 on end # RP2 |
| 189 | device pci 1c.2 on end # RP3 |
| 190 | device pci 1c.4 on end # RP5 |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 191 | |
| 192 | device pci 1d.0 off end # Intel PSE IPC (local host to PSE) |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 193 | device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1 |
| 194 | # Enable external Marvell PHY 88E1512 |
| 195 | chip drivers/net/phy/m88e1512 |
| 196 | register "configure_leds" = "true" |
| 197 | # LED[0]: On - 1000 Mbps Link, Off - Else |
| 198 | register "led_0_ctrl" = "7" |
| 199 | # LED[1]: On - Link, Blink - Activity, Off - No Link |
| 200 | register "led_1_ctrl" = "1" |
| 201 | # INTn is routed to LED[2] pin |
| 202 | register "enable_int" = "true" |
| 203 | register "downshift_cnt" = "2" |
| 204 | device mdio 1 on # PHY address |
| 205 | ops m88e1512_ops |
| 206 | end |
| 207 | end |
| 208 | end |
| 209 | |
| 210 | device pci 1e.0 on end # UART0 |
| 211 | device pci 1e.1 on end # UART1 |
| 212 | device pci 1e.4 on # PCH Time-Sensitive Networking GbE |
| 213 | # Enable external Marvell PHY 88E1512 |
| 214 | chip drivers/net/phy/m88e1512 |
| 215 | register "configure_leds" = "true" |
| 216 | # LED[0]: On - 1000 Mbps Link, Off - Else |
| 217 | register "led_0_ctrl" = "7" |
| 218 | # LED[1]: On - Link, Blink - Activity, Off - No Link |
| 219 | register "led_1_ctrl" = "1" |
| 220 | # INTn is routed to LED[2] pin |
| 221 | register "enable_int" = "true" |
| 222 | register "downshift_cnt" = "2" |
| 223 | device mdio 1 on # PHY address |
| 224 | ops m88e1512_ops |
| 225 | end |
| 226 | end |
| 227 | end |
| 228 | |
| 229 | device pci 1f.0 on # eSPI Interface |
| 230 | chip drivers/pc80/tpm |
| 231 | device pnp 0c31.0 on end |
| 232 | end |
| 233 | end |
| 234 | device pci 1f.2 hidden end # Power Management Controller |
| 235 | device pci 1f.4 on end # SMBus |
| 236 | device pci 1f.5 on end # PCH SPI (flash & TPM) |
| 237 | end |
| 238 | end |