blob: e1538c67b6058f4101910175491d282116a2365a [file] [log] [blame]
Gaggery Tsai7130ca02018-07-31 15:55:54 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2018 Google Inc.
5 * Copyright (C) 2018 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <baseboard/variants.h>
18#include <chip.h>
19#include <device/device.h>
20#include <device/pci_ids.h>
21#include <device/pci_ops.h>
22
23#define PL2_AML 18
24#define PL2_KBL 15
25
26static uint32_t get_pl2(void)
27{
Kyösti Mälkki71756c212019-07-12 13:10:19 +030028 struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
Gaggery Tsai7130ca02018-07-31 15:55:54 -070029 uint16_t id;
Kyösti Mälkki71756c212019-07-12 13:10:19 +030030
31 id = pci_read_config16(igd_dev, PCI_DEVICE_ID);
Gaggery Tsai7130ca02018-07-31 15:55:54 -070032 /* Assume we only have KLB-Y and AML-Y SKUs */
33 if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM)
34 return PL2_KBL;
35
36 return PL2_AML;
37}
38
39/* Override dev tree settings per board */
40void variant_devtree_update(void)
41{
Kyösti Mälkkid5f645c2019-09-28 00:20:27 +030042 config_t *cfg = config_of_soc();
Gaggery Tsai7130ca02018-07-31 15:55:54 -070043
44 /* Update PL2 based on CPU */
45 cfg->tdp_pl2_override = get_pl2();
46}