Gitiles
Code Review Sign In
review.coreboot.org / coreboot / d5b0aeab2e7320d79f2f1aad24868a844c257413 / . / util / inteltool / gpio_names / icelake.h
blob: 95636d4a2830484222ffc43da07e1ba31e653a95 [file] [log] [blame]
Nicholas Chind5b0aea2023-10-24 18:30:51 -0600[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Johanna Schanderdca20cd2020-01-29 09:14:18 +0100[diff] [blame]3#ifndef GPIO_NAMES_ICELAKE_H
4#define GPIO_NAMES_ICELAKE_H
5
6#include "gpio_groups.h"
7
8static const char *const icelake_pch_h_group_g_names[] = {
9 /* GPP_G */
10 "GPP_G0", "SD3_CMD",
11 "GPP_G1", "SD3_D0",
12 "GPP_G2", "SD3_D1",
13 "GPP_G3", "SD3_D2",
14 "GPP_G4", "SD3_D3",
15 "GPP_G5", "SD3_CDB",
16 "GPP_G6", "SD3_CLK",
17 "GPP_G7", "SD3_WP",
18};
19
20static const char *const icelake_pch_h_group_b_names[] = {
21 /* GPP_B */
22 "GPP_B0", "CORE_VID_0",
23 "GPP_B1", "CORE_VID_1",
24 "GPP_B2", "VRALERTB",
25 "GPP_B3", "CPU_GP_2",
26 "GPP_B4", "CPU_GP_3",
27 "GPP_B5", "ISH_I2C0_SDA",
28 "GPP_B6", "ISH_I2C0_SCL",
29 "GPP_B7", "ISH_I2C1_SDA",
30 "GPP_B8", "ISH_I2C1_SCL",
31 "GPP_B9", "I2C5_SDA",
32 "GPP_B10", "I2C5_SCL",
33 "GPP_B11", "PMCALERTB",
34 "GPP_B12", "SLP_S0B",
35 "GPP_B13", "PLTRSTB",
36 "GPP_B14", "SPKR",
37 "GPP_B15", "GSPI0_CS0B",
38 "GPP_B16", "GSPI0_CLK",
39 "GPP_B17", "GSPI0_MISO",
40 "GPP_B18", "GSPI0_MOSI",
41 "GPP_B19", "GSPI1_CS0B",
42 "GPP_B20", "GSPI1_CLK",
43 "GPP_B21", "GSPI1_MISO",
44 "GPP_B22", "GSPI1_MOSI",
45 "GPP_B23", "SML1ALERTB",
46 "GPP_B24", "GSPI0_CLK_LOOPBK",
47 "GPP_B25", "GSPI1_CLK_LOOPBK",
48};
49
50static const char *const icelake_pch_h_group_a_names[] = {
51 /* GPP_A */
52 "GPP_A0", "ESPI_IO_0",
53 "GPP_A1", "ESPI_IO_1",
54 "GPP_A2", "ESPI_IO_2",
55 "GPP_A3", "ESPI_IO_3",
56 "GPP_A4", "ESPI_CSB",
57 "GPP_A5", "ESPI_CLK",
58 "GPP_A6", "ESPI_RESETB",
59 "GPP_A7", "I2S2_SCLK",
60 "GPP_A8", "I2S2_SFRM",
61 "GPP_A9", "I2S2_TXD",
62 "GPP_A10", "I2S2_RXD",
63 "GPP_A11", "SATA_DEVSLP_2",
64 "GPP_A12", "SATAXPCIE_1",
65 "GPP_A13", "SATAXPCIE_2",
66 "GPP_A14", "USB2_OCB_1",
67 "GPP_A15", "USB2_OCB_2",
68 "GPP_A16", "USB2_OCB_3",
69 "GPP_A17", "DDSP_HPD_C",
70 "GPP_A18", "DDSP_HPD_B",
71 "GPP_A19", "DDSP_HPD_1",
72 "GPP_A20", "DDSP_HPD_2",
73 "GPP_A21", "I2S5_TXD",
74 "GPP_A22", "I2S5_RXD",
75 "GPP_A23", "I2S1_SCLK",
76 "GPP_A24", "ESPI_CLK_LOOPBK",
77};
78
79static const char *const icelake_pch_h_group_h_names[] = {
80 /* GPP_H */
81 "GPP_H0", "SD_1P8_SEL",
82 "GPP_H1", "SD_PWR_EN_B",
83 "GPP_H2", "GPPC_H_2",
84 "GPP_H3", "SX_EXIT_HOLDOFFB",
85 "GPP_H4", "I2C2_SDA",
86 "GPP_H5", "I2C2_SCL",
87 "GPP_H6", "I2C3_SDA",
88 "GPP_H7", "I2C3_SCL",
89 "GPP_H8", "I2C4_SDA",
90 "GPP_H9", "I2C4_SCL",
91 "GPP_H10", "SRCCLKREQB_4",
92 "GPP_H11", "SRCCLKREQB_5",
93 "GPP_H12", "M2_SKT2_CFG_0",
94 "GPP_H13", "M2_SKT2_CFG_1",
95 "GPP_H14", "M2_SKT2_CFG_2",
96 "GPP_H15", "M2_SKT2_CFG_3",
97 "GPP_H16", "DDPB_CTRLCLK",
98 "GPP_H17", "DDPB_CTRLDATA",
99 "GPP_H18", "CPU_VCCIO_PWR_GATEB",
100 "GPP_H19", "TIME_SYNC_0",
101 "GPP_H20", "IMGCLKOUT_1",
102 "GPP_H21", "IMGCLKOUT_2",
103 "GPP_H22", "IMGCLKOUT_3",
104 "GPP_H23", "IMGCLKOUT_4",
105};
106
107static const char *const icelake_pch_h_group_d_names[] = {
108 /* GPP_D */
109 "GPP_D0", "ISH_GP_0",
110 "GPP_D1", "ISH_GP_1",
111 "GPP_D2", "ISH_GP_2",
112 "GPP_D3", "ISH_GP_3",
113 "GPP_D4", "IMGCLKOUT_0",
114 "GPP_D5", "SRCCLKREQB_0",
115 "GPP_D6", "SRCCLKREQB_1",
116 "GPP_D7", "SRCCLKREQB_2",
117 "GPP_D8", "SRCCLKREQB_3",
118 "GPP_D9", "ISH_SPI_CSB",
119 "GPP_D10", "ISH_SPI_CLK",
120 "GPP_D11", "ISH_SPI_MISO",
121 "GPP_D12", "ISH_SPI_MOSI",
122 "GPP_D13", "ISH_UART0_RXD",
123 "GPP_D14", "ISH_UART0_TXD",
124 "GPP_D15", "ISH_UART0_RTSB",
125 "GPP_D16", "ISH_UART0_CTSB",
126 "GPP_D17", "ISH_GP_4",
127 "GPP_D18", "ISH_GP_5",
128 "GPP_D19", "I2S_MCLK",
129 "GPP_D10", "GSPI2_CLK_LOOPBK",
130};
131
132static const char *const icelake_pch_h_group_f_names[] = {
133 /* GPP_F */
134 "GPP_F0", "CNV_BRI_DT",
135 "GPP_F1", "CNV_BRI_RSP",
136 "GPP_F2", "CNV_RGI_DT",
137 "GPP_F3", "CNV_RGI_RSP",
138 "GPP_F4", "CNV_RF_RESET_B",
139 "GPP_F5", "EMMC_HIP_MON",
140 "GPP_F6", "CNV_PA_BLANKING",
141 "GPP_F7", "EMMC_CMD",
142 "GPP_F8", "EMMC_DATA0",
143 "GPP_F9", "EMMC_DATA1",
144 "GPP_F10", "EMMC_DATA2",
145 "GPP_F11", "EMMC_DATA3",
146 "GPP_F12", "EMMC_DATA4",
147 "GPP_F13", "EMMC_DATA5",
148 "GPP_F14", "EMMC_DATA6",
149 "GPP_F15", "EMMC_DATA7",
150 "GPP_F16", "EMMC_RCLK",
151 "GPP_F17", "EMMC_CLK",
152 "GPP_F18", "EMMC_RESETB",
153 "GPP_F19", "A4WP_PRESENT",
154};
155
156static const char *const icelake_pch_h_group_vgpio_names[] = {
157 /* vGPIO */
158 "CNV_BTEN", "",
159 "CNV_WCEN", "",
160 "CNV_BT_HOST_WAKEB", "",
161 "CNV_BT_IF_SELECT", "",
162 "vCNV_BT_UART_TXD", "",
163 "vCNV_BT_UART_RXD", "",
164 "vCNV_BT_UART_CTS_B", "",
165 "vCNV_BT_UART_RTS_B", "",
166 "vCNV_MFUART1_TXD", "",
167 "vCNV_MFUART1_RXD", "",
168 "vCNV_MFUART1_CTS_B", "",
169 "vCNV_MFUART1_RTS_B", "",
170 "vUART0_TXD", "",
171 "vUART0_RXD", "",
172 "vUART0_CTS_B", "",
173 "vUART0_RTS_B", "",
174 "vISH_UART0_TXD", "",
175 "vISH_UART0_RXD", "",
176 "vISH_UART0_CTS_B", "",
177 "vISH_UART0_RTS_B", "",
178 "vCNV_BT_I2S_BCLK", "",
179 "vCNV_BT_I2S_WS_SYNC", "",
180 "vCNV_BT_I2S_SDO", "",
181 "vCNV_BT_I2S_SDI", "",
182 "vI2S2_SCLK", "",
183 "vI2S2_SFRM", "",
184 "vI2S2_TXD", "",
185 "vI2S2_RXD", "",
186 "vSD3_CD_B", "",
187};
188
189static const char *const icelake_pch_h_group_c_names[] = {
190 /* GPP_C */
191 "GPP_C0", "SMBCLK",
192 "GPP_C1", "SMBDATA",
193 "GPP_C2", "SMBALERTB",
194 "GPP_C3", "SML0CLK",
195 "GPP_C4", "SML0DATA",
196 "GPP_C5", "SML0ALERTB",
197 "GPP_C6", "SML1CLK",
198 "GPP_C7", "SML1DATA",
199 "GPP_C8", "UART0_RXD",
200 "GPP_C9", "UART0_TXD",
201 "GPP_C10", "UART0_RTSB",
202 "GPP_C11", "UART0_CTSB",
203 "GPP_C12", "UART1_RXD",
204 "GPP_C13", "UART1_TXD",
205 "GPP_C14", "UART1_RTSB",
206 "GPP_C15", "UART1_CTSB",
207 "GPP_C16", "I2C0_SDA",
208 "GPP_C17", "I2C0_SCL",
209 "GPP_C18", "I2C1_SDA",
210 "GPP_C19", "I2C1_SCL",
211 "GPP_C20", "UART2_RXD",
212 "GPP_C21", "UART2_TXD",
213 "GPP_C22", "UART2_RTSB",
214 "GPP_C23", "UART2_CTSB",
215};
216
217static const char *const icelake_pch_h_group_hvcmos_names[] = {
218 /* HVCMOS */
219 "L_BKLTEN", "",
220 "L_BKLTCTL", "",
221 "L_VDDEN", "",
222 "SYS_PWROK", "",
223 "SYS_RESETB", "",
224 "MLK_RSTB", "",
225};
226
227static const char *const icelake_pch_h_group_e_names[] = {
228 /* GPP_E */
229 "GPP_E0", "SATAXPCIE_0",
230 "GPP_E1", "SPI1_IO_2",
231 "GPP_E2", "SPI1_IO_3",
232 "GPP_E3", "CPU_GP_0",
233 "GPP_E4", "SATA_DEVSLP_0",
234 "GPP_E5", "SATA_DEVSLP_1",
235 "GPP_E6", "GPPC_E_6",
236 "GPP_E7", "CPU_GP_1",
237 "GPP_E8", "SATA_LEDB",
238 "GPP_E9", "USB2_OCB_0",
239 "GPP_E10", "SPI1_CSB",
240 "GPP_E11", "SPI1_CLK",
241 "GPP_E12", "SPI1_MISO_IO_1",
242 "GPP_E13", "SPI1_MOSI_IO_0",
243 "GPP_E14", "DDSP_HPD_A",
244 "GPP_E15", "ISH_GP_6",
245 "GPP_E16", "ISH_GP_7",
246 "GPP_E17", "DISP_MISC_4",
247 "GPP_E18", "DDP1_CTRLCLK",
248 "GPP_E19", "DDP1_CTRLDATA",
249 "GPP_E20", "DDP2_CTRLCLK",
250 "GPP_E21", "DDP2_CTRLDATA",
251 "GPP_E22", "DDPA_CTRLCLK",
252 "GPP_E23", "DDPA_CTRLDATA",
253};
254
255static const char *const icelake_pch_h_group_jtag_names[] = {
256 /* JTAG */
257 "JTAG0", "JTAG_TDO",
258 "JTAG1", "JTAGX",
259 "JTAG2", "PRDYB",
260 "JTAG3", "PREQB",
261 "JTAG4", "CPU_TRSTB",
262 "JTAG5", "JTAG_TDI",
263 "JTAG6", "JTAG_TMS",
264 "JTAG7", "JTAG_TCK",
265 "JTAG8", "ITP_PMODE",
266};
267
268static const char *const icelake_pch_h_group_r_names[] = {
269 /* GPP_R */
270 "GPP_R0", "HDA_BCLK",
271 "GPP_R1", "HDA_SYNC",
272 "GPP_R2", "HDA_SDO",
273 "GPP_R3", "HDA_SDI_0",
274 "GPP_R4", "HDA_RSTB",
275 "GPP_R5", "HDA_SDI_1",
276 "GPP_R6", "I2S1_TXD",
277 "GPP_R7", "I2S1_RXD",
278};
279
280static const char *const icelake_pch_h_group_s_names[] = {
281 /* GPP_S */
282 "GPP_S0", "SNDW1_CLK",
283 "GPP_S1", "SNDW1_DATA",
284 "GPP_S2", "SNDW2_CLK",
285 "GPP_S3", "SNDW2_DATA",
286 "GPP_S4", "SNDW3_CLK",
287 "GPP_S5", "SNDW3_DATA",
288 "GPP_S6", "SNDW4_CLK",
289 "GPP_S7", "SNDW4_DATA",
290};
291
292static const char *const icelake_pch_h_group_spi_names[] = {
293 /* SPI */
294 "SPIP0", "SPI0_IO_2",
295 "SPIP1", "SPI0_IO_3",
296 "SPIP2", "SPI0_MOSI_IO_0",
297 "SPIP3", "SPI0_MISO_IO_1",
298 "SPIP4", "SPI0_TPM_CSB",
299 "SPIP5", "SPI0_FLASH_0_CSB",
300 "SPIP6", "SPI0_FLASH_1_CSB",
301 "SPIP7", "SPI0_CLK",
302 "SPIP8", "SPI0_CLK_LOOPBK",
303};
304
305/* Ice Lake-LP */
306static const struct gpio_group icelake_pch_h_group_g = {
307 .display = "------- GPIO Group GPP_G -------",
308 .pad_count = ARRAY_SIZE(icelake_pch_h_group_g_names) / 2,
309 .func_count = 2,
310 .pad_names = icelake_pch_h_group_g_names,
311};
312
313static const struct gpio_group icelake_pch_h_group_b = {
314 .display = "------- GPIO Group GPP_B -------",
315 .pad_count = ARRAY_SIZE(icelake_pch_h_group_b_names) / 2,
316 .func_count = 2,
317 .pad_names = icelake_pch_h_group_b_names,
318};
319
320static const struct gpio_group icelake_pch_h_group_a = {
321 .display = "------- GPIO Group GPP_A -------",
322 .pad_count = ARRAY_SIZE(icelake_pch_h_group_a_names) / 2,
323 .func_count = 2,
324 .pad_names = icelake_pch_h_group_a_names,
325};
326
327static const struct gpio_group *const icelake_pch_h_community_0_groups[] = {
328 &icelake_pch_h_group_g,
329 &icelake_pch_h_group_b,
330 &icelake_pch_h_group_a,
331};
332
333static const struct gpio_community icelake_pch_h_community_0 = {
334 .name = "------- GPIO Community 0 -------",
335 .pcr_port_id = 0x6e,
336 .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups),
337 .groups = icelake_pch_h_community_0_groups,
338};
339
340static const struct gpio_group icelake_pch_h_group_h = {
341 .display = "------- GPIO Group GPP_H -------",
342 .pad_count = ARRAY_SIZE(icelake_pch_h_group_h_names) / 2,
343 .func_count = 2,
344 .pad_names = icelake_pch_h_group_h_names,
345};
346
347static const struct gpio_group icelake_pch_h_group_d = {
348 .display = "------- GPIO Group GPP_D -------",
349 .pad_count = ARRAY_SIZE(icelake_pch_h_group_d_names) / 2,
350 .func_count = 2,
351 .pad_names = icelake_pch_h_group_d_names,
352};
353
354static const struct gpio_group icelake_pch_h_group_f = {
355 .display = "------- GPIO Group GPP_F -------",
356 .pad_count = ARRAY_SIZE(icelake_pch_h_group_f_names) / 2,
357 .func_count = 2,
358 .pad_names = icelake_pch_h_group_f_names,
359};
360
361static const struct gpio_group icelake_pch_h_group_vgpio_0 = {
362 .display = "------- GPIO Group vGPIO_0 -------",
363 .pad_count = ARRAY_SIZE(icelake_pch_h_group_vgpio_names) / 2,
364 .func_count = 2,
365 .pad_names = icelake_pch_h_group_vgpio_names,
366};
367
368static const struct gpio_group *const icelake_pch_h_community_1_groups[] = {
369 &icelake_pch_h_group_h,
370 &icelake_pch_h_group_d,
371 &icelake_pch_h_group_f,
372 &icelake_pch_h_group_vgpio_0,
373};
374
375static const struct gpio_community icelake_pch_h_community_1 = {
376 .name = "------- GPIO Community 1 -------",
377 .pcr_port_id = 0x6d,
378 .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups),
379 .groups = icelake_pch_h_community_1_groups,
380};
381
382
383static const struct gpio_community icelake_pch_h_community_2 = {
384 .name = "------- GPIO Community 2 (skipped)-------",
385 .pcr_port_id = 0x6c,
386 .group_count = 0,
387};
388
389static const struct gpio_community icelake_pch_h_community_3 = {
390 .name = "------- GPIO Community 3 (skipped)-------",
391 .pcr_port_id = 0x6b,
392 .group_count = 0,
393};
394
395static const struct gpio_group icelake_pch_h_group_c = {
396 .display = "------- GPIO Group GPP_C -------",
397 .pad_count = ARRAY_SIZE(icelake_pch_h_group_c_names) / 2,
398 .func_count = 2,
399 .pad_names = icelake_pch_h_group_c_names,
400};
401
402static const struct gpio_group icelake_pch_h_group_hvcmos = {
403 .display = "------- GPIO Group HVCMOS -------",
404 .pad_count = ARRAY_SIZE(icelake_pch_h_group_hvcmos_names) / 2,
405 .func_count = 2,
406 .pad_names = icelake_pch_h_group_hvcmos_names,
407};
408
409static const struct gpio_group icelake_pch_h_group_e = {
410 .display = "------- GPIO Group E -------",
411 .pad_count = ARRAY_SIZE(icelake_pch_h_group_e_names) / 2,
412 .func_count = 2,
413 .pad_names = icelake_pch_h_group_e_names,
414};
415
416static const struct gpio_group icelake_pch_h_group_jtag = {
417 .display = "------- GPIO Group JTAG -------",
418 .pad_count = ARRAY_SIZE(icelake_pch_h_group_jtag_names) / 2,
419 .func_count = 2,
420 .pad_names = icelake_pch_h_group_jtag_names,
421};
422
423static const struct gpio_group *const icelake_pch_h_community_4_groups[] = {
424 &icelake_pch_h_group_c,
425 &icelake_pch_h_group_hvcmos,
426 &icelake_pch_h_group_e,
427 &icelake_pch_h_group_jtag,
428};
429
430static const struct gpio_community icelake_pch_h_community_4 = {
431 .name = "------- GPIO Community 4 -------",
432 .pcr_port_id = 0x6a,
433 .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups),
434 .groups = icelake_pch_h_community_4_groups,
435};
436
437static const struct gpio_group icelake_pch_h_group_r = {
438 .display = "------- GPIO Group R -------",
439 .pad_count = ARRAY_SIZE(icelake_pch_h_group_r_names) / 2,
440 .func_count = 2,
441 .pad_names = icelake_pch_h_group_r_names,
442};
443
444static const struct gpio_group icelake_pch_h_group_s = {
445 .display = "------- GPIO Group S -------",
446 .pad_count = ARRAY_SIZE(icelake_pch_h_group_s_names) / 2,
447 .func_count = 2,
448 .pad_names = icelake_pch_h_group_s_names,
449};
450
451static const struct gpio_group icelake_pch_h_group_spi = {
452 .display = "------- GPIO Group SPI -------",
453 .pad_count = ARRAY_SIZE(icelake_pch_h_group_spi_names) / 2,
454 .func_count = 2,
455 .pad_names = icelake_pch_h_group_spi_names,
456};
457
458static const struct gpio_group *const icelake_pch_h_community_5_groups[] = {
459 &icelake_pch_h_group_r,
460 &icelake_pch_h_group_s,
461 &icelake_pch_h_group_spi,
462};
463
464static const struct gpio_community icelake_pch_h_community_5 = {
465 .name = "------- GPIO Community 5 -------",
466 .pcr_port_id = 0x69,
467 .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups),
468 .groups = icelake_pch_h_community_5_groups,
469};
470
471static const struct gpio_community *const icelake_pch_h_communities[] = {
472 &icelake_pch_h_community_0,
473 &icelake_pch_h_community_1,
474 &icelake_pch_h_community_2,
475 &icelake_pch_h_community_3,
476 &icelake_pch_h_community_4,
477 &icelake_pch_h_community_5,
478};
479
480#endif