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review.coreboot.org / coreboot / d5b0aeab2e7320d79f2f1aad24868a844c257413 / . / util / inteltool / gpio_names / denverton.h
blob: 1ab2f268ee41b44cfe0c1a7ea38bcbab8ba11deb [file] [log] [blame]
Nicholas Chind5b0aea2023-10-24 18:30:51 -0600[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Johanna Schander7da602f2020-01-29 09:51:25 +0100[diff] [blame]3#ifndef GPIO_NAMES_DENVERTON_H
4#define GPIO_NAMES_DENVERTON_H
5
6#include "gpio_groups.h"
7
8static const char *const denverton_group_north_all_names[] = {
9 "NORTH_ALL_GBE0_SDP0",
10 "NORTH_ALL_GBE1_SDP0",
11 "NORTH_ALL_GBE0_SDP1",
12 "NORTH_ALL_GBE1_SDP1",
13 "NORTH_ALL_GBE0_SDP2",
14 "NORTH_ALL_GBE1_SDP2",
15 "NORTH_ALL_GBE0_SDP3",
16 "NORTH_ALL_GBE1_SDP3",
17 "NORTH_ALL_GBE2_LED0",
18 "NORTH_ALL_GBE2_LED1",
19 "NORTH_ALL_GBE0_I2C_CLK",
20 "NORTH_ALL_GBE0_I2C_DATA",
21 "NORTH_ALL_GBE1_I2C_CLK",
22 "NORTH_ALL_GBE1_I2C_DATA",
23 "NORTH_ALL_NCSI_RXD0",
24 "NORTH_ALL_NCSI_CLK_IN",
25 "NORTH_ALL_NCSI_RXD1",
26 "NORTH_ALL_NCSI_CRS_DV",
27 "NORTH_ALL_NCSI_ARB_IN",
28 "NORTH_ALL_NCSI_TX_EN",
29 "NORTH_ALL_NCSI_TXD0",
30 "NORTH_ALL_NCSI_TXD1",
31 "NORTH_ALL_NCSI_ARB_OUT",
32 "NORTH_ALL_GBE0_LED0",
33 "NORTH_ALL_GBE0_LED1",
34 "NORTH_ALL_GBE1_LED0",
35 "NORTH_ALL_GBE1_LED1",
36 "NORTH_ALL_GPIO_0",
37 "NORTH_ALL_PCIE_CLKREQ0_N",
38 "NORTH_ALL_PCIE_CLKREQ1_N",
39 "NORTH_ALL_PCIE_CLKREQ2_N",
40 "NORTH_ALL_PCIE_CLKREQ3_N",
41 "NORTH_ALL_PCIE_CLKREQ4_N",
42 "NORTH_ALL_GPIO_1",
43 "NORTH_ALL_GPIO_2",
44 "NORTH_ALL_SVID_ALERT_N",
45 "NORTH_ALL_SVID_DATA",
46 "NORTH_ALL_SVID_CLK",
47 "NORTH_ALL_THERMTRIP_N",
48 "NORTH_ALL_PROCHOT_N",
49 "NORTH_ALL_MEMHOT_N",
50};
51
52static const char *const denverton_group_south_dfx_names[] = {
53 "SOUTH_DFX_DFX_PORT_CLK0",
54 "SOUTH_DFX_DFX_PORT_CLK1",
55 "SOUTH_DFX_DFX_PORT0",
56 "SOUTH_DFX_DFX_PORT1",
57 "SOUTH_DFX_DFX_PORT2",
58 "SOUTH_DFX_DFX_PORT3",
59 "SOUTH_DFX_DFX_PORT4",
60 "SOUTH_DFX_DFX_PORT5",
61 "SOUTH_DFX_DFX_PORT6",
62 "SOUTH_DFX_DFX_PORT7",
63 "SOUTH_DFX_DFX_PORT8",
64 "SOUTH_DFX_DFX_PORT9",
65 "SOUTH_DFX_DFX_PORT10",
66 "SOUTH_DFX_DFX_PORT11",
67 "SOUTH_DFX_DFX_PORT12",
68 "SOUTH_DFX_DFX_PORT13",
69 "SOUTH_DFX_DFX_PORT14",
70 "SOUTH_DFX_DFX_PORT15",
71};
72
73static const char *const denverton_group_south_group0_names[] = {
74 "SOUTH_GROUP0_GPIO_12",
75 "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
76 "SOUTH_GROUP0_PCIE_CLKREQ5_N",
77 "SOUTH_GROUP0_PCIE_CLKREQ6_N",
78 "SOUTH_GROUP0_PCIE_CLKREQ7_N",
79 "SOUTH_GROUP0_UART0_RXD",
80 "SOUTH_GROUP0_UART0_TXD",
81 "SOUTH_GROUP0_SMB5_GBE_CLK",
82 "SOUTH_GROUP0_SMB5_GBE_DATA",
83 "SOUTH_GROUP0_ERROR2_N",
84 "SOUTH_GROUP0_ERROR1_N",
85 "SOUTH_GROUP0_ERROR0_N",
86 "SOUTH_GROUP0_IERR_N",
87 "SOUTH_GROUP0_MCERR_N",
88 "SOUTH_GROUP0_SMB0_LEG_CLK",
89 "SOUTH_GROUP0_SMB0_LEG_DATA",
90 "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
91 "SOUTH_GROUP0_SMB1_HOST_DATA",
92 "SOUTH_GROUP0_SMB1_HOST_CLK",
93 "SOUTH_GROUP0_SMB2_PECI_DATA",
94 "SOUTH_GROUP0_SMB2_PECI_CLK",
95 "SOUTH_GROUP0_SMB4_CSME0_DATA",
96 "SOUTH_GROUP0_SMB4_CSME0_CLK",
97 "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
98 "SOUTH_GROUP0_USB_OC0_N",
99 "SOUTH_GROUP0_FLEX_CLK_SE0",
100 "SOUTH_GROUP0_FLEX_CLK_SE1",
101 "SOUTH_GROUP0_GPIO_4",
102 "SOUTH_GROUP0_GPIO_5",
103 "SOUTH_GROUP0_GPIO_6",
104 "SOUTH_GROUP0_GPIO_7",
105 "SOUTH_GROUP0_SATA0_LED_N",
106 "SOUTH_GROUP0_SATA1_LED_N",
107 "SOUTH_GROUP0_SATA_PDETECT0",
108 "SOUTH_GROUP0_SATA_PDETECT1",
109 "SOUTH_GROUP0_SATA0_SDOUT",
110 "SOUTH_GROUP0_SATA1_SDOUT",
111 "SOUTH_GROUP0_UART1_RXD",
112 "SOUTH_GROUP0_UART1_TXD",
113 "SOUTH_GROUP0_GPIO_8",
114 "SOUTH_GROUP0_GPIO_9",
115 "SOUTH_GROUP0_TCK",
116 "SOUTH_GROUP0_TRST_N",
117 "SOUTH_GROUP0_TMS",
118 "SOUTH_GROUP0_TDI",
119 "SOUTH_GROUP0_TDO",
120 "SOUTH_GROUP0_CX_PRDY_N",
121 "SOUTH_GROUP0_CX_PREQ_N",
122 "SOUTH_GROUP0_CTBTRIGINOUT",
123 "SOUTH_GROUP0_CTBTRIGOUT",
124 "SOUTH_GROUP0_DFX_SPARE2",
125 "SOUTH_GROUP0_DFX_SPARE3",
126 "SOUTH_GROUP0_DFX_SPARE4",
127};
128
129static const char *const denverton_group_south_group1_names[] = {
130 "SOUTH_GROUP1_SUSPWRDNACK",
131 "SOUTH_GROUP1_PMU_SUSCLK",
132 "SOUTH_GROUP1_ADR_TRIGGER",
133 "SOUTH_GROUP1_PMU_SLP_S45_N",
134 "SOUTH_GROUP1_PMU_SLP_S3_N",
135 "SOUTH_GROUP1_PMU_WAKE_N",
136 "SOUTH_GROUP1_PMU_PWRBTN_N",
137 "SOUTH_GROUP1_PMU_RESETBUTTON_N",
138 "SOUTH_GROUP1_PMU_PLTRST_N",
139 "SOUTH_GROUP1_SUS_STAT_N",
140 "SOUTH_GROUP1_SLP_S0IX_N",
141 "SOUTH_GROUP1_SPI_CS0_N",
142 "SOUTH_GROUP1_SPI_CS1_N",
143 "SOUTH_GROUP1_SPI_MOSI_IO0",
144 "SOUTH_GROUP1_SPI_MISO_IO1",
145 "SOUTH_GROUP1_SPI_IO2",
146 "SOUTH_GROUP1_SPI_IO3",
147 "SOUTH_GROUP1_SPI_CLK",
148 "SOUTH_GROUP1_SPI_CLK_LOOPBK",
149 "SOUTH_GROUP1_ESPI_IO0",
150 "SOUTH_GROUP1_ESPI_IO1",
151 "SOUTH_GROUP1_ESPI_IO2",
152 "SOUTH_GROUP1_ESPI_IO3",
153 "SOUTH_GROUP1_ESPI_CS0_N",
154 "SOUTH_GROUP1_ESPI_CLK",
155 "SOUTH_GROUP1_ESPI_RST_N",
156 "SOUTH_GROUP1_ESPI_ALRT0_N",
157 "SOUTH_GROUP1_GPIO_10",
158 "SOUTH_GROUP1_GPIO_11",
159 "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
160 "SOUTH_GROUP1_EMMC_CMD",
161 "SOUTH_GROUP1_EMMC_STROBE",
162 "SOUTH_GROUP1_EMMC_CLK",
163 "SOUTH_GROUP1_EMMC_D0",
164 "SOUTH_GROUP1_EMMC_D1",
165 "SOUTH_GROUP1_EMMC_D2",
166 "SOUTH_GROUP1_EMMC_D3",
167 "SOUTH_GROUP1_EMMC_D4",
168 "SOUTH_GROUP1_EMMC_D5",
169 "SOUTH_GROUP1_EMMC_D6",
170 "SOUTH_GROUP1_EMMC_D7",
171 "SOUTH_GROUP1_GPIO_3",
172};
173
174
175static const struct gpio_group denverton_group_north_all = {
176 .display = "------- GPIO Group North All -------",
177 .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
178 .func_count = 1,
179 .pad_names = denverton_group_north_all_names,
180};
181
182static const struct gpio_group *const denverton_community_north_groups[] = {
183 &denverton_group_north_all,
184};
185
186static const struct gpio_community denverton_community_north = {
187 .name = "------- GPIO Community 0 -------",
188 .pcr_port_id = 0xc2,
189 .group_count = ARRAY_SIZE(denverton_community_north_groups),
190 .groups = denverton_community_north_groups,
191};
192
193static const struct gpio_group denverton_group_south_dfx = {
194 .display = "------- GPIO Group South DFX -------",
195 .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
196 .func_count = 1,
197 .pad_names = denverton_group_south_dfx_names,
198};
199
200static const struct gpio_group denverton_group_south_group0 = {
201 .display = "------- GPIO Group South Group0 -------",
202 .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
203 .func_count = 1,
204 .pad_names = denverton_group_south_group0_names,
205};
206
207static const struct gpio_group denverton_group_south_group1 = {
208 .display = "------- GPIO Group South Group1 -------",
209 .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
210 .func_count = 1,
211 .pad_names = denverton_group_south_group1_names,
212};
213
214static const struct gpio_group *const denverton_community_south_groups[] = {
215 &denverton_group_south_dfx,
216 &denverton_group_south_group0,
217 &denverton_group_south_group1,
218};
219
220static const struct gpio_community denverton_community_south = {
221 .name = "------- GPIO Community 1 -------",
222 .pcr_port_id = 0xc5,
223 .group_count = ARRAY_SIZE(denverton_community_south_groups),
224 .groups = denverton_community_south_groups,
225};
226
227static const struct gpio_community *const denverton_communities[] = {
228 &denverton_community_north, &denverton_community_south,
229};
230
231#endif