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review.coreboot.org / coreboot / d2f45c651694b2ada2443bb12def23e6c7910b10 / . / src / cpu / samsung / exynos5250 / Kconfig
blob: 63b46d64ed182d17edda899521c17800874896b1 [file] [log] [blame]
Stefan Reinauer3511b922013-06-19 12:02:47 -0700[diff] [blame]1config CPU_SAMSUNG_EXYNOS5250
2 depends on ARCH_ARMV7
3 select HAVE_MONOTONIC_TIMER
4 select HAVE_UART_SPECIAL
Stefan Reinauerd2f45c62013-06-19 13:42:00 -0700[diff] [blame^]5 select EARLY_CONSOLE
Stefan Reinauer3511b922013-06-19 12:02:47 -0700[diff] [blame]6 bool
7 default n
8
9if CPU_SAMSUNG_EXYNOS5250
10
David Hendricks694719a2013-01-11 11:34:06 -0800[diff] [blame]11config BOOTBLOCK_CPU_INIT
12 string
13 default "cpu/samsung/exynos5250/bootblock.c"
14 help
15 CPU/SoC-specific bootblock code. This is useful if the
16 bootblock must load microcode or copy data from ROM before
17 searching for the bootblock.
18
Hung-Te Lind63bddc2013-06-11 21:55:58 -0700[diff] [blame]19# ROM image layout.
20#
21# 0x0000: vendor-provided BL1 (8k).
22# 0x2000: bootblock
23# 0x2010-0x2090: reserved for CBFS master header.
24# 0xA000: Free for CBFS data.
25
26config BOOTBLOCK_ROM_OFFSET
27 hex
28 default 0x2000
29
30config CBFS_HEADER_ROM_OFFSET
31 hex "offset of master CBFS header in ROM"
32 default 0x2010
33
34config CBFS_ROM_OFFSET
35 # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
36 hex "offset of CBFS data in ROM"
37 default 0x0A000
38
David Hendricksb73d9042013-02-08 19:10:33 -0800[diff] [blame]39
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]40# Example SRAM/iRAM map for Exynos5250 platform:
41#
42# 0x0202_0000: vendor-provided BL1
43# 0x0202_3400: bootblock, assume up to 32KB in size
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]44# 0x0203_0000: romstage, assume up to 128KB in size.
David Hendricks882fdcf2013-02-14 16:41:54 -0800[diff] [blame]45# 0x0207_8000: stack pointer
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -0800[diff] [blame]46
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]47config BOOTBLOCK_BASE
David Hendricksf1dfb2e2012-12-27 13:50:32 -0800[diff] [blame]48 hex
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]49 default 0x02023400
50
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]51config ROMSTAGE_BASE
52 hex
53 default 0x02030000
54
55config ROMSTAGE_SIZE
56 hex
57 default 0x10000
58
David Hendricks882fdcf2013-02-14 16:41:54 -0800[diff] [blame]59# Stack may reside in either IRAM or DRAM. We will define it to live
60# at the top of IRAM for now.
61#
62# Stack grows downward, push operation stores register contents in
63# consecutive memory locations ending just below SP
64config STACK_TOP
65 hex
66 default 0x02078000
67
68config STACK_BOTTOM
69 hex
70 default 0x02077000
71
72config STACK_SIZE
73 hex
74 default 0x1000
75
Hung-Te Lin6fe0cab2013-01-22 18:57:56 +0800[diff] [blame]76# TODO We may probably move this to board-specific implementation files instead
77# of KConfig values.
78config CBFS_CACHE_ADDRESS
79 hex "memory address to put CBFS cache data"
80 default 0x02060000
81
82config CBFS_CACHE_SIZE
83 hex "size of CBFS cache data"
84 default 0x000017000
85
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]86config SYS_SDRAM_BASE
Ronald G. Minnich836fd192013-02-20 13:24:35 -0800[diff] [blame]87 hex
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]88 default 0x40000000
89
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]90config SYS_TEXT_BASE
Ronald G. Minnich836fd192013-02-20 13:24:35 -0800[diff] [blame]91 hex
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]92 default 0x43e00000
93
David Hendricks5d994632013-02-10 15:50:20 -0800[diff] [blame]94config COREBOOT_TABLES_SIZE
David Hendricks211a5d52013-01-17 20:52:21 -0800[diff] [blame]95 hex
Ronald G. Minnichb48605d2013-04-09 14:35:35 -0700[diff] [blame]96 default 0x4000000
Stefan Reinauer043eb0e2013-05-10 16:21:58 -0700[diff] [blame]97
98choice CONSOLE_SERIAL_UART_CHOICES
99 prompt "Serial Console UART"
100 default CONSOLE_SERIAL_UART3
101 depends on CONSOLE_SERIAL_UART
102
103config CONSOLE_SERIAL_UART0
104 bool "UART0"
105 help
106 Serial console on UART0
107
108config CONSOLE_SERIAL_UART1
109 bool "UART1"
110 help
111 Serial console on UART1
112
113config CONSOLE_SERIAL_UART2
114 bool "UART2"
115 help
116 Serial console on UART2
117
118config CONSOLE_SERIAL_UART3
119 bool "UART3"
120 help
121 Serial console on UART3
122
123endchoice
124
125config CONSOLE_SERIAL_UART_ADDRESS
126 hex
127 depends on CONSOLE_SERIAL_UART
128 default 0x12c00000 if CONSOLE_SERIAL_UART0
129 default 0x12c10000 if CONSOLE_SERIAL_UART1
130 default 0x12c20000 if CONSOLE_SERIAL_UART2
131 default 0x12c30000 if CONSOLE_SERIAL_UART3
132 help
133 Map the UART names to the respective MMIO address.
134
Stefan Reinauer3511b922013-06-19 12:02:47 -0700[diff] [blame]135endif