Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | This file is automatically generated. Please do NOT modify !!! |
| 30 | |
| 31 | **/ |
| 32 | |
| 33 | #ifndef __FSPSUPD_H__ |
| 34 | #define __FSPSUPD_H__ |
| 35 | |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 36 | #include <FspUpd.h> |
| 37 | |
| 38 | #pragma pack(push, 1) |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 39 | |
| 40 | |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 41 | #include <ConfigBlock/CpuConfigFspData.h> |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 42 | /// |
| 43 | /// Azalia Header structure |
| 44 | /// |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 45 | typedef struct { |
| 46 | UINT16 VendorId; ///< Codec Vendor ID |
| 47 | UINT16 DeviceId; ///< Codec Device ID |
| 48 | UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. |
| 49 | UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. |
| 50 | UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. |
| 51 | UINT32 Reserved; ///< Reserved for future use. Must be set to 0. |
| 52 | } AZALIA_HEADER; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 53 | |
| 54 | /// |
| 55 | /// Audio Azalia Verb Table structure |
| 56 | /// |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 57 | typedef struct { |
| 58 | AZALIA_HEADER Header; ///< AZALIA PCH header |
| 59 | UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header |
| 60 | } AUDIO_AZALIA_VERB_TABLE; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 61 | |
| 62 | /// |
| 63 | /// Refer to the definition of PCH_INT_PIN |
| 64 | /// |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 65 | typedef enum { |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 66 | SiPchNoInt, ///< No Interrupt Pin |
| 67 | SiPchIntA, |
| 68 | SiPchIntB, |
| 69 | SiPchIntC, |
| 70 | SiPchIntD |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 71 | } SI_PCH_INT_PIN; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 72 | /// |
| 73 | /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. |
| 74 | /// |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 75 | typedef struct { |
| 76 | UINT8 Device; ///< Device number |
| 77 | UINT8 Function; ///< Device function |
| 78 | UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) |
| 79 | UINT8 Irq; ///< IRQ to be set for device. |
| 80 | } SI_PCH_DEVICE_INTERRUPT_CONFIG; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 81 | |
| 82 | #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices |
| 83 | |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 84 | |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 85 | /** Fsp S Configuration |
| 86 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 87 | typedef struct { |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 88 | |
| 89 | /** Offset 0x0020 - Logo Pointer |
| 90 | Points to PEI Display Logo Image |
| 91 | 0 : 0 |
| 92 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 93 | UINT32 LogoPtr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 94 | |
| 95 | /** Offset 0x0024 - Logo Size |
| 96 | Size of PEI Display Logo Image |
| 97 | 0 : 0 |
| 98 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 99 | UINT32 LogoSize; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 100 | |
| 101 | /** Offset 0x0028 - Graphics Configuration Ptr |
| 102 | Points to VBT |
| 103 | 0 : 0 |
| 104 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 105 | UINT32 GraphicsConfigPtr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 106 | |
| 107 | /** Offset 0x002C - Enable Device 4 |
| 108 | Enable/disable Device 4 |
| 109 | $EN_DIS |
| 110 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 111 | UINT8 Device4Enable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 112 | |
| 113 | /** Offset 0x002D - Enable Intel HD Audio (Azalia) |
| 114 | Enable/disable Azalia controller. |
| 115 | $EN_DIS |
| 116 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 117 | UINT8 PchHdaEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 118 | |
| 119 | /** Offset 0x002E - Enable HD Audio DSP |
| 120 | Enable/disable HD Audio DSP feature. |
| 121 | $EN_DIS |
| 122 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 123 | UINT8 PchHdaDspEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 124 | |
| 125 | /** Offset 0x002F - Select HDAudio IoBuffer Ownership |
| 126 | Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / |
| 127 | I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link |
| 128 | owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 |
| 129 | of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports |
| 130 | own all the I/O buffers. |
| 131 | 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports |
| 132 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 133 | UINT8 PchHdaIoBufferOwnership; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 134 | |
| 135 | /** Offset 0x0030 - Enable CIO2 Controller |
| 136 | Enable/disable SKYCAM CIO2 Controller. |
| 137 | $EN_DIS |
| 138 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 139 | UINT8 PchCio2Enable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 140 | |
| 141 | /** Offset 0x0031 - Enable eMMC Controller |
| 142 | Enable/disable eMMC Controller. |
| 143 | $EN_DIS |
| 144 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 145 | UINT8 ScsEmmcEnabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 146 | |
| 147 | /** Offset 0x0032 - Enable eMMC HS400 Mode |
| 148 | Enable eMMC HS400 Mode. |
| 149 | $EN_DIS |
| 150 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 151 | UINT8 ScsEmmcHs400Enabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 152 | |
| 153 | /** Offset 0x0033 - Enable SdCard Controller |
| 154 | Enable/disable SD Card Controller. |
| 155 | $EN_DIS |
| 156 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 157 | UINT8 ScsSdCardEnabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 158 | |
| 159 | /** Offset 0x0034 - Enable PCH ISH Controller |
| 160 | Enable/disable ISH Controller. |
| 161 | $EN_DIS |
| 162 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 163 | UINT8 PchIshEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 164 | |
| 165 | /** Offset 0x0035 - Show SPI controller |
| 166 | Enable/disable to show SPI controller. |
| 167 | $EN_DIS |
| 168 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 169 | UINT8 ShowSpiController; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 170 | |
| 171 | /** Offset 0x0036 |
| 172 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 173 | UINT16 UnusedUpdSpace0; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 174 | |
| 175 | /** Offset 0x0038 - MicrocodeRegionBase |
| 176 | Memory Base of Microcode Updates |
| 177 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 178 | UINT32 MicrocodeRegionBase; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 179 | |
| 180 | /** Offset 0x003C - MicrocodeRegionSize |
| 181 | Size of Microcode Updates |
| 182 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 183 | UINT32 MicrocodeRegionSize; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 184 | |
| 185 | /** Offset 0x0040 - Turbo Mode |
| 186 | Enable/Disable Turbo mode. 0: disable, 1: enable |
| 187 | $EN_DIS |
| 188 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 189 | UINT8 TurboMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 190 | |
| 191 | /** Offset 0x0041 - Enable SATA SALP Support |
| 192 | Enable/disable SATA Aggressive Link Power Management. |
| 193 | $EN_DIS |
| 194 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 195 | UINT8 SataSalpSupport; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 196 | |
| 197 | /** Offset 0x0042 - Enable SATA ports |
| 198 | Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, |
| 199 | and so on. |
| 200 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 201 | UINT8 SataPortsEnable[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 202 | |
| 203 | /** Offset 0x004A - Enable SATA DEVSLP Feature |
| 204 | Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each |
| 205 | port, byte0 for port0, byte1 for port1, and so on. |
| 206 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 207 | UINT8 SataPortsDevSlp[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 208 | |
| 209 | /** Offset 0x0052 - Enable USB2 ports |
| 210 | Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for |
| 211 | port1, and so on. |
| 212 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 213 | UINT8 PortUsb20Enable[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 214 | |
| 215 | /** Offset 0x0062 - Enable USB3 ports |
| 216 | Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for |
| 217 | port1, and so on. |
| 218 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 219 | UINT8 PortUsb30Enable[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 220 | |
| 221 | /** Offset 0x006C - Enable xDCI controller |
| 222 | Enable/disable to xDCI controller. |
| 223 | $EN_DIS |
| 224 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 225 | UINT8 XdciEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 226 | |
| 227 | /** Offset 0x006D - Enable XHCI SSIC Eanble |
| 228 | Enable/disable XHCI SSIC port. |
| 229 | $EN_DIS |
| 230 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 231 | UINT8 SsicPortEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 232 | |
| 233 | /** Offset 0x006E |
| 234 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 235 | UINT8 UnusedUpdSpace1[1]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 236 | |
| 237 | /** Offset 0x006F - Enable SerialIo Device Mode |
| 238 | 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable |
| 239 | SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode |
| 240 | respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. |
| 241 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 242 | UINT8 SerialIoDevMode[11]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 243 | |
| 244 | /** Offset 0x007A - Address of PCH_DEVICE_INTERRUPT_CONFIG table. |
| 245 | The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. |
| 246 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 247 | UINT32 DevIntConfigPtr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 248 | |
| 249 | /** Offset 0x007E - Number of DevIntConfig Entry |
| 250 | Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr |
| 251 | must not be NULL. |
| 252 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 253 | UINT8 NumOfDevIntConfig; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 254 | |
| 255 | /** Offset 0x007F - PIRQx to IRQx Map Config |
| 256 | PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for |
| 257 | PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy |
| 258 | 8259 PCI mode. |
| 259 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 260 | UINT8 PxRcConfig[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 261 | |
| 262 | /** Offset 0x0087 - Select GPIO IRQ Route |
| 263 | GPIO IRQ Select. The valid value is 14 or 15. |
| 264 | 0 : 0xFF |
| 265 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 266 | UINT8 GpioIrqRoute; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 267 | |
| 268 | /** Offset 0x0088 - Select SciIrqSelect |
| 269 | SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. |
| 270 | 0 : 0xFF |
| 271 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 272 | UINT8 SciIrqSelect; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 273 | |
| 274 | /** Offset 0x0089 - Select TcoIrqSelect |
| 275 | TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. |
| 276 | 0 : 0xFF |
| 277 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 278 | UINT8 TcoIrqSelect; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 279 | |
| 280 | /** Offset 0x008A - Enable/Disable Tco IRQ |
| 281 | Enable/disable TCO IRQ |
| 282 | $EN_DIS |
| 283 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 284 | UINT8 TcoIrqEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 285 | |
| 286 | /** Offset 0x008B - PCH HDA Verb Table Entry Number |
| 287 | Number of Entries in Verb Table. |
| 288 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 289 | UINT8 PchHdaVerbTableEntryNum; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 290 | |
| 291 | /** Offset 0x008C - PCH HDA Verb Table Pointer |
| 292 | Pointer to Array of pointers to Verb Table. |
| 293 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 294 | UINT32 PchHdaVerbTablePtr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 295 | |
| 296 | /** Offset 0x0090 |
| 297 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 298 | UINT8 UnusedUpdSpace2; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 299 | |
| 300 | /** Offset 0x0091 - Enable SATA |
| 301 | Enable/disable SATA controller. |
| 302 | $EN_DIS |
| 303 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 304 | UINT8 SataEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 305 | |
| 306 | /** Offset 0x0092 - SATA Mode |
| 307 | Select SATA controller working mode. |
| 308 | 0:AHCI, 1:RAID |
| 309 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 310 | UINT8 SataMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 311 | |
| 312 | /** Offset 0x0093 - USB Per Port HS Preemphasis Bias |
| 313 | USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, |
| 314 | 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. |
| 315 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 316 | UINT8 Usb2AfePetxiset[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 317 | |
| 318 | /** Offset 0x00A3 - USB Per Port HS Transmitter Bias |
| 319 | USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, |
| 320 | 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. |
| 321 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 322 | UINT8 Usb2AfeTxiset[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 323 | |
| 324 | /** Offset 0x00B3 - USB Per Port HS Transmitter Emphasis |
| 325 | USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, |
| 326 | 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. |
| 327 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 328 | UINT8 Usb2AfePredeemp[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 329 | |
| 330 | /** Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis |
| 331 | USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. |
| 332 | One byte for each port. |
| 333 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 334 | UINT8 Usb2AfePehalfbit[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 335 | |
| 336 | /** Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment |
| 337 | Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value |
| 338 | in arrary can be between 0-1. One byte for each port. |
| 339 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 340 | UINT8 Usb3HsioTxDeEmphEnable[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 341 | |
| 342 | /** Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting |
| 343 | USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], |
| 344 | <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port. |
| 345 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 346 | UINT8 Usb3HsioTxDeEmph[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 347 | |
| 348 | /** Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment |
| 349 | Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value |
| 350 | in arrary can be between 0-1. One byte for each port. |
| 351 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 352 | UINT8 Usb3HsioTxDownscaleAmpEnable[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 353 | |
| 354 | /** Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment |
| 355 | USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default |
| 356 | = 00h</b>. One byte for each port. |
| 357 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 358 | UINT8 Usb3HsioTxDownscaleAmp[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 359 | |
| 360 | /** Offset 0x00FB - Enable LAN |
| 361 | Enable/disable LAN controller. |
| 362 | $EN_DIS |
| 363 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 364 | UINT8 PchLanEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 365 | |
| 366 | /** Offset 0x00FC |
| 367 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 368 | UINT8 UnusedUpdSpace3[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 369 | |
| 370 | /** Offset 0x0114 - Enable PCIE RP CLKREQ Support |
| 371 | Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for |
| 372 | each port, byte0 for port1, byte1 for port2, and so on. |
| 373 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 374 | UINT8 PcieRpClkReqSupport[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 375 | |
| 376 | /** Offset 0x012C - Configure CLKREQ Number |
| 377 | Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can |
| 378 | be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. |
| 379 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 380 | UINT8 PcieRpClkReqNumber[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 381 | |
| 382 | /** Offset 0x0144 |
| 383 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 384 | UINT8 UnusedUpdSpace4[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 385 | |
| 386 | /** Offset 0x0149 - HECI3 state |
| 387 | The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. |
| 388 | 0: disable, 1: enable |
| 389 | $EN_DIS |
| 390 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 391 | UINT8 Heci3Enabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 392 | |
| 393 | /** Offset 0x014A |
| 394 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 395 | UINT8 UnusedUpdSpace5[9]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 396 | |
| 397 | /** Offset 0x0153 - AMT Switch |
| 398 | Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. |
| 399 | $EN_DIS |
| 400 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 401 | UINT8 AmtEnabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 402 | |
| 403 | /** Offset 0x0154 - WatchDog Timer Switch |
| 404 | Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. |
| 405 | $EN_DIS |
| 406 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 407 | UINT8 WatchDog; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 408 | |
| 409 | /** Offset 0x0155 - ASF Switch |
| 410 | Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. |
| 411 | $EN_DIS |
| 412 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 413 | UINT8 AsfEnabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 414 | |
| 415 | /** Offset 0x0156 - Manageability Mode set by Mebx |
| 416 | Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. |
| 417 | $EN_DIS |
| 418 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 419 | UINT8 ManageabilityMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 420 | |
| 421 | /** Offset 0x0157 - PET Progress |
| 422 | Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive |
| 423 | PET Events. |
| 424 | $EN_DIS |
| 425 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 426 | UINT8 FwProgress; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 427 | |
| 428 | /** Offset 0x0158 - SOL Switch |
| 429 | Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx |
| 430 | $EN_DIS |
| 431 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 432 | UINT8 AmtSolEnabled; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 433 | |
| 434 | /** Offset 0x0159 - OS Timer |
| 435 | 16 bits Value, Set OS watchdog timer. |
| 436 | $EN_DIS |
| 437 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 438 | UINT16 WatchDogTimerOs; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 439 | |
| 440 | /** Offset 0x015B - BIOS Timer |
| 441 | 16 bits Value, Set BIOS watchdog timer. |
| 442 | $EN_DIS |
| 443 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 444 | UINT16 WatchDogTimerBios; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 445 | |
| 446 | /** Offset 0x015D |
| 447 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 448 | UINT8 UnusedUpdSpace6[163]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 449 | |
| 450 | /** Offset 0x0200 - Enable/Disable SA CRID |
| 451 | Enable: SA CRID, Disable (Default): SA CRID |
| 452 | $EN_DIS |
| 453 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 454 | UINT8 CridEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 455 | |
| 456 | /** Offset 0x0201 - Subsystem Vendor ID for SA devices |
| 457 | Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086 |
| 458 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 459 | UINT16 DefaultSvid; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 460 | |
| 461 | /** Offset 0x0203 - Subsystem Device ID for SA devices |
| 462 | Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015 |
| 463 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 464 | UINT16 DefaultSid; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 465 | |
| 466 | /** Offset 0x0205 - DMI ASPM |
| 467 | 0=Disable, 2(Default)=L1 |
| 468 | 0:Disable, 2:L1 |
| 469 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 470 | UINT8 DmiAspm; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 471 | |
| 472 | /** Offset 0x0206 - PCIe DeEmphasis control per root port |
| 473 | 0: -6dB, 1(Default): -3.5dB |
| 474 | 0:Disable, 2:L1 |
| 475 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 476 | UINT8 PegDeEmphasis[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 477 | |
| 478 | /** Offset 0x0209 - PCIe Slot Power Limit value per root port |
| 479 | Slot power limit value per root port |
| 480 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 481 | UINT8 PegSlotPowerLimitValue[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 482 | |
| 483 | /** Offset 0x020C - PCIe Slot Power Limit scale per root port |
| 484 | Slot power limit scale per root port |
| 485 | 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x |
| 486 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 487 | UINT8 PegSlotPowerLimitScale[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 488 | |
| 489 | /** Offset 0x020F - PCIe Physical Slot Number per root port |
| 490 | Physical Slot Number per root port |
| 491 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 492 | UINT16 PegPhysicalSlotNumber[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 493 | |
| 494 | /** Offset 0x0215 - Enable/Disable PavpEnable |
| 495 | Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable |
| 496 | $EN_DIS |
| 497 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 498 | UINT8 PavpEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 499 | |
| 500 | /** Offset 0x0216 - CdClock Frequency selection |
| 501 | 0=308.57 Mhz, 1=337.5 Mhz, 2=432 Mhz, 3=450 Mhz, 4=540 Mhz, 5=617.14 Mhz, 6(Default)= 675 Mhz |
| 502 | 0: 308.57 Mhz, 1: 337.5 Mhz, 2: 432 Mhz, 3: 450 Mhz, 4: 540 Mhz, 5: 617.14 Mhz, |
| 503 | 6: 675 Mhz |
| 504 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 505 | UINT8 CdClock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 506 | |
| 507 | /** Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit |
| 508 | Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit |
| 509 | $EN_DIS |
| 510 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 511 | UINT8 PeiGraphicsPeimInit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 512 | |
| 513 | /** Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) |
| 514 | Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) |
| 515 | $EN_DIS |
| 516 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 517 | UINT8 SaImguEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 518 | |
| 519 | /** Offset 0x0219 - Enable or disable GMM device |
| 520 | 0=Disable, 1(Default)=Enable |
| 521 | $EN_DIS |
| 522 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 523 | UINT8 GmmEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 524 | |
| 525 | /** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table |
| 526 | 0=Disable/Clear, 1(Default)=Enable/Set |
| 527 | $EN_DIS |
| 528 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 529 | UINT8 X2ApicOptOut; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 530 | |
| 531 | /** Offset 0x021B - Base addresses for VT-d function MMIO access |
| 532 | Base addresses for VT-d MMIO access per VT-d engine |
| 533 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 534 | UINT32 VtdBaseAddress[2]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 535 | |
| 536 | /** Offset 0x0223 |
| 537 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 538 | UINT8 UnusedUpdSpace7[20]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 539 | |
| 540 | /** Offset 0x0237 - SaPostMemProductionRsvd |
| 541 | Reserved for SA Post-Mem Production |
| 542 | $EN_DIS |
| 543 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 544 | UINT8 SaPostMemProductionRsvd[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 545 | |
| 546 | /** Offset 0x0247 |
| 547 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 548 | UINT8 UnusedUpdSpace8[7]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 549 | |
| 550 | /** Offset 0x024E - Power State 3 enable/disable |
| 551 | PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>. |
| 552 | For all VR Indexes |
| 553 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 554 | UINT8 Psi3Enable[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 555 | |
| 556 | /** Offset 0x0253 - Power State 4 enable/disable |
| 557 | PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For |
| 558 | all VR Indexes |
| 559 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 560 | UINT8 Psi4Enable[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 561 | |
| 562 | /** Offset 0x0258 - Imon slope correction |
| 563 | PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. |
| 564 | Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes |
| 565 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 566 | UINT8 ImonSlope[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 567 | |
| 568 | /** Offset 0x025D - Imon offset correction |
| 569 | PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. |
| 570 | Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b> |
| 571 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 572 | UINT8 ImonOffset[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 573 | |
| 574 | /** Offset 0x0262 - Enable/Disable BIOS configuration of VR |
| 575 | Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes |
| 576 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 577 | UINT8 VrConfigEnable[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 578 | |
| 579 | /** Offset 0x0267 - Thermal Design Current enable/disable |
| 580 | PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: |
| 581 | Enable.For all VR Indexes |
| 582 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 583 | UINT8 TdcEnable[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 584 | |
| 585 | /** Offset 0x026C - HECI3 state |
| 586 | PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. |
| 587 | Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms |
| 588 | , 8 - 8ms , 10 - 10ms.For all VR Indexe |
| 589 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 590 | UINT8 TdcTimeWindow[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 591 | |
| 592 | /** Offset 0x0271 - Thermal Design Current Lock |
| 593 | PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For |
| 594 | all VR Indexes |
| 595 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 596 | UINT8 TdcLock[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 597 | |
| 598 | /** Offset 0x0276 - Platform Psys slope correction |
| 599 | PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in |
| 600 | 1/100 increment values. Range is 0-200. 125 = 1.25 |
| 601 | 0x0:0xFF |
| 602 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 603 | UINT8 PsysSlope; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 604 | |
| 605 | /** Offset 0x0277 - Platform Psys offset correction |
| 606 | PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4, |
| 607 | Range 0-255. Value of 100 = 100/4 = 25 offset |
| 608 | 0x0:0xFF |
| 609 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 610 | UINT8 PsysOffset; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 611 | |
| 612 | /** Offset 0x0278 - Acoustic Noise Mitigation feature |
| 613 | Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled |
| 614 | 0x0:0xFF |
| 615 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 616 | UINT8 AcousticNoiseMitigation; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 617 | |
| 618 | /** Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain |
| 619 | Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation |
| 620 | feature enabled. <b>0: False</b>; 1: True |
| 621 | 0x0:0xFF |
| 622 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 623 | UINT8 FastPkgCRampDisableIa; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 624 | |
| 625 | /** Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain |
| 626 | Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic |
| 627 | Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 |
| 628 | 0x0:0xFF |
| 629 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 630 | UINT8 SlowSlewRateForIa; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 631 | |
| 632 | /** Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain |
| 633 | Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic |
| 634 | Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 |
| 635 | 0x0:0xFF |
| 636 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 637 | UINT8 SlowSlewRateForGt; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 638 | |
| 639 | /** Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain |
| 640 | Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic |
| 641 | Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 |
| 642 | 0x0:0xFF |
| 643 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 644 | UINT8 SlowSlewRateForSa; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 645 | |
| 646 | /** Offset 0x027D |
| 647 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 648 | UINT8 UnusedUpdSpace9[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 649 | |
| 650 | /** Offset 0x0285 - Thermal Design Current current limit |
| 651 | PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. |
| 652 | Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes |
| 653 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 654 | UINT16 TdcPowerLimit[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 655 | |
| 656 | /** Offset 0x028F |
| 657 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 658 | UINT8 UnusedUpdSpace10[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 659 | |
| 660 | /** Offset 0x0299 - AcLoadline |
| 661 | PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is |
| 662 | 0-6249. <b>Intel Recommended Defaults vary by domain and SKU. |
| 663 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 664 | UINT16 AcLoadline[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 665 | |
| 666 | /** Offset 0x02A3 - DcLoadline |
| 667 | PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is |
| 668 | 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b> |
| 669 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 670 | UINT16 DcLoadline[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 671 | |
| 672 | /** Offset 0x02AD - Power State 1 Threshold current |
| 673 | PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is |
| 674 | 0-128A. Default Value = 20A. |
| 675 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 676 | UINT16 Psi1Threshold[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 677 | |
| 678 | /** Offset 0x02B7 - Power State 2 Threshold current |
| 679 | PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is |
| 680 | 0-128A. Default Value = 5A. |
| 681 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 682 | UINT16 Psi2Threshold[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 683 | |
| 684 | /** Offset 0x02C1 - Power State 3 Threshold current |
| 685 | PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is |
| 686 | 0-128A. Default Value = 1A. |
| 687 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 688 | UINT16 Psi3Threshold[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 689 | |
| 690 | /** Offset 0x02CB - Icc Max limit |
| 691 | PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A |
| 692 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 693 | UINT16 IccMax[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 694 | |
| 695 | /** Offset 0x02D5 - VR Voltage Limit |
| 696 | PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. |
| 697 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 698 | UINT16 VrVoltageLimit[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 699 | |
| 700 | /** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain |
| 701 | Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation |
| 702 | feature enabled. <b>0: False</b>; 1: True |
| 703 | 0x0:0xFF |
| 704 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 705 | UINT8 FastPkgCRampDisableGt; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 706 | |
| 707 | /** Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain |
| 708 | Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation |
| 709 | feature enabled. <b>0: False</b>; 1: True |
| 710 | 0x0:0xFF |
| 711 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 712 | UINT8 FastPkgCRampDisableSa; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 713 | |
| 714 | /** Offset 0x02E1 |
| 715 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 716 | UINT8 UnusedUpdSpace11; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 717 | |
| 718 | /** Offset 0x02E2 - Enable VR specific mailbox command |
| 719 | VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A |
| 720 | VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific |
| 721 | command sent for PS4 exit issue. 11b - Reserved. |
| 722 | $EN_DIS |
| 723 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 724 | UINT8 SendVrMbxCmd; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 725 | |
| 726 | /** Offset 0x02E3 - Select VR specific mailbox command to send |
| 727 | VR specific mailbox commands. <b>000b - no VR specific command sent.</b> 001b - |
| 728 | VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific |
| 729 | command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue. |
| 730 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 731 | UINT8 SendVrMbxCmd1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 732 | |
| 733 | /** Offset 0x02E4 |
| 734 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 735 | UINT8 UnusedUpdSpace12; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 736 | |
| 737 | /** Offset 0x02E5 - CpuS3ResumeMtrrData |
| 738 | Pointer CPU S3 Resume MTRR Data |
| 739 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 740 | UINT32 CpuS3ResumeMtrrData; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 741 | |
| 742 | /** Offset 0x02E9 - CpuS3ResumeMtrrDataSize |
| 743 | Size of S3 resume MTRR data. |
| 744 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 745 | UINT16 CpuS3ResumeMtrrDataSize; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 746 | |
| 747 | /** Offset 0x02EB |
| 748 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 749 | UINT8 UnusedUpdSpace13[2]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 750 | |
| 751 | /** Offset 0x02ED - Cpu Configuration |
| 752 | Size of S3 resume MTRR data. |
| 753 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 754 | CPU_CONFIG_FSP_DATA CpuConfig; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 755 | |
| 756 | /** Offset 0x02F9 |
| 757 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 758 | UINT16 UnusedUpdSpace14; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 759 | |
| 760 | /** Offset 0x02FB - Enable SkyCam PortA Termination override |
| 761 | Enable/disable PortA Termination override. |
| 762 | $EN_DIS |
| 763 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 764 | UINT8 PchSkyCamPortATermOvrEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 765 | |
| 766 | /** Offset 0x02FC - Enable SkyCam PortB Termination override |
| 767 | Enable/disable PortB Termination override. |
| 768 | $EN_DIS |
| 769 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 770 | UINT8 PchSkyCamPortBTermOvrEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 771 | |
| 772 | /** Offset 0x02FD - Enable SkyCam PortC Termination override |
| 773 | Enable/disable PortC Termination override. |
| 774 | $EN_DIS |
| 775 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 776 | UINT8 PchSkyCamPortCTermOvrEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 777 | |
| 778 | /** Offset 0x02FE - Enable SkyCam PortD Termination override |
| 779 | Enable/disable PortD Termination override. |
| 780 | $EN_DIS |
| 781 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 782 | UINT8 PchSkyCamPortDTermOvrEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 783 | |
| 784 | /** Offset 0x02FF - Enable SkyCam PortA Clk Trim |
| 785 | Enable/disable PortA Clk Trim. |
| 786 | $EN_DIS |
| 787 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 788 | UINT8 PchSkyCamPortATrimEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 789 | |
| 790 | /** Offset 0x0300 - Enable SkyCam PortB Clk Trim |
| 791 | Enable/disable PortB Clk Trim. |
| 792 | $EN_DIS |
| 793 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 794 | UINT8 PchSkyCamPortBTrimEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 795 | |
| 796 | /** Offset 0x0301 - Enable SkyCam PortC Clk Trim |
| 797 | Enable/disable PortC Clk Trim. |
| 798 | $EN_DIS |
| 799 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 800 | UINT8 PchSkyCamPortCTrimEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 801 | |
| 802 | /** Offset 0x0302 - Enable SkyCam PortD Clk Trim |
| 803 | Enable/disable PortD Clk Trim. |
| 804 | $EN_DIS |
| 805 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 806 | UINT8 PchSkyCamPortDTrimEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 807 | |
| 808 | /** Offset 0x0303 - Enable SkyCam PortA Ctle |
| 809 | Enable/disable PortA Ctle. |
| 810 | $EN_DIS |
| 811 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 812 | UINT8 PchSkyCamPortACtleEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 813 | |
| 814 | /** Offset 0x0304 - Enable SkyCam PortB Ctle |
| 815 | Enable/disable PortB Ctle. |
| 816 | $EN_DIS |
| 817 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 818 | UINT8 PchSkyCamPortBCtleEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 819 | |
| 820 | /** Offset 0x0305 - Enable SkyCam PortCD Ctle |
| 821 | Enable/disable PortCD Ctle. |
| 822 | $EN_DIS |
| 823 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 824 | UINT8 PchSkyCamPortCDCtleEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 825 | |
| 826 | /** Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value |
| 827 | Enable/disable PortA Ctle Cap Value. |
| 828 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 829 | UINT8 PchSkyCamPortACtleCapValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 830 | |
| 831 | /** Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value |
| 832 | Enable/disable PortB Ctle Cap Value. |
| 833 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 834 | UINT8 PchSkyCamPortBCtleCapValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 835 | |
| 836 | /** Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value |
| 837 | Enable/disable PortCD Ctle Cap Value. |
| 838 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 839 | UINT8 PchSkyCamPortCDCtleCapValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 840 | |
| 841 | /** Offset 0x0309 - Enable SkyCam PortA Ctle Res Value |
| 842 | Enable/disable PortA Ctle Res Value. |
| 843 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 844 | UINT8 PchSkyCamPortACtleResValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 845 | |
| 846 | /** Offset 0x030A - Enable SkyCam PortB Ctle Res Value |
| 847 | Enable/disable PortB Ctle Res Value. |
| 848 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 849 | UINT8 PchSkyCamPortBCtleResValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 850 | |
| 851 | /** Offset 0x030B - Enable SkyCam PortCD Ctle Res Value |
| 852 | Enable/disable PortCD Ctle Res Value. |
| 853 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 854 | UINT8 PchSkyCamPortCDCtleResValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 855 | |
| 856 | /** Offset 0x030C - Enable SkyCam PortA Clk Trim Value |
| 857 | Enable/disable PortA Clk Trim Value. |
| 858 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 859 | UINT8 PchSkyCamPortAClkTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 860 | |
| 861 | /** Offset 0x030D - Enable SkyCam PortB Clk Trim Value |
| 862 | Enable/disable PortB Clk Trim Value. |
| 863 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 864 | UINT8 PchSkyCamPortBClkTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 865 | |
| 866 | /** Offset 0x030E - Enable SkyCam PortC Clk Trim Value |
| 867 | Enable/disable PortC Clk Trim Value. |
| 868 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 869 | UINT8 PchSkyCamPortCClkTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 870 | |
| 871 | /** Offset 0x030F - Enable SkyCam PortD Clk Trim Value |
| 872 | Enable/disable PortD Clk Trim Value. |
| 873 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 874 | UINT8 PchSkyCamPortDClkTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 875 | |
| 876 | /** Offset 0x0310 - Enable SkyCam Port A Data Trim Value |
| 877 | Enable/disable Port A Data Trim Value. |
| 878 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 879 | UINT16 PchSkyCamPortADataTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 880 | |
| 881 | /** Offset 0x0312 - Enable SkyCam Port B Data Trim Value |
| 882 | Enable/disable Port B Data Trim Value. |
| 883 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 884 | UINT16 PchSkyCamPortBDataTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 885 | |
| 886 | /** Offset 0x0314 - Enable SkyCam C/D Data Trim Value |
| 887 | Enable/disable C/D Data Trim Value. |
| 888 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 889 | UINT16 PchSkyCamPortCDDataTrimValue; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 890 | |
| 891 | /** Offset 0x0316 - Enable DMI ASPM |
| 892 | ASPM on PCH side of the DMI Link. |
| 893 | $EN_DIS |
| 894 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 895 | UINT8 PchDmiAspm; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 896 | |
| 897 | /** Offset 0x0317 - Enable Power Optimizer |
| 898 | Enable DMI Power Optimizer on PCH side. |
| 899 | $EN_DIS |
| 900 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 901 | UINT8 PchPwrOptEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 902 | |
| 903 | /** Offset 0x0318 - PCH Flash Protection Ranges Write Enble |
| 904 | Write or erase is blocked by hardware. |
| 905 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 906 | UINT8 PchWriteProtectionEnable[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 907 | |
| 908 | /** Offset 0x031D - PCH Flash Protection Ranges Read Enble |
| 909 | Read is blocked by hardware. |
| 910 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 911 | UINT8 PchReadProtectionEnable[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 912 | |
| 913 | /** Offset 0x0322 - PCH Protect Range Limit |
| 914 | Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for |
| 915 | limit comparison. |
| 916 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 917 | UINT16 PchProtectedRangeLimit[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 918 | |
| 919 | /** Offset 0x032C - PCH Protect Range Base |
| 920 | Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. |
| 921 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 922 | UINT16 PchProtectedRangeBase[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 923 | |
| 924 | /** Offset 0x0336 - Enable Pme |
| 925 | Enable Azalia wake-on-ring. |
| 926 | $EN_DIS |
| 927 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 928 | UINT8 PchHdaPme; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 929 | |
| 930 | /** Offset 0x0337 - IO Buffer Voltage |
| 931 | I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V. |
| 932 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 933 | UINT8 PchHdaIoBufferVoltage; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 934 | |
| 935 | /** Offset 0x0338 - VC Type |
| 936 | Virtual Channel Type Select: 0: VC0, 1: VC1. |
| 937 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 938 | UINT8 PchHdaVcType; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 939 | |
| 940 | /** Offset 0x0339 - HD Audio Link Frequency |
| 941 | HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz. |
| 942 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 943 | UINT8 PchHdaLinkFrequency; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 944 | |
| 945 | /** Offset 0x033A - iDisp-Link Frequency |
| 946 | iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. |
| 947 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 948 | UINT8 PchHdaIDispLinkFrequency; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 949 | |
| 950 | /** Offset 0x033B - iDisp-Link T-mode |
| 951 | iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. |
| 952 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 953 | UINT8 PchHdaIDispLinkTmode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 954 | |
| 955 | /** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system |
| 956 | 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox |
| 957 | driver or SST driver supported). |
| 958 | $EN_DIS |
| 959 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 960 | UINT8 PchHdaDspUaaCompliance; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 961 | |
| 962 | /** Offset 0x033D - iDisplay Audio Codec disconnection |
| 963 | 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. |
| 964 | $EN_DIS |
| 965 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 966 | UINT8 PchHdaIDispCodecDisconnect; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 967 | |
| 968 | /** Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) |
| 969 | 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array. |
| 970 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 971 | UINT8 PchHdaDspEndpointDmic; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 972 | |
| 973 | /** Offset 0x033F - DSP Bluetooth enablement |
| 974 | 0: Disable; 1: Enable. |
| 975 | $EN_DIS |
| 976 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 977 | UINT8 PchHdaDspEndpointBluetooth; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 978 | |
| 979 | /** Offset 0x0340 - DSP I2S enablement |
| 980 | 0: Disable; 1: Enable. |
| 981 | $EN_DIS |
| 982 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 983 | UINT8 PchHdaDspEndpointI2s; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 984 | |
| 985 | /** Offset 0x0341 - Bitmask of supported DSP features |
| 986 | [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] |
| 987 | - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: |
| 988 | Intel WoV, 1: Windows Voice Activation. |
| 989 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 990 | UINT32 PchHdaDspFeatureMask; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 991 | |
| 992 | /** Offset 0x0345 - Bitmask of supported DSP Pre/Post-Processing Modules |
| 993 | Deprecated: Specific pre/post-processing module bit position must be coherent with |
| 994 | the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing |
| 995 | Module Support. |
| 996 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 997 | UINT32 PchHdaDspPpModuleMask; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 998 | |
| 999 | /** Offset 0x0349 - Enable PCH Io Apic |
| 1000 | Set to 1 if BDF value is valid. |
| 1001 | $EN_DIS |
| 1002 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1003 | UINT8 PchIoApicBdfValid; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1004 | |
| 1005 | /** Offset 0x034A - PCH Io Apic Bus Number |
| 1006 | Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. |
| 1007 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1008 | UINT8 PchIoApicBusNumber; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1009 | |
| 1010 | /** Offset 0x034B - PCH Io Apic Device Number |
| 1011 | Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. |
| 1012 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1013 | UINT8 PchIoApicDeviceNumber; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1014 | |
| 1015 | /** Offset 0x034C - PCH Io Apic Function Number |
| 1016 | Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. |
| 1017 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1018 | UINT8 PchIoApicFunctionNumber; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1019 | |
| 1020 | /** Offset 0x034D - Enable PCH Io Apic Entry 24-119 |
| 1021 | 0: Disable; 1: Enable. |
| 1022 | $EN_DIS |
| 1023 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1024 | UINT8 PchIoApicEntry24_119; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1025 | |
| 1026 | /** Offset 0x034E - PCH Io Apic ID |
| 1027 | This member determines IOAPIC ID. Default is 0x02. |
| 1028 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1029 | UINT8 PchIoApicId; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1030 | |
| 1031 | /** Offset 0x034F - PCH Io Apic Range Select |
| 1032 | Define address bits 19:12 for the IOxAPIC range. Default is 0. |
| 1033 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1034 | UINT8 PchIoApicRangeSelect; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1035 | |
| 1036 | /** Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned |
| 1037 | 0: Disable; 1: Enable. |
| 1038 | $EN_DIS |
| 1039 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1040 | UINT8 PchIshSpiGpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1041 | |
| 1042 | /** Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned |
| 1043 | 0: Disable; 1: Enable. |
| 1044 | $EN_DIS |
| 1045 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1046 | UINT8 PchIshUart0GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1047 | |
| 1048 | /** Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned |
| 1049 | 0: Disable; 1: Enable. |
| 1050 | $EN_DIS |
| 1051 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1052 | UINT8 PchIshUart1GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1053 | |
| 1054 | /** Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned |
| 1055 | 0: Disable; 1: Enable. |
| 1056 | $EN_DIS |
| 1057 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1058 | UINT8 PchIshI2c0GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1059 | |
| 1060 | /** Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned |
| 1061 | 0: Disable; 1: Enable. |
| 1062 | $EN_DIS |
| 1063 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1064 | UINT8 PchIshI2c1GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1065 | |
| 1066 | /** Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned |
| 1067 | 0: Disable; 1: Enable. |
| 1068 | $EN_DIS |
| 1069 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1070 | UINT8 PchIshI2c2GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1071 | |
| 1072 | /** Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned |
| 1073 | 0: Disable; 1: Enable. |
| 1074 | $EN_DIS |
| 1075 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1076 | UINT8 PchIshGp0GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1077 | |
| 1078 | /** Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned |
| 1079 | 0: Disable; 1: Enable. |
| 1080 | $EN_DIS |
| 1081 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1082 | UINT8 PchIshGp1GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1083 | |
| 1084 | /** Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned |
| 1085 | 0: Disable; 1: Enable. |
| 1086 | $EN_DIS |
| 1087 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1088 | UINT8 PchIshGp2GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1089 | |
| 1090 | /** Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned |
| 1091 | 0: Disable; 1: Enable. |
| 1092 | $EN_DIS |
| 1093 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1094 | UINT8 PchIshGp3GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1095 | |
| 1096 | /** Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned |
| 1097 | 0: Disable; 1: Enable. |
| 1098 | $EN_DIS |
| 1099 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1100 | UINT8 PchIshGp4GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1101 | |
| 1102 | /** Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned |
| 1103 | 0: Disable; 1: Enable. |
| 1104 | $EN_DIS |
| 1105 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1106 | UINT8 PchIshGp5GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1107 | |
| 1108 | /** Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned |
| 1109 | 0: Disable; 1: Enable. |
| 1110 | $EN_DIS |
| 1111 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1112 | UINT8 PchIshGp6GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1113 | |
| 1114 | /** Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned |
| 1115 | 0: Disable; 1: Enable. |
| 1116 | $EN_DIS |
| 1117 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1118 | UINT8 PchIshGp7GpioAssign; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1119 | |
| 1120 | /** Offset 0x035E - PCH ISH PDT Unlock Msg |
| 1121 | 0: False; 1: True. |
| 1122 | $EN_DIS |
| 1123 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1124 | UINT8 PchIshPdtUnlock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1125 | |
| 1126 | /** Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN |
| 1127 | 0: Disable; 1: Enable. |
| 1128 | $EN_DIS |
| 1129 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1130 | UINT8 PchLanLtrEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1131 | |
| 1132 | /** Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management |
| 1133 | 0: Disable; 1: Enable. |
| 1134 | $EN_DIS |
| 1135 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1136 | UINT8 PchLanK1OffEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1137 | |
| 1138 | /** Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported |
| 1139 | 0: Disable; 1: Enable. |
| 1140 | $EN_DIS |
| 1141 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1142 | UINT8 PchLanClkReqSupported; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1143 | |
| 1144 | /** Offset 0x0362 - CLKREQ# used by GbE |
| 1145 | Valid if ClkReqSupported is TRUE. |
| 1146 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1147 | UINT8 PchLanClkReqNumber; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1148 | |
| 1149 | /** Offset 0x0363 - Enable LOCKDOWN BIOS LOCK |
| 1150 | Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region |
| 1151 | protection. |
| 1152 | $EN_DIS |
| 1153 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1154 | UINT8 PchLockDownBiosLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1155 | |
| 1156 | /** Offset 0x0364 - Enable LOCKDOWN SPI Eiss |
| 1157 | Enable InSMM.STS (EISS) in SPI. |
| 1158 | $EN_DIS |
| 1159 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1160 | UINT8 PchLockDownSpiEiss; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1161 | |
| 1162 | /** Offset 0x0365 - PCH Sub system vendor ID |
| 1163 | Default Subsystem Vendor ID of the PCH devices. Default is 0x8086. |
| 1164 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1165 | UINT16 PchSubSystemVendorId; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1166 | |
| 1167 | /** Offset 0x0367 - PCH Sub system ID |
| 1168 | Default Subsystem ID of the PCH devices. Default is 0x7270. |
| 1169 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1170 | UINT16 PchSubSystemId; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1171 | |
| 1172 | /** Offset 0x0369 - PCH Compatibility Revision ID |
| 1173 | This member describes whether or not the CRID feature of PCH should be enabled. |
| 1174 | $EN_DIS |
| 1175 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1176 | UINT8 PchCrid; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1177 | |
| 1178 | /** Offset 0x036A |
| 1179 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1180 | UINT8 UnusedUpdSpace15[6]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1181 | |
| 1182 | /** Offset 0x0370 - Enable PCIE RP HotPlug |
| 1183 | Indicate whether the root port is hot plug available. |
| 1184 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1185 | UINT8 PcieRpHotPlug[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1186 | |
| 1187 | /** Offset 0x0388 - Enable PCIE RP Pm Sci |
| 1188 | Indicate whether the root port power manager SCI is enabled. |
| 1189 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1190 | UINT8 PcieRpPmSci[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1191 | |
| 1192 | /** Offset 0x03A0 - Enable PCIE RP Ext Sync |
| 1193 | Indicate whether the extended synch is enabled. |
| 1194 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1195 | UINT8 PcieRpExtSync[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1196 | |
| 1197 | /** Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing |
| 1198 | Indicate whether the Transmitter Half Swing is enabled. |
| 1199 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1200 | UINT8 PcieRpTransmitterHalfSwing[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1201 | |
| 1202 | /** Offset 0x03D0 - Enable PCIE RP Clk Req Detect |
| 1203 | Probe CLKREQ# signal before enabling CLKREQ# based power management. |
| 1204 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1205 | UINT8 PcieRpClkReqDetect[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1206 | |
| 1207 | /** Offset 0x03E8 - PCIE RP Advanced Error Report |
| 1208 | Indicate whether the Advanced Error Reporting is enabled. |
| 1209 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1210 | UINT8 PcieRpAdvancedErrorReporting[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1211 | |
| 1212 | /** Offset 0x0400 - PCIE RP Unsupported Request Report |
| 1213 | Indicate whether the Unsupported Request Report is enabled. |
| 1214 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1215 | UINT8 PcieRpUnsupportedRequestReport[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1216 | |
| 1217 | /** Offset 0x0418 - PCIE RP Fatal Error Report |
| 1218 | Indicate whether the Fatal Error Report is enabled. |
| 1219 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1220 | UINT8 PcieRpFatalErrorReport[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1221 | |
| 1222 | /** Offset 0x0430 - PCIE RP No Fatal Error Report |
| 1223 | Indicate whether the No Fatal Error Report is enabled. |
| 1224 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1225 | UINT8 PcieRpNoFatalErrorReport[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1226 | |
| 1227 | /** Offset 0x0448 - PCIE RP Correctable Error Report |
| 1228 | Indicate whether the Correctable Error Report is enabled. |
| 1229 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1230 | UINT8 PcieRpCorrectableErrorReport[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1231 | |
| 1232 | /** Offset 0x0460 - PCIE RP System Error On Fatal Error |
| 1233 | Indicate whether the System Error on Fatal Error is enabled. |
| 1234 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1235 | UINT8 PcieRpSystemErrorOnFatalError[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1236 | |
| 1237 | /** Offset 0x0478 - PCIE RP System Error On Non Fatal Error |
| 1238 | Indicate whether the System Error on Non Fatal Error is enabled. |
| 1239 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1240 | UINT8 PcieRpSystemErrorOnNonFatalError[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1241 | |
| 1242 | /** Offset 0x0490 - PCIE RP System Error On Correctable Error |
| 1243 | Indicate whether the System Error on Correctable Error is enabled. |
| 1244 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1245 | UINT8 PcieRpSystemErrorOnCorrectableError[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1246 | |
| 1247 | /** Offset 0x04A8 - PCIE RP Max Payload |
| 1248 | Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. |
| 1249 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1250 | UINT8 PcieRpMaxPayload[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1251 | |
| 1252 | /** Offset 0x04C0 - PCIE RP Device Reset Pad Active High |
| 1253 | Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad. |
| 1254 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1255 | UINT8 PcieRpDeviceResetPadActiveHigh[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1256 | |
| 1257 | /** Offset 0x04D8 - PCIE RP Pcie Speed |
| 1258 | Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: |
| 1259 | PCH_PCIE_SPEED). |
| 1260 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1261 | UINT8 PcieRpPcieSpeed[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1262 | |
| 1263 | /** Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method |
| 1264 | PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; |
| 1265 | 4: Fixed Coeficients. |
| 1266 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1267 | UINT8 PcieRpGen3EqPh3Method[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1268 | |
| 1269 | /** Offset 0x0508 - PCIE RP Physical Slot Number |
| 1270 | Indicates the slot number for the root port. Default is the value as root port index. |
| 1271 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1272 | UINT8 PcieRpPhysicalSlotNumber[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1273 | |
| 1274 | /** Offset 0x0520 - PCIE RP Completion Timeout |
| 1275 | The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. |
| 1276 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1277 | UINT8 PcieRpCompletionTimeout[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1278 | |
| 1279 | /** Offset 0x0538 - PCIE RP Device Reset Pad |
| 1280 | The PCH pin assigned to device PERST# signal if available, zero otherwise. See |
| 1281 | also DeviceResetPadActiveHigh. |
| 1282 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1283 | UINT32 PcieRpDeviceResetPad[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1284 | |
| 1285 | /** Offset 0x0598 - PCIE RP Aspm |
| 1286 | The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is |
| 1287 | PchPcieAspmAutoConfig. |
| 1288 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1289 | UINT8 PcieRpAspm[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1290 | |
| 1291 | /** Offset 0x05B0 - PCIE RP L1 Substates |
| 1292 | The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). |
| 1293 | Default is PchPcieL1SubstatesL1_1_2. |
| 1294 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1295 | UINT8 PcieRpL1Substates[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1296 | |
| 1297 | /** Offset 0x05C8 - PCIE RP Ltr Enable |
| 1298 | Latency Tolerance Reporting Mechanism. |
| 1299 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1300 | UINT8 PcieRpLtrEnable[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1301 | |
| 1302 | /** Offset 0x05E0 - PCIE RP Ltr Config Lock |
| 1303 | 0: Disable; 1: Enable. |
| 1304 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1305 | UINT8 PcieRpLtrConfigLock[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1306 | |
| 1307 | /** Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm |
| 1308 | PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. |
| 1309 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1310 | UINT8 PcieEqPh3LaneParamCm[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1311 | |
| 1312 | /** Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp |
| 1313 | PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. |
| 1314 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1315 | UINT8 PcieEqPh3LaneParamCp[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1316 | |
| 1317 | /** Offset 0x0628 - PCIE Sw Eq CoeffList Cm |
| 1318 | PCH_PCIE_EQ_PARAM. Coefficient C-1. |
| 1319 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1320 | UINT8 PcieSwEqCoeffListCm[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1321 | |
| 1322 | /** Offset 0x062D - PCIE Sw Eq CoeffList Cp |
| 1323 | PCH_PCIE_EQ_PARAM. Coefficient C+1. |
| 1324 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1325 | UINT8 PcieSwEqCoeffListCp[5]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1326 | |
| 1327 | /** Offset 0x0632 - PCIE Disable RootPort Clock Gating |
| 1328 | Describes whether the PCI Express Clock Gating for each root port is enabled by |
| 1329 | platform modules. 0: Disable; 1: Enable. |
| 1330 | $EN_DIS |
| 1331 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1332 | UINT8 PcieDisableRootPortClockGating; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1333 | |
| 1334 | /** Offset 0x0633 - PCIE Enable Peer Memory Write |
| 1335 | This member describes whether Peer Memory Writes are enabled on the platform. |
| 1336 | $EN_DIS |
| 1337 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1338 | UINT8 PcieEnablePeerMemoryWrite; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1339 | |
| 1340 | /** Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown |
| 1341 | Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable |
| 1342 | or leaving untouched. |
| 1343 | $EN_DIS |
| 1344 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1345 | UINT8 PcieAllowNoLtrIccPllShutdown; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1346 | |
| 1347 | /** Offset 0x0635 - PCIE Compliance Test Mode |
| 1348 | Compliance Test Mode shall be enabled when using Compliance Load Board. |
| 1349 | $EN_DIS |
| 1350 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1351 | UINT8 PcieComplianceTestMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1352 | |
| 1353 | /** Offset 0x0636 - PCIE Rp Function Swap |
| 1354 | Allows BIOS to use root port function number swapping when root port of function |
| 1355 | 0 is disabled. |
| 1356 | $EN_DIS |
| 1357 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1358 | UINT8 PcieRpFunctionSwap; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1359 | |
| 1360 | /** Offset 0x0637 - PCIE Rp Detect Timeout Ms |
| 1361 | Will wait for link to exit Detect state for enabled ports before assuming there |
| 1362 | is no device and potentially disabling the port. |
| 1363 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1364 | UINT16 PcieDetectTimeoutMs; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1365 | |
| 1366 | /** Offset 0x0639 - PCH Pm PME_B0_S5_DIS |
| 1367 | When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. |
| 1368 | $EN_DIS |
| 1369 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1370 | UINT8 PchPmPmeB0S5Dis; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1371 | |
| 1372 | /** Offset 0x063A |
| 1373 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1374 | UINT8 UnusedUpdSpace16[6]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1375 | |
| 1376 | /** Offset 0x0640 - PCH Pm Wol Enable Override |
| 1377 | Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. |
| 1378 | $EN_DIS |
| 1379 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1380 | UINT8 PchPmWolEnableOverride; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1381 | |
| 1382 | /** Offset 0x0641 - PCH Pm Pcie Wake From DeepSx |
| 1383 | Determine if enable PCIe to wake from deep Sx. |
| 1384 | $EN_DIS |
| 1385 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1386 | UINT8 PchPmPcieWakeFromDeepSx; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1387 | |
| 1388 | /** Offset 0x0642 - PCH Pm WoW lan Enable |
| 1389 | Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. |
| 1390 | $EN_DIS |
| 1391 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1392 | UINT8 PchPmWoWlanEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1393 | |
| 1394 | /** Offset 0x0643 - PCH Pm WoW lan DeepSx Enable |
| 1395 | Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the |
| 1396 | PWRM_CFG3 register. |
| 1397 | $EN_DIS |
| 1398 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1399 | UINT8 PchPmWoWlanDeepSxEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1400 | |
| 1401 | /** Offset 0x0644 - PCH Pm Lan Wake From DeepSx |
| 1402 | Determine if enable LAN to wake from deep Sx. |
| 1403 | $EN_DIS |
| 1404 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1405 | UINT8 PchPmLanWakeFromDeepSx; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1406 | |
| 1407 | /** Offset 0x0645 - PCH Pm Deep Sx Pol |
| 1408 | Deep Sx Policy. |
| 1409 | $EN_DIS |
| 1410 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1411 | UINT8 PchPmDeepSxPol; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1412 | |
| 1413 | /** Offset 0x0646 - PCH Pm Slp S3 Min Assert |
| 1414 | SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. |
| 1415 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1416 | UINT8 PchPmSlpS3MinAssert; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1417 | |
| 1418 | /** Offset 0x0647 - PCH Pm Slp S4 Min Assert |
| 1419 | SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. |
| 1420 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1421 | UINT8 PchPmSlpS4MinAssert; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1422 | |
| 1423 | /** Offset 0x0648 - PCH Pm Slp Sus Min Assert |
| 1424 | SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. |
| 1425 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1426 | UINT8 PchPmSlpSusMinAssert; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1427 | |
| 1428 | /** Offset 0x0649 - PCH Pm Slp A Min Assert |
| 1429 | SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. |
| 1430 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1431 | UINT8 PchPmSlpAMinAssert; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1432 | |
| 1433 | /** Offset 0x064A |
| 1434 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1435 | UINT8 UnusedUpdSpace17[6]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1436 | |
| 1437 | /** Offset 0x0650 - PCH Pm Lpc Clock Run |
| 1438 | This member describes whether or not the LPC ClockRun feature of PCH should be enabled. |
| 1439 | $EN_DIS |
| 1440 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1441 | UINT8 PchPmLpcClockRun; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1442 | |
| 1443 | /** Offset 0x0651 - PCH Pm Slp Strch Sus Up |
| 1444 | Enable SLP_X Stretching After SUS Well Power Up. |
| 1445 | $EN_DIS |
| 1446 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1447 | UINT8 PchPmSlpStrchSusUp; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1448 | |
| 1449 | /** Offset 0x0652 - PCH Pm Slp Lan Low Dc |
| 1450 | Enable/Disable SLP_LAN# Low on DC Power. |
| 1451 | $EN_DIS |
| 1452 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1453 | UINT8 PchPmSlpLanLowDc; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1454 | |
| 1455 | /** Offset 0x0653 - PCH Pm Pwr Btn Override Period |
| 1456 | PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. |
| 1457 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1458 | UINT8 PchPmPwrBtnOverridePeriod; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1459 | |
| 1460 | /** Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown |
| 1461 | When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. |
| 1462 | $EN_DIS |
| 1463 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1464 | UINT8 PchPmDisableDsxAcPresentPulldown; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1465 | |
| 1466 | /** Offset 0x0655 - PCH Pm Capsule Reset Type |
| 1467 | Deprecated: Determines type of reset issued during UpdateCapsule(). Always Warm reset. |
| 1468 | $EN_DIS |
| 1469 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1470 | UINT8 PchPmCapsuleResetType; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1471 | |
| 1472 | /** Offset 0x0656 - PCH Pm Disable Native Power Button |
| 1473 | Power button native mode disable. |
| 1474 | $EN_DIS |
| 1475 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1476 | UINT8 PchPmDisableNativePowerButton; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1477 | |
| 1478 | /** Offset 0x0657 - PCH Pm Slp S0 Enable |
| 1479 | Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. |
| 1480 | $EN_DIS |
| 1481 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1482 | UINT8 PchPmSlpS0Enable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1483 | |
| 1484 | /** Offset 0x0658 - PCH Pm ME_WAKE_STS |
| 1485 | Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. |
| 1486 | $EN_DIS |
| 1487 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1488 | UINT8 PchPmMeWakeSts; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1489 | |
| 1490 | /** Offset 0x0659 - PCH Pm WOL_OVR_WK_STS |
| 1491 | Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. |
| 1492 | $EN_DIS |
| 1493 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1494 | UINT8 PchPmWolOvrWkSts; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1495 | |
| 1496 | /** Offset 0x065A - PCH Pm Reset Power Cycle Duration |
| 1497 | Could be customized in the unit of second. Please refer to EDS for all support settings. |
| 1498 | 0 is default, 1 is 1 second, 2 is 2 seconds, ... |
| 1499 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1500 | UINT8 PchPmPwrCycDur; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1501 | |
| 1502 | /** Offset 0x065B - PCH Pm Pcie Pll Ssc |
| 1503 | Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No |
| 1504 | BIOS override. |
| 1505 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1506 | UINT8 PchPmPciePllSsc; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1507 | |
| 1508 | /** Offset 0x065C - PCH Pm WOL_OVR_WK_STS |
| 1509 | Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. |
| 1510 | $EN_DIS |
| 1511 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1512 | UINT8 PchPort61hEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1513 | |
| 1514 | /** Offset 0x065D - PCH Sata Pwr Opt Enable |
| 1515 | SATA Power Optimizer on PCH side. |
| 1516 | $EN_DIS |
| 1517 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1518 | UINT8 SataPwrOptEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1519 | |
| 1520 | /** Offset 0x065E - PCH Sata eSATA Speed Limit |
| 1521 | When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. |
| 1522 | $EN_DIS |
| 1523 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1524 | UINT8 EsataSpeedLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1525 | |
| 1526 | /** Offset 0x065F - PCH Sata Speed Limit |
| 1527 | Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. |
| 1528 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1529 | UINT8 SataSpeedLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1530 | |
| 1531 | /** Offset 0x0660 - Enable SATA Port HotPlug |
| 1532 | Enable SATA Port HotPlug. |
| 1533 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1534 | UINT8 SataPortsHotPlug[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1535 | |
| 1536 | /** Offset 0x0668 - Enable SATA Port Interlock Sw |
| 1537 | Enable SATA Port Interlock Sw. |
| 1538 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1539 | UINT8 SataPortsInterlockSw[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1540 | |
| 1541 | /** Offset 0x0670 - Enable SATA Port External |
| 1542 | Enable SATA Port External. |
| 1543 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1544 | UINT8 SataPortsExternal[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1545 | |
| 1546 | /** Offset 0x0678 - Enable SATA Port SpinUp |
| 1547 | Enable the COMRESET initialization Sequence to the device. |
| 1548 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1549 | UINT8 SataPortsSpinUp[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1550 | |
| 1551 | /** Offset 0x0680 - Enable SATA Port Solid State Drive |
| 1552 | 0: HDD; 1: SSD. |
| 1553 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1554 | UINT8 SataPortsSolidStateDrive[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1555 | |
| 1556 | /** Offset 0x0688 - Enable SATA Port Enable Dito Config |
| 1557 | Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 1558 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1559 | UINT8 SataPortsEnableDitoConfig[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1560 | |
| 1561 | /** Offset 0x0690 - Enable SATA Port DmVal |
| 1562 | DITO multiplier. Default is 15. |
| 1563 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1564 | UINT8 SataPortsDmVal[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1565 | |
| 1566 | /** Offset 0x0698 - Enable SATA Port DmVal |
| 1567 | DEVSLP Idle Timeout (DITO), Default is 625. |
| 1568 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1569 | UINT16 SataPortsDitoVal[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1570 | |
| 1571 | /** Offset 0x06A8 - Enable SATA Port ZpOdd |
| 1572 | Support zero power ODD. |
| 1573 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1574 | UINT8 SataPortsZpOdd[8]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1575 | |
| 1576 | /** Offset 0x06B0 - PCH Sata Rst Raid Alternate Id |
| 1577 | Enable RAID Alternate ID. |
| 1578 | $EN_DIS |
| 1579 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1580 | UINT8 SataRstRaidAlternateId; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1581 | |
| 1582 | /** Offset 0x06B1 - PCH Sata Rst Raid0 |
| 1583 | RAID0. |
| 1584 | $EN_DIS |
| 1585 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1586 | UINT8 SataRstRaid0; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1587 | |
| 1588 | /** Offset 0x06B2 - PCH Sata Rst Raid1 |
| 1589 | RAID1. |
| 1590 | $EN_DIS |
| 1591 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1592 | UINT8 SataRstRaid1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1593 | |
| 1594 | /** Offset 0x06B3 - PCH Sata Rst Raid10 |
| 1595 | RAID10. |
| 1596 | $EN_DIS |
| 1597 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1598 | UINT8 SataRstRaid10; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1599 | |
| 1600 | /** Offset 0x06B4 - PCH Sata Rst Raid5 |
| 1601 | RAID5. |
| 1602 | $EN_DIS |
| 1603 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1604 | UINT8 SataRstRaid5; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1605 | |
| 1606 | /** Offset 0x06B5 - PCH Sata Rst Irrt |
| 1607 | Intel Rapid Recovery Technology. |
| 1608 | $EN_DIS |
| 1609 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1610 | UINT8 SataRstIrrt; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1611 | |
| 1612 | /** Offset 0x06B6 - PCH Sata Rst Orom Ui Banner |
| 1613 | OROM UI and BANNER. |
| 1614 | $EN_DIS |
| 1615 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1616 | UINT8 SataRstOromUiBanner; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1617 | |
| 1618 | /** Offset 0x06B7 - PCH Sata Rst Orom Ui Delay |
| 1619 | 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). |
| 1620 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1621 | UINT8 SataRstOromUiDelay; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1622 | |
| 1623 | /** Offset 0x06B8 - PCH Sata Rst Hdd Unlock |
| 1624 | Indicates that the HDD password unlock in the OS is enabled. |
| 1625 | $EN_DIS |
| 1626 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1627 | UINT8 SataRstHddUnlock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1628 | |
| 1629 | /** Offset 0x06B9 - PCH Sata Rst Led Locate |
| 1630 | Indicates that the LED/SGPIO hardware is attached and ping to locate feature is |
| 1631 | enabled on the OS. |
| 1632 | $EN_DIS |
| 1633 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1634 | UINT8 SataRstLedLocate; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1635 | |
| 1636 | /** Offset 0x06BA - PCH Sata Rst Irrt Only |
| 1637 | Allow only IRRT drives to span internal and external ports. |
| 1638 | $EN_DIS |
| 1639 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1640 | UINT8 SataRstIrrtOnly; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1641 | |
| 1642 | /** Offset 0x06BB - PCH Sata Rst Smart Storage |
| 1643 | RST Smart Storage caching Bit. |
| 1644 | $EN_DIS |
| 1645 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1646 | UINT8 SataRstSmartStorage; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1647 | |
| 1648 | /** Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable |
| 1649 | Enable Intel RST for PCIe Storage remapping. |
| 1650 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1651 | UINT8 SataRstPcieEnable[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1652 | |
| 1653 | /** Offset 0x06BF - PCH Sata Rst Pcie Storage Port |
| 1654 | Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). |
| 1655 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1656 | UINT8 SataRstPcieStoragePort[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1657 | |
| 1658 | /** Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay |
| 1659 | PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms |
| 1660 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1661 | UINT8 SataRstPcieDeviceResetDelay[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1662 | |
| 1663 | /** Offset 0x06C5 - Enable eMMC HS400 Training |
| 1664 | Determine if HS400 Training is required. |
| 1665 | $EN_DIS |
| 1666 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1667 | UINT8 PchScsEmmcHs400TuningRequired; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1668 | |
| 1669 | /** Offset 0x06C6 - Set HS400 Tuning Data Valid |
| 1670 | Set if HS400 Tuning Data Valid. |
| 1671 | $EN_DIS |
| 1672 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1673 | UINT8 PchScsEmmcHs400DllDataValid; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1674 | |
| 1675 | /** Offset 0x06C7 - Rx Strobe Delay Control |
| 1676 | Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). |
| 1677 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1678 | UINT8 PchScsEmmcHs400RxStrobeDll1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1679 | |
| 1680 | /** Offset 0x06C8 - Tx Data Delay Control |
| 1681 | Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). |
| 1682 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1683 | UINT8 PchScsEmmcHs400TxDataDll; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1684 | |
| 1685 | /** Offset 0x06C9 - I/O Driver Strength |
| 1686 | I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm. |
| 1687 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1688 | UINT8 PchScsEmmcHs400DriverStrength; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1689 | |
| 1690 | /** Offset 0x06CA - Enable Pch Serial IO GPIO |
| 1691 | Determines if enable Serial IO GPIO. |
| 1692 | $EN_DIS |
| 1693 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1694 | UINT8 SerialIoGpio; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1695 | |
| 1696 | /** Offset 0x06CB - IO voltage for I2C controllers |
| 1697 | Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. |
| 1698 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1699 | UINT8 SerialIoI2cVoltage[6]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1700 | |
| 1701 | /** Offset 0x06D1 - SPI ChipSelect signal polarity |
| 1702 | Selects SPI ChipSelect signal polarity. |
| 1703 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1704 | UINT8 SerialIoSpiCsPolarity[2]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1705 | |
| 1706 | /** Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines |
| 1707 | Enables UART hardware flow control, CTS and RTS linesh. |
| 1708 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1709 | UINT8 SerialIoUartHwFlowCtrl[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1710 | |
| 1711 | /** Offset 0x06D6 - UART Number For Debug Purpose |
| 1712 | UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. |
| 1713 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1714 | UINT8 SerialIoDebugUartNumber; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1715 | |
| 1716 | /** Offset 0x06D7 - Enable Debug UART Controller |
| 1717 | Enable debug UART controller after post. |
| 1718 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1719 | UINT8 SerialIoEnableDebugUartAfterPost; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1720 | |
| 1721 | /** Offset 0x06D8 - Enable Serial IRQ |
| 1722 | Determines if enable Serial IRQ. |
| 1723 | $EN_DIS |
| 1724 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1725 | UINT8 PchSirqEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1726 | |
| 1727 | /** Offset 0x06D9 - Serial IRQ Mode Select |
| 1728 | Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. |
| 1729 | $EN_DIS |
| 1730 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1731 | UINT8 PchSirqMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1732 | |
| 1733 | /** Offset 0x06DA - Start Frame Pulse Width |
| 1734 | Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. |
| 1735 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1736 | UINT8 PchStartFramePulse; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1737 | |
| 1738 | /** Offset 0x06DB - Enable Thermal Device |
| 1739 | Enable Thermal Device. |
| 1740 | $EN_DIS |
| 1741 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1742 | UINT8 PchThermalDeviceEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1743 | |
| 1744 | /** Offset 0x06DC - Thermal Device SMI Enable |
| 1745 | This locks down SMI Enable on Alert Thermal Sensor Trip. |
| 1746 | $EN_DIS |
| 1747 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1748 | UINT8 PchTsmicLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1749 | |
| 1750 | /** Offset 0x06DD - Thermal Throttling Custimized T0Level Value |
| 1751 | Custimized T0Level value. |
| 1752 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1753 | UINT16 PchT0Level; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1754 | |
| 1755 | /** Offset 0x06DF - Thermal Throttling Custimized T1Level Value |
| 1756 | Custimized T1Level value. |
| 1757 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1758 | UINT16 PchT1Level; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1759 | |
| 1760 | /** Offset 0x06E1 - Thermal Throttling Custimized T2Level Value |
| 1761 | Custimized T2Level value. |
| 1762 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1763 | UINT16 PchT2Level; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1764 | |
| 1765 | /** Offset 0x06E3 - Enable The Thermal Throttle |
| 1766 | Enable the thermal throttle function. |
| 1767 | $EN_DIS |
| 1768 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1769 | UINT8 PchTTEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1770 | |
| 1771 | /** Offset 0x06E4 - PMSync State 13 |
| 1772 | When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force |
| 1773 | at least T2 state. |
| 1774 | $EN_DIS |
| 1775 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1776 | UINT8 PchTTState13Enable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1777 | |
| 1778 | /** Offset 0x06E5 - Thermal Throttle Lock |
| 1779 | Thermal Throttle Lock. |
| 1780 | $EN_DIS |
| 1781 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1782 | UINT8 PchTTLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1783 | |
| 1784 | /** Offset 0x06E6 - Thermal Throttling Suggested Setting |
| 1785 | Thermal Throttling Suggested Setting. |
| 1786 | $EN_DIS |
| 1787 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1788 | UINT8 TTSuggestedSetting; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1789 | |
| 1790 | /** Offset 0x06E7 - Enable PCH Cross Throttling |
| 1791 | Enable/Disable PCH Cross Throttling |
| 1792 | $EN_DIS |
| 1793 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1794 | UINT8 TTCrossThrottling; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1795 | |
| 1796 | /** Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable |
| 1797 | DMI Thermal Sensor Autonomous Width Enable. |
| 1798 | $EN_DIS |
| 1799 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1800 | UINT8 PchDmiTsawEn; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1801 | |
| 1802 | /** Offset 0x06E9 - DMI Thermal Sensor Suggested Setting |
| 1803 | DMT thermal sensor suggested representative values. |
| 1804 | $EN_DIS |
| 1805 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1806 | UINT8 DmiSuggestedSetting; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1807 | |
| 1808 | /** Offset 0x06EA - Thermal Sensor 0 Target Width |
| 1809 | Thermal Sensor 0 Target Width. |
| 1810 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1811 | UINT8 DmiTS0TW; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1812 | |
| 1813 | /** Offset 0x06EB - Thermal Sensor 1 Target Width |
| 1814 | Thermal Sensor 1 Target Width. |
| 1815 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1816 | UINT8 DmiTS1TW; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1817 | |
| 1818 | /** Offset 0x06EC - Thermal Sensor 2 Target Width |
| 1819 | Thermal Sensor 2 Target Width. |
| 1820 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1821 | UINT8 DmiTS2TW; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1822 | |
| 1823 | /** Offset 0x06ED - Thermal Sensor 3 Target Width |
| 1824 | Thermal Sensor 3 Target Width. |
| 1825 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1826 | UINT8 DmiTS3TW; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1827 | |
| 1828 | /** Offset 0x06EE - Port 0 T1 Multipler |
| 1829 | Port 0 T1 Multipler. |
| 1830 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1831 | UINT8 SataP0T1M; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1832 | |
| 1833 | /** Offset 0x06EF - Port 0 T2 Multipler |
| 1834 | Port 0 T2 Multipler. |
| 1835 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1836 | UINT8 SataP0T2M; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1837 | |
| 1838 | /** Offset 0x06F0 - Port 0 T3 Multipler |
| 1839 | Port 0 T3 Multipler. |
| 1840 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1841 | UINT8 SataP0T3M; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1842 | |
| 1843 | /** Offset 0x06F1 - Port 0 Tdispatch |
| 1844 | Port 0 Tdispatch. |
| 1845 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1846 | UINT8 SataP0TDisp; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1847 | |
| 1848 | /** Offset 0x06F2 - Port 1 T1 Multipler |
| 1849 | Port 1 T1 Multipler. |
| 1850 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1851 | UINT8 SataP1T1M; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1852 | |
| 1853 | /** Offset 0x06F3 - Port 1 T2 Multipler |
| 1854 | Port 1 T2 Multipler. |
| 1855 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1856 | UINT8 SataP1T2M; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1857 | |
| 1858 | /** Offset 0x06F4 - Port 1 T3 Multipler |
| 1859 | Port 1 T3 Multipler. |
| 1860 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1861 | UINT8 SataP1T3M; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1862 | |
| 1863 | /** Offset 0x06F5 - Port 1 Tdispatch |
| 1864 | Port 1 Tdispatch. |
| 1865 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1866 | UINT8 SataP1TDisp; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1867 | |
| 1868 | /** Offset 0x06F6 - Port 0 Tinactive |
| 1869 | Port 0 Tinactive. |
| 1870 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1871 | UINT8 SataP0Tinact; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1872 | |
| 1873 | /** Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch |
| 1874 | Port 0 Alternate Fast Init Tdispatch. |
| 1875 | $EN_DIS |
| 1876 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1877 | UINT8 SataP0TDispFinit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1878 | |
| 1879 | /** Offset 0x06F8 - Port 1 Tinactive |
| 1880 | Port 1 Tinactive. |
| 1881 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1882 | UINT8 SataP1Tinact; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1883 | |
| 1884 | /** Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch |
| 1885 | Port 1 Alternate Fast Init Tdispatch. |
| 1886 | $EN_DIS |
| 1887 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1888 | UINT8 SataP1TDispFinit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1889 | |
| 1890 | /** Offset 0x06FA - Sata Thermal Throttling Suggested Setting |
| 1891 | Sata Thermal Throttling Suggested Setting. |
| 1892 | $EN_DIS |
| 1893 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1894 | UINT8 SataThermalSuggestedSetting; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1895 | |
| 1896 | /** Offset 0x06FB - Enable Memory Thermal Throttling |
| 1897 | Enable Memory Thermal Throttling. |
| 1898 | $EN_DIS |
| 1899 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1900 | UINT8 PchMemoryThrottlingEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1901 | |
| 1902 | /** Offset 0x06FC - Memory Thermal Throttling |
| 1903 | Enable Memory Thermal Throttling. |
| 1904 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1905 | UINT8 PchMemoryPmsyncEnable[2]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1906 | |
| 1907 | /** Offset 0x06FE - Enable Memory Thermal Throttling |
| 1908 | Enable Memory Thermal Throttling. |
| 1909 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1910 | UINT8 PchMemoryC0TransmitEnable[2]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1911 | |
| 1912 | /** Offset 0x0700 - Enable Memory Thermal Throttling |
| 1913 | Enable Memory Thermal Throttling. |
| 1914 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1915 | UINT8 PchMemoryPinSelection[2]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1916 | |
| 1917 | /** Offset 0x0702 - Thermal Device Temperature |
| 1918 | Decides the temperature. |
| 1919 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1920 | UINT16 PchTemperatureHotLevel; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1921 | |
| 1922 | /** Offset 0x0704 - Disable XHCI Compliance Mode |
| 1923 | This policy will disable XHCI compliance mode on all ports. Complicance Mode should |
| 1924 | be default enabled. |
| 1925 | $EN_DIS |
| 1926 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1927 | UINT8 PchDisableComplianceMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1928 | |
| 1929 | /** Offset 0x0705 - USB2 Port Over Current Pin |
| 1930 | Describe the specific over current pin number of USB 2.0 Port N. |
| 1931 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1932 | UINT8 Usb2OverCurrentPin[16]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1933 | |
| 1934 | /** Offset 0x0715 - USB3 Port Over Current Pin |
| 1935 | Describe the specific over current pin number of USB 3.0 Port N. |
| 1936 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1937 | UINT8 Usb3OverCurrentPin[10]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1938 | |
| 1939 | /** Offset 0x071F - Enable 8254 Static Clock Gating in early POST time |
| 1940 | Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might |
| 1941 | fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy |
| 1942 | OS boot before enabling this. |
| 1943 | $EN_DIS |
| 1944 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1945 | UINT8 Early8254ClockGatingEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1946 | |
| 1947 | /** Offset 0x0720 |
| 1948 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1949 | UINT32 UnusedUpdSpace18; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1950 | |
| 1951 | /** Offset 0x0724 - Pch PCIE device override table pointer |
| 1952 | The PCIe device table is being used to override PCIe device ASPM settings. This |
| 1953 | is a pointer points to a 32bit address. And it's only used in PostMem phase. Please |
| 1954 | refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId |
| 1955 | must be 0. |
| 1956 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1957 | UINT32 PchPcieDeviceOverrideTablePtr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1958 | |
| 1959 | /** Offset 0x0728 - Enable TCO timer. |
| 1960 | When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have |
| 1961 | huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer |
| 1962 | emulation must be enabled, and WDAT table must not be exposed to the OS. |
| 1963 | $EN_DIS |
| 1964 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1965 | UINT8 EnableTcoTimer; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1966 | |
| 1967 | /** Offset 0x0729 - BgpdtHash[4] |
| 1968 | BgpdtHash values |
| 1969 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1970 | UINT64 BgpdtHash[4]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1971 | |
| 1972 | /** Offset 0x0749 - BiosGuardAttr |
| 1973 | BiosGuardAttr default values |
| 1974 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1975 | UINT32 BiosGuardAttr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1976 | |
| 1977 | /** Offset 0x074D - BiosGuardModulePtr |
| 1978 | BiosGuardModulePtr default values |
| 1979 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1980 | UINT64 BiosGuardModulePtr; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1981 | |
| 1982 | /** Offset 0x0755 - SendEcCmd |
| 1983 | SendEcCmd function pointer. \n |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1984 | @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1985 | EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode |
| 1986 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1987 | UINT64 SendEcCmd; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1988 | |
| 1989 | /** Offset 0x075D - EcCmdProvisionEav |
| 1990 | Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC |
| 1991 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1992 | UINT8 EcCmdProvisionEav; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1993 | |
| 1994 | /** Offset 0x075E - EcCmdLock |
| 1995 | EcCmdLock default values. Locks Ephemeral Authorization Value sent previously |
| 1996 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 1997 | UINT8 EcCmdLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 1998 | |
| 1999 | /** Offset 0x075F - SgxEpoch0 |
| 2000 | SgxEpoch0 default values |
| 2001 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2002 | UINT64 SgxEpoch0; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2003 | |
| 2004 | /** Offset 0x0767 - SgxEpoch1 |
| 2005 | SgxEpoch1 default values |
| 2006 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2007 | UINT64 SgxEpoch1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2008 | |
| 2009 | /** Offset 0x076F - SgxSinitNvsData |
| 2010 | SgxSinitNvsData default values |
| 2011 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2012 | UINT8 SgxSinitNvsData; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2013 | |
| 2014 | /** Offset 0x0770 |
| 2015 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2016 | UINT8 ReservedFspsUpd[13]; |
| 2017 | } FSP_S_CONFIG; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2018 | |
| 2019 | /** Fsp S Test Configuration |
| 2020 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2021 | typedef struct { |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2022 | |
| 2023 | /** Offset 0x077D |
| 2024 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2025 | UINT32 Signature; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2026 | |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2027 | /** Offset 0x0781 - Enable/Disable Device 7 |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2028 | Enable: Device 7 enabled, Disable (Default): Device 7 disabled |
| 2029 | $EN_DIS |
| 2030 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2031 | UINT8 ChapDeviceEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2032 | |
| 2033 | /** Offset 0x0782 - Skip PAM regsiter lock |
| 2034 | Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): |
| 2035 | PAM registers will be locked by RC |
| 2036 | $EN_DIS |
| 2037 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2038 | UINT8 SkipPamLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2039 | |
| 2040 | /** Offset 0x0783 - EDRAM Test Mode |
| 2041 | Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): |
| 2042 | PAM registers will be locked by RC |
| 2043 | 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode |
| 2044 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2045 | UINT8 EdramTestMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2046 | |
| 2047 | /** Offset 0x0784 - DMI Extended Sync Control |
| 2048 | Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended |
| 2049 | Sync Control |
| 2050 | $EN_DIS |
| 2051 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2052 | UINT8 DmiExtSync; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2053 | |
| 2054 | /** Offset 0x0785 - DMI IOT Control |
| 2055 | Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control |
| 2056 | $EN_DIS |
| 2057 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2058 | UINT8 DmiIot; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2059 | |
| 2060 | /** Offset 0x0786 - PEG Max Payload size per root port |
| 2061 | 0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B |
| 2062 | 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B |
| 2063 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2064 | UINT8 PegMaxPayload[3]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2065 | |
| 2066 | /** Offset 0x0789 - Enable/Disable IGFX RenderStandby |
| 2067 | Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby |
| 2068 | $EN_DIS |
| 2069 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2070 | UINT8 RenderStandby; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2071 | |
| 2072 | /** Offset 0x078A - Enable/Disable IGFX PmSupport |
| 2073 | Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport |
| 2074 | $EN_DIS |
| 2075 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2076 | UINT8 PmSupport; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2077 | |
| 2078 | /** Offset 0x078B - Enable/Disable CdynmaxClamp |
| 2079 | Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp |
| 2080 | $EN_DIS |
| 2081 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2082 | UINT8 CdynmaxClampEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2083 | |
| 2084 | /** Offset 0x078C - Disable VT-d |
| 2085 | 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled) |
| 2086 | $EN_DIS |
| 2087 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2088 | UINT8 VtdDisable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2089 | |
| 2090 | /** Offset 0x078D - GT Frequency Limit |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2091 | 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, |
| 2092 | 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: |
| 2093 | 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, |
| 2094 | 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, |
| 2095 | 0x18: 1200 Mhz |
| 2096 | 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, |
| 2097 | 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: |
| 2098 | 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, |
| 2099 | 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, |
| 2100 | 0x18: 1200 Mhz |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2101 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2102 | UINT8 GtFreqMax; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2103 | |
| 2104 | /** Offset 0x078E - SaPostMemTestRsvd |
| 2105 | Reserved for SA Post-Mem Test |
| 2106 | $EN_DIS |
| 2107 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2108 | UINT8 SaPostMemTestRsvd[12]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2109 | |
| 2110 | /** Offset 0x079A |
| 2111 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2112 | UINT16 UnusedUpdSpace19; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2113 | |
| 2114 | /** Offset 0x079C - 1-Core Ratio Limit |
| 2115 | 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused |
| 2116 | 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal |
| 2117 | to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 |
| 2118 | 0x0:0xFF |
| 2119 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2120 | UINT8 OneCoreRatioLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2121 | |
| 2122 | /** Offset 0x079D - 2-Core Ratio Limit |
| 2123 | 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused |
| 2124 | 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal |
| 2125 | to 1-Core Ratio Limit.Range is 0 to 83 |
| 2126 | 0x0:0xFF |
| 2127 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2128 | UINT8 TwoCoreRatioLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2129 | |
| 2130 | /** Offset 0x079E - 3-Core Ratio Limit |
| 2131 | 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused |
| 2132 | 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal |
| 2133 | to 1-Core Ratio Limit.Range is 0 to 83 |
| 2134 | 0x0:0xFF |
| 2135 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2136 | UINT8 ThreeCoreRatioLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2137 | |
| 2138 | /** Offset 0x079F - 4-Core Ratio Limit |
| 2139 | 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused |
| 2140 | 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal |
| 2141 | to 1-Core Ratio Limit.Range is 0 to 83 |
| 2142 | 0x0:0xFF |
| 2143 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2144 | UINT8 FourCoreRatioLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2145 | |
| 2146 | /** Offset 0x07A0 |
| 2147 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2148 | UINT8 UnusedUpdSpace20; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2149 | |
| 2150 | /** Offset 0x07A1 - Enable or Disable HWP |
| 2151 | Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> |
| 2152 | 2-3:Reserved |
| 2153 | $EN_DIS |
| 2154 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2155 | UINT8 Hwp; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2156 | |
| 2157 | /** Offset 0x07A2 - Hardware Duty Cycle Control |
| 2158 | Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved |
| 2159 | $EN_DIS |
| 2160 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2161 | UINT8 HdcControl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2162 | |
| 2163 | /** Offset 0x07A3 - Package Long duration turbo mode time |
| 2164 | Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) |
| 2165 | 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 |
| 2166 | 0x0:0xFF |
| 2167 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2168 | UINT8 PowerLimit1Time; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2169 | |
| 2170 | /** Offset 0x07A4 - Short Duration Turbo Mode |
| 2171 | Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b> |
| 2172 | $EN_DIS |
| 2173 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2174 | UINT8 PowerLimit2; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2175 | |
| 2176 | /** Offset 0x07A5 - Turbo settings Lock |
| 2177 | Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable |
| 2178 | $EN_DIS |
| 2179 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2180 | UINT8 TurboPowerLimitLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2181 | |
| 2182 | /** Offset 0x07A6 - Package PL3 time window |
| 2183 | Package PL3 time window range for this policy in milliseconds. Valid values are |
| 2184 | 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64 |
| 2185 | 0x0:0xFF |
| 2186 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2187 | UINT8 PowerLimit3Time; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2188 | |
| 2189 | /** Offset 0x07A7 - Package PL3 Duty Cycle |
| 2190 | Package PL3 Duty Cycle; Valid Range is 0 to 100 |
| 2191 | 0x0:0xFF |
| 2192 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2193 | UINT8 PowerLimit3DutyCycle; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2194 | |
| 2195 | /** Offset 0x07A8 - Package PL3 Lock |
| 2196 | Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable |
| 2197 | $EN_DIS |
| 2198 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2199 | UINT8 PowerLimit3Lock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2200 | |
| 2201 | /** Offset 0x07A9 - Package PL4 Lock |
| 2202 | Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable |
| 2203 | $EN_DIS |
| 2204 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2205 | UINT8 PowerLimit4Lock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2206 | |
| 2207 | /** Offset 0x07AA - TCC Activation Offset |
| 2208 | TCC Activation Offset. Offset from factory set TCC activation temperature at which |
| 2209 | the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation |
| 2210 | Temperature, in volts.For SKL Y SKU, the recommended default for this policy is |
| 2211 | <b>10</b>, For all other SKUs the recommended default are <b>0</b> |
| 2212 | 0x0:0xFF |
| 2213 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2214 | UINT8 TccActivationOffset; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2215 | |
| 2216 | /** Offset 0x07AB - Tcc Offset Clamp Enable/Disable |
| 2217 | Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle |
| 2218 | below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>, |
| 2219 | For all other SKUs the recommended default are <b>0: Disabled</b>. |
| 2220 | $EN_DIS |
| 2221 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2222 | UINT8 TccOffsetClamp; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2223 | |
| 2224 | /** Offset 0x07AC - Tcc Offset Lock |
| 2225 | Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature |
| 2226 | target; <b>0: Disabled</b>; 1: Enabled. |
| 2227 | $EN_DIS |
| 2228 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2229 | UINT8 TccOffsetLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2230 | |
| 2231 | /** Offset 0x07AD - Custom Ratio State Entries |
| 2232 | The number of custom ratio state entries, ranges from 0 to 40 for a valid custom |
| 2233 | ratio table.Sets the number of custom P-states. At least 2 states must be present |
| 2234 | 0x0:0xFF |
| 2235 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2236 | UINT8 NumberOfEntries; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2237 | |
| 2238 | /** Offset 0x07AE - Custom Short term Power Limit time window |
| 2239 | Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 |
| 2240 | 0x0:0xFF |
| 2241 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2242 | UINT8 Custom1PowerLimit1Time; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2243 | |
| 2244 | /** Offset 0x07AF - Custom Turbo Activation Ratio |
| 2245 | Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 |
| 2246 | 0x0:0xFF |
| 2247 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2248 | UINT8 Custom1TurboActivationRatio; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2249 | |
| 2250 | /** Offset 0x07B0 - Custom Config Tdp Control |
| 2251 | Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 |
| 2252 | 0x0:0xFF |
| 2253 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2254 | UINT8 Custom1ConfigTdpControl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2255 | |
| 2256 | /** Offset 0x07B1 - Custom Short term Power Limit time window |
| 2257 | Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 |
| 2258 | 0x0:0xFF |
| 2259 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2260 | UINT8 Custom2PowerLimit1Time; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2261 | |
| 2262 | /** Offset 0x07B2 - Custom Turbo Activation Ratio |
| 2263 | Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 |
| 2264 | 0x0:0xFF |
| 2265 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2266 | UINT8 Custom2TurboActivationRatio; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2267 | |
| 2268 | /** Offset 0x07B3 - Custom Config Tdp Control |
| 2269 | Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 |
| 2270 | 0x0:0xFF |
| 2271 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2272 | UINT8 Custom2ConfigTdpControl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2273 | |
| 2274 | /** Offset 0x07B4 - Custom Short term Power Limit time window |
| 2275 | Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 |
| 2276 | 0x0:0xFF |
| 2277 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2278 | UINT8 Custom3PowerLimit1Time; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2279 | |
| 2280 | /** Offset 0x07B5 - Custom Turbo Activation Ratio |
| 2281 | Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 |
| 2282 | 0x0:0xFF |
| 2283 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2284 | UINT8 Custom3TurboActivationRatio; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2285 | |
| 2286 | /** Offset 0x07B6 - Custom Config Tdp Control |
| 2287 | Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 |
| 2288 | 0x0:0xFF |
| 2289 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2290 | UINT8 Custom3ConfigTdpControl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2291 | |
| 2292 | /** Offset 0x07B7 - ConfigTdp mode settings Lock |
| 2293 | Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable |
| 2294 | $EN_DIS |
| 2295 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2296 | UINT8 ConfigTdpLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2297 | |
| 2298 | /** Offset 0x07B8 - Load Configurable TDP SSDT |
| 2299 | Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable. |
| 2300 | $EN_DIS |
| 2301 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2302 | UINT8 ConfigTdpBios; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2303 | |
| 2304 | /** Offset 0x07B9 - PL1 Enable value |
| 2305 | PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable. |
| 2306 | $EN_DIS |
| 2307 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2308 | UINT8 PsysPowerLimit1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2309 | |
| 2310 | /** Offset 0x07BA - PL1 timewindow |
| 2311 | PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 |
| 2312 | , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 |
| 2313 | 0x0:0xFF |
| 2314 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2315 | UINT8 PsysPowerLimit1Time; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2316 | |
| 2317 | /** Offset 0x07BB - PL2 Enable Value |
| 2318 | PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>; |
| 2319 | 1: Enable. |
| 2320 | $EN_DIS |
| 2321 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2322 | UINT8 PsysPowerLimit2; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2323 | |
| 2324 | /** Offset 0x07BC |
| 2325 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2326 | UINT16 UnusedUpdSpace21; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2327 | |
| 2328 | /** Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher |
| 2329 | Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>. |
| 2330 | $EN_DIS |
| 2331 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2332 | UINT8 MlcStreamerPrefetcher; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2333 | |
| 2334 | /** Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher |
| 2335 | Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b> |
| 2336 | $EN_DIS |
| 2337 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2338 | UINT8 MlcSpatialPrefetcher; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2339 | |
| 2340 | /** Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions |
| 2341 | Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>. |
| 2342 | $EN_DIS |
| 2343 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2344 | UINT8 MonitorMwaitEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2345 | |
| 2346 | /** Offset 0x07C1 - Enable or Disable initialization of machine check registers |
| 2347 | Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>. |
| 2348 | $EN_DIS |
| 2349 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2350 | UINT8 MachineCheckEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2351 | |
| 2352 | /** Offset 0x07C2 - Enable or Disable processor debug features |
| 2353 | Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable. |
| 2354 | $EN_DIS |
| 2355 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2356 | UINT8 DebugInterfaceEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2357 | |
| 2358 | /** Offset 0x07C3 - Lock or Unlock debug interface features |
| 2359 | Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>. |
| 2360 | $EN_DIS |
| 2361 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2362 | UINT8 DebugInterfaceLockEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2363 | |
| 2364 | /** Offset 0x07C4 - AP Idle Manner of waiting for SIPI |
| 2365 | AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop. |
| 2366 | 0x0:0xFF |
| 2367 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2368 | UINT8 ApIdleManner; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2369 | |
| 2370 | /** Offset 0x07C5 - Settings for AP Handoff to OS |
| 2371 | Settings for AP Handoff to OS; 1: HALT loop; <b>2: MWAIT loop</b>. |
| 2372 | 0x0:0xFF |
| 2373 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2374 | UINT8 ApHandoffManner; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2375 | |
| 2376 | /** Offset 0x07C6 |
| 2377 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2378 | UINT16 UnusedUpdSpace22; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2379 | |
| 2380 | /** Offset 0x07C8 - Control on Processor Trace output scheme |
| 2381 | Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output. |
| 2382 | 0x0:0xFF |
| 2383 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2384 | UINT8 ProcTraceOutputScheme; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2385 | |
| 2386 | /** Offset 0x07C9 - Enable or Disable Processor Trace feature |
| 2387 | Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable. |
| 2388 | $EN_DIS |
| 2389 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2390 | UINT8 ProcTraceEnable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2391 | |
| 2392 | /** Offset 0x07CA - Memory region allocation for Processor Trace |
| 2393 | Memory region allocation for Processor Trace, Valid Values are 0 - 4KB , 0x1 - 8KB |
| 2394 | , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB |
| 2395 | , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB , 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE |
| 2396 | - 64MB , 0xF - 128MB , 0xFF: Disable |
| 2397 | 0x0:0xFF |
| 2398 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2399 | UINT8 ProcTraceMemSize; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2400 | |
| 2401 | /** Offset 0x07CB |
| 2402 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2403 | UINT8 UnusedUpdSpace23; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2404 | |
| 2405 | /** Offset 0x07CC - Enable or Disable Voltage Optimization feature |
| 2406 | Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b> |
| 2407 | $EN_DIS |
| 2408 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2409 | UINT8 VoltageOptimization; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2410 | |
| 2411 | /** Offset 0x07CD - Enable or Disable Intel SpeedStep Technology |
| 2412 | Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b> |
| 2413 | $EN_DIS |
| 2414 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2415 | UINT8 Eist; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2416 | |
| 2417 | /** Offset 0x07CE - Enable or Disable Energy Efficient P-state |
| 2418 | Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; |
| 2419 | <b>1: Enable</b> |
| 2420 | $EN_DIS |
| 2421 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2422 | UINT8 EnergyEfficientPState; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2423 | |
| 2424 | /** Offset 0x07CF - Enable or Disable Energy Efficient Turbo |
| 2425 | Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; |
| 2426 | <b>1: Enable</b> |
| 2427 | $EN_DIS |
| 2428 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2429 | UINT8 EnergyEfficientTurbo; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2430 | |
| 2431 | /** Offset 0x07D0 - Enable or Disable T states |
| 2432 | Enable or Disable T states; <b>0: Disable</b>; 1: Enable. |
| 2433 | $EN_DIS |
| 2434 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2435 | UINT8 TStates; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2436 | |
| 2437 | /** Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT# |
| 2438 | Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b> |
| 2439 | $EN_DIS |
| 2440 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2441 | UINT8 BiProcHot; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2442 | |
| 2443 | /** Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally |
| 2444 | Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>. |
| 2445 | $EN_DIS |
| 2446 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2447 | UINT8 DisableProcHotOut; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2448 | |
| 2449 | /** Offset 0x07D3 - Enable or Disable PROCHOT# Response |
| 2450 | Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable. |
| 2451 | $EN_DIS |
| 2452 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2453 | UINT8 ProcHotResponse; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2454 | |
| 2455 | /** Offset 0x07D4 - Enable or Disable VR Thermal Alert |
| 2456 | Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable. |
| 2457 | $EN_DIS |
| 2458 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2459 | UINT8 DisableVrThermalAlert; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2460 | |
| 2461 | /** Offset 0x07D5 - Enable or Disable Thermal Reporting |
| 2462 | Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>. |
| 2463 | $EN_DIS |
| 2464 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2465 | UINT8 AutoThermalReporting; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2466 | |
| 2467 | /** Offset 0x07D6 - Enable or Disable Thermal Monitor |
| 2468 | Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b> |
| 2469 | $EN_DIS |
| 2470 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2471 | UINT8 ThermalMonitor; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2472 | |
| 2473 | /** Offset 0x07D7 - Enable or Disable CPU power states (C-states) |
| 2474 | Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> |
| 2475 | $EN_DIS |
| 2476 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2477 | UINT8 Cx; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2478 | |
| 2479 | /** Offset 0x07D8 - Configure C-State Configuration Lock |
| 2480 | Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>. |
| 2481 | $EN_DIS |
| 2482 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2483 | UINT8 PmgCstCfgCtrlLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2484 | |
| 2485 | /** Offset 0x07D9 - Enable or Disable Enhanced C-states |
| 2486 | Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b> |
| 2487 | $EN_DIS |
| 2488 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2489 | UINT8 C1e; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2490 | |
| 2491 | /** Offset 0x07DA - Enable or Disable Package Cstate Demotion |
| 2492 | Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b> |
| 2493 | $EN_DIS |
| 2494 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2495 | UINT8 PkgCStateDemotion; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2496 | |
| 2497 | /** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion |
| 2498 | Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b> |
| 2499 | $EN_DIS |
| 2500 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2501 | UINT8 PkgCStateUnDemotion; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2502 | |
| 2503 | /** Offset 0x07DC - Enable or Disable CState-Pre wake |
| 2504 | Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b> |
| 2505 | $EN_DIS |
| 2506 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2507 | UINT8 CStatePreWake; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2508 | |
| 2509 | /** Offset 0x07DD - Enable or Disable TimedMwait Support. |
| 2510 | Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable |
| 2511 | $EN_DIS |
| 2512 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2513 | UINT8 TimedMwait; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2514 | |
| 2515 | /** Offset 0x07DE - Enable or Disable IO to MWAIT redirection |
| 2516 | Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable. |
| 2517 | $EN_DIS |
| 2518 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2519 | UINT8 CstCfgCtrIoMwaitRedirection; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2520 | |
| 2521 | /** Offset 0x07DF - Set the Max Pkg Cstate |
| 2522 | Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep |
| 2523 | C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , |
| 2524 | 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto |
| 2525 | 0x0:0xFF |
| 2526 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2527 | UINT8 PkgCStateLimit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2528 | |
| 2529 | /** Offset 0x07E0 - TimeUnit for C-State Latency Control0 |
| 2530 | TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns |
| 2531 | , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns |
| 2532 | 0x0:0xFF |
| 2533 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2534 | UINT8 CstateLatencyControl0TimeUnit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2535 | |
| 2536 | /** Offset 0x07E1 - TimeUnit for C-State Latency Control1 |
| 2537 | TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns |
| 2538 | , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns |
| 2539 | 0x0:0xFF |
| 2540 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2541 | UINT8 CstateLatencyControl1TimeUnit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2542 | |
| 2543 | /** Offset 0x07E2 - TimeUnit for C-State Latency Control2 |
| 2544 | TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns |
| 2545 | , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns |
| 2546 | 0x0:0xFF |
| 2547 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2548 | UINT8 CstateLatencyControl2TimeUnit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2549 | |
| 2550 | /** Offset 0x07E3 - TimeUnit for C-State Latency Control3 |
| 2551 | TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns |
| 2552 | , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns |
| 2553 | 0x0:0xFF |
| 2554 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2555 | UINT8 CstateLatencyControl3TimeUnit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2556 | |
| 2557 | /** Offset 0x07E4 - TimeUnit for C-State Latency Control4 |
| 2558 | TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns |
| 2559 | , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns |
| 2560 | 0x0:0xFF |
| 2561 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2562 | UINT8 CstateLatencyControl4TimeUnit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2563 | |
| 2564 | /** Offset 0x07E5 - TimeUnit for C-State Latency Control5 |
| 2565 | TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns |
| 2566 | , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns |
| 2567 | 0x0:0xFF |
| 2568 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2569 | UINT8 CstateLatencyControl5TimeUnit; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2570 | |
| 2571 | /** Offset 0x07E6 - Interrupt Redirection Mode Select |
| 2572 | Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: |
| 2573 | PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. |
| 2574 | 0x0:0xFF |
| 2575 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2576 | UINT8 PpmIrmSetting; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2577 | |
| 2578 | /** Offset 0x07E7 - Lock prochot configuration |
| 2579 | Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable |
| 2580 | $EN_DIS |
| 2581 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2582 | UINT8 ProcHotLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2583 | |
| 2584 | /** Offset 0x07E8 - Configuration for boot TDP selection |
| 2585 | Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP |
| 2586 | Up;0xFF : Deactivate |
| 2587 | 0x0:0xFF |
| 2588 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2589 | UINT8 ConfigTdpLevel; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2590 | |
| 2591 | /** Offset 0x07E9 - Max P-State Ratio |
| 2592 | Max P-State Ratio , Valid Range 0 to 0x7F |
| 2593 | 0x0:0xFFFF |
| 2594 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2595 | UINT16 MaxRatio; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2596 | |
| 2597 | /** Offset 0x07EB - Maximum P-state ratio to use in the custom P-state table |
| 2598 | Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has |
| 2599 | valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates) |
| 2600 | , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F |
| 2601 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2602 | UINT16 StateRatio[40]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2603 | |
| 2604 | /** Offset 0x083B - Platform Power Pmax |
| 2605 | PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. |
| 2606 | Range 0-1024 Watts. Value of 800 = 100W |
| 2607 | 0x0:0xFFFF |
| 2608 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2609 | UINT16 PsysPmax; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2610 | |
| 2611 | /** Offset 0x083D - Interrupt Response Time Limit of C-State LatencyContol0 |
| 2612 | Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF |
| 2613 | 0x0:0xFFFF |
| 2614 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2615 | UINT16 CstateLatencyControl0Irtl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2616 | |
| 2617 | /** Offset 0x083F - Interrupt Response Time Limit of C-State LatencyContol1 |
| 2618 | Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF |
| 2619 | 0x0:0xFFFF |
| 2620 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2621 | UINT16 CstateLatencyControl1Irtl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2622 | |
| 2623 | /** Offset 0x0841 - Interrupt Response Time Limit of C-State LatencyContol2 |
| 2624 | Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF |
| 2625 | 0x0:0xFFFF |
| 2626 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2627 | UINT16 CstateLatencyControl2Irtl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2628 | |
| 2629 | /** Offset 0x0843 - Interrupt Response Time Limit of C-State LatencyContol3 |
| 2630 | Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF |
| 2631 | 0x0:0xFFFF |
| 2632 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2633 | UINT16 CstateLatencyControl3Irtl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2634 | |
| 2635 | /** Offset 0x0845 - Interrupt Response Time Limit of C-State LatencyContol4 |
| 2636 | Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF |
| 2637 | 0x0:0xFFFF |
| 2638 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2639 | UINT16 CstateLatencyControl4Irtl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2640 | |
| 2641 | /** Offset 0x0847 - Interrupt Response Time Limit of C-State LatencyContol5 |
| 2642 | Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF |
| 2643 | 0x0:0xFFFF |
| 2644 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2645 | UINT16 CstateLatencyControl5Irtl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2646 | |
| 2647 | /** Offset 0x0849 - Package Long duration turbo mode power limit |
| 2648 | Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. |
| 2649 | Valid Range 0 to 4095875 in Step size of 125 |
| 2650 | 0x0:0xFFFFFFFF |
| 2651 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2652 | UINT32 PowerLimit1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2653 | |
| 2654 | /** Offset 0x084D - Package Short duration turbo mode power limit |
| 2655 | Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2656 | Range 0 to 4095875 in Step size of 125 |
| 2657 | 0x0:0xFFFFFFFF |
| 2658 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2659 | UINT32 PowerLimit2Power; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2660 | |
| 2661 | /** Offset 0x0851 - Package PL3 power limit |
| 2662 | Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2663 | Range 0 to 4095875 in Step size of 125 |
| 2664 | 0x0:0xFFFFFFFF |
| 2665 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2666 | UINT32 PowerLimit3; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2667 | |
| 2668 | /** Offset 0x0855 - Package PL4 power limit |
| 2669 | Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2670 | Range 0 to 4095875 in Step size of 125 |
| 2671 | 0x0:0xFFFFFFFF |
| 2672 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2673 | UINT32 PowerLimit4; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2674 | |
| 2675 | /** Offset 0x0859 - Tcc Offset Time Window for RATL |
| 2676 | Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2677 | Range 0 to 4095875 in Step size of 125 |
| 2678 | 0x0:0xFFFFFFFF |
| 2679 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2680 | UINT32 TccOffsetTimeWindowForRatl; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2681 | |
| 2682 | /** Offset 0x085D - Short term Power Limit value for custom cTDP level 1 |
| 2683 | Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2684 | Range 0 to 4095875 in Step size of 125 |
| 2685 | 0x0:0xFFFFFFFF |
| 2686 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2687 | UINT32 Custom1PowerLimit1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2688 | |
| 2689 | /** Offset 0x0861 - Long term Power Limit value for custom cTDP level 1 |
| 2690 | Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2691 | Range 0 to 4095875 in Step size of 125 |
| 2692 | 0x0:0xFFFFFFFF |
| 2693 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2694 | UINT32 Custom1PowerLimit2; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2695 | |
| 2696 | /** Offset 0x0865 - Short term Power Limit value for custom cTDP level 2 |
| 2697 | Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2698 | Range 0 to 4095875 in Step size of 125 |
| 2699 | 0x0:0xFFFFFFFF |
| 2700 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2701 | UINT32 Custom2PowerLimit1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2702 | |
| 2703 | /** Offset 0x0869 - Long term Power Limit value for custom cTDP level 2 |
| 2704 | Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2705 | Range 0 to 4095875 in Step size of 125 |
| 2706 | 0x0:0xFFFFFFFF |
| 2707 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2708 | UINT32 Custom2PowerLimit2; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2709 | |
| 2710 | /** Offset 0x086D - Short term Power Limit value for custom cTDP level 3 |
| 2711 | Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2712 | Range 0 to 4095875 in Step size of 125 |
| 2713 | 0x0:0xFFFFFFFF |
| 2714 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2715 | UINT32 Custom3PowerLimit1; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2716 | |
| 2717 | /** Offset 0x0871 - Long term Power Limit value for custom cTDP level 3 |
| 2718 | Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid |
| 2719 | Range 0 to 4095875 in Step size of 125 |
| 2720 | 0x0:0xFFFFFFFF |
| 2721 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2722 | UINT32 Custom3PowerLimit2; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2723 | |
| 2724 | /** Offset 0x0875 - Platform PL1 power |
| 2725 | Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range |
| 2726 | 0 to 4095875 in Step size of 125 |
| 2727 | 0x0:0xFFFFFFFF |
| 2728 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2729 | UINT32 PsysPowerLimit1Power; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2730 | |
| 2731 | /** Offset 0x0879 - Platform PL2 power |
| 2732 | Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range |
| 2733 | 0 to 4095875 in Step size of 125 |
| 2734 | 0x0:0xFFFFFFFF |
| 2735 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2736 | UINT32 PsysPowerLimit2Power; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2737 | |
| 2738 | /** Offset 0x087D - Race To Halt |
| 2739 | Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency |
| 2740 | in order to enter pkg C-State faster to reduce overall power. (RTH is controlled |
| 2741 | through MSR 1FC bit 20)Disable; <b>1: Enable</b> |
| 2742 | $EN_DIS |
| 2743 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2744 | UINT8 RaceToHalt; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2745 | |
| 2746 | /** Offset 0x087E - ReservedCpuPostMemTest |
| 2747 | Reserved for CPU Post-Mem Test |
| 2748 | $EN_DIS |
| 2749 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2750 | UINT8 ReservedCpuPostMemTest[12]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2751 | |
| 2752 | /** Offset 0x088A - SgxSinitDataFromTpm |
| 2753 | SgxSinitDataFromTpm default values |
| 2754 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2755 | UINT8 SgxSinitDataFromTpm; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2756 | |
| 2757 | /** Offset 0x088B - End of Post message |
| 2758 | Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): |
| 2759 | EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE |
| 2760 | 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved |
| 2761 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2762 | UINT8 EndOfPostMessage; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2763 | |
| 2764 | /** Offset 0x088C - D0I3 Setting for HECI Disable |
| 2765 | Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all |
| 2766 | HECI devices |
| 2767 | $EN_DIS |
| 2768 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2769 | UINT8 DisableD0I3SettingForHeci; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2770 | |
| 2771 | /** Offset 0x088D - HD Audio Reset Wait Timer |
| 2772 | The delay timer after Azalia reset, the value is number of microseconds. Default is 600. |
| 2773 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2774 | UINT16 PchHdaResetWaitTimer; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2775 | |
| 2776 | /** Offset 0x088F - Enable LOCKDOWN SMI |
| 2777 | Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. |
| 2778 | $EN_DIS |
| 2779 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2780 | UINT8 PchLockDownGlobalSmi; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2781 | |
| 2782 | /** Offset 0x0890 - Enable LOCKDOWN BIOS Interface |
| 2783 | Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. |
| 2784 | $EN_DIS |
| 2785 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2786 | UINT8 PchLockDownBiosInterface; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2787 | |
| 2788 | /** Offset 0x0891 - RTC CMOS RAM LOCK |
| 2789 | Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper |
| 2790 | and and lower 128-byte bank of RTC RAM. |
| 2791 | $EN_DIS |
| 2792 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2793 | UINT8 PchLockDownRtcLock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2794 | |
| 2795 | /** Offset 0x0892 - PCH Sbi lock bit |
| 2796 | This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. |
| 2797 | $EN_DIS |
| 2798 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2799 | UINT8 PchSbiUnlock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2800 | |
| 2801 | /** Offset 0x0893 - PCH Psf lock bit |
| 2802 | The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable. |
| 2803 | $EN_DIS |
| 2804 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2805 | UINT8 PchSbAccessUnlock; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2806 | |
| 2807 | /** Offset 0x0894 - PCIE RP Ltr Max Snoop Latency |
| 2808 | Latency Tolerance Reporting, Max Snoop Latency. |
| 2809 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2810 | UINT16 PcieRpLtrMaxSnoopLatency[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2811 | |
| 2812 | /** Offset 0x08C4 - PCIE RP Ltr Max No Snoop Latency |
| 2813 | Latency Tolerance Reporting, Max Non-Snoop Latency. |
| 2814 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2815 | UINT16 PcieRpLtrMaxNoSnoopLatency[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2816 | |
| 2817 | /** Offset 0x08F4 - PCIE RP Snoop Latency Override Mode |
| 2818 | Latency Tolerance Reporting, Snoop Latency Override Mode. |
| 2819 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2820 | UINT8 PcieRpSnoopLatencyOverrideMode[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2821 | |
| 2822 | /** Offset 0x090C - PCIE RP Snoop Latency Override Multiplier |
| 2823 | Latency Tolerance Reporting, Snoop Latency Override Multiplier. |
| 2824 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2825 | UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2826 | |
| 2827 | /** Offset 0x0924 - PCIE RP Snoop Latency Override Value |
| 2828 | Latency Tolerance Reporting, Snoop Latency Override Value. |
| 2829 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2830 | UINT16 PcieRpSnoopLatencyOverrideValue[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2831 | |
| 2832 | /** Offset 0x0954 - PCIE RP Non Snoop Latency Override Mode |
| 2833 | Latency Tolerance Reporting, Non-Snoop Latency Override Mode. |
| 2834 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2835 | UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2836 | |
| 2837 | /** Offset 0x096C - PCIE RP Non Snoop Latency Override Multiplier |
| 2838 | Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. |
| 2839 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2840 | UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2841 | |
| 2842 | /** Offset 0x0984 - PCIE RP Non Snoop Latency Override Value |
| 2843 | Latency Tolerance Reporting, Non-Snoop Latency Override Value. |
| 2844 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2845 | UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2846 | |
| 2847 | /** Offset 0x09B4 - PCIE RP Slot Power Limit Scale |
| 2848 | Specifies scale used for slot power limit value. Leave as 0 to set to default. |
| 2849 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2850 | UINT8 PcieRpSlotPowerLimitScale[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2851 | |
| 2852 | /** Offset 0x09CC - PCIE RP Slot Power Limit Value |
| 2853 | Specifies upper limit on power supplie by slot. Leave as 0 to set to default. |
| 2854 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2855 | UINT16 PcieRpSlotPowerLimitValue[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2856 | |
| 2857 | /** Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset |
| 2858 | Used during Gen3 Link Equalization. Used for all lanes. Default is 5. |
| 2859 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2860 | UINT8 PcieRpUptp[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2861 | |
| 2862 | /** Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset |
| 2863 | Used during Gen3 Link Equalization. Used for all lanes. Default is 7. |
| 2864 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2865 | UINT8 PcieRpDptp[24]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2866 | |
| 2867 | /** Offset 0x0A2C - PCIE RP Enable Port8xh Decode |
| 2868 | This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; |
| 2869 | 1: Enable. |
| 2870 | $EN_DIS |
| 2871 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2872 | UINT8 PcieEnablePort8xhDecode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2873 | |
| 2874 | /** Offset 0x0A2D - PCIE Port8xh Decode Port Index |
| 2875 | The Index of PCIe Port that is selected for Port8xh Decode (0 Based). |
| 2876 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2877 | UINT8 PchPciePort8xhDecodePortIndex; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2878 | |
| 2879 | /** Offset 0x0A2E - PCH Pm Disable Energy Report |
| 2880 | Disable/Enable PCH to CPU enery report feature. |
| 2881 | $EN_DIS |
| 2882 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2883 | UINT8 PchPmDisableEnergyReport; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2884 | |
| 2885 | /** Offset 0x0A2F - PCH Pm Pmc Read Disable |
| 2886 | When set to true, this bit disallows host reads to PMC XRAM. |
| 2887 | $EN_DIS |
| 2888 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2889 | UINT8 PchPmPmcReadDisable; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2890 | |
| 2891 | /** Offset 0x0A30 - PCH Sata Test Mode |
| 2892 | Allow entrance to the PCH SATA test modes. |
| 2893 | $EN_DIS |
| 2894 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2895 | UINT8 SataTestMode; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2896 | |
| 2897 | /** Offset 0x0A31 |
| 2898 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2899 | UINT8 ReservedFspsTestUpd[15]; |
| 2900 | } FSP_S_TEST_CONFIG; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2901 | |
| 2902 | /** Fsp S UPD Configuration |
| 2903 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2904 | typedef struct { |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2905 | |
| 2906 | /** Offset 0x0000 |
| 2907 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2908 | FSP_UPD_HEADER FspUpdHeader; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2909 | |
| 2910 | /** Offset 0x0020 |
| 2911 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2912 | FSP_S_CONFIG FspsConfig; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2913 | |
| 2914 | /** Offset 0x077D |
| 2915 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2916 | FSP_S_TEST_CONFIG FspsTestConfig; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2917 | |
| 2918 | /** Offset 0x0A40 |
| 2919 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2920 | UINT8 UnusedUpdSpace24[474]; |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2921 | |
| 2922 | /** Offset 0x0C1A |
| 2923 | **/ |
Rizwan Qureshi | d2ec569 | 2016-09-07 13:09:36 +0530 | [diff] [blame^] | 2924 | UINT16 UpdTerminator; |
| 2925 | } FSPS_UPD; |
| 2926 | |
| 2927 | #pragma pack(pop) |
Rizwan Qureshi | da723ce | 2016-08-03 12:23:18 +0530 | [diff] [blame] | 2928 | |
| 2929 | #endif |