Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <delay.h> |
Arthur Heymans | 2aeb2a1 | 2021-07-02 10:05:09 +0200 | [diff] [blame] | 6 | #include <stdint.h> |
Angel Pons | 41e66ac | 2020-09-15 13:17:23 +0200 | [diff] [blame] | 7 | #include "raminit.h" |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 8 | #include "x4x.h" |
| 9 | |
| 10 | #define MAX_COARSE 15 |
| 11 | #define DQS_HIGH 1 |
| 12 | #define DQS_LOW 0 |
| 13 | |
Angel Pons | d059112 | 2021-05-26 14:24:06 +0200 | [diff] [blame] | 14 | #define RESET_CNTL(channel) (0x5d8 + (channel) * 0x400) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 15 | |
| 16 | struct rec_timing { |
| 17 | u8 medium; |
| 18 | u8 coarse; |
| 19 | u8 pi; |
| 20 | u8 tap; |
| 21 | }; |
| 22 | |
Angel Pons | 879c4de | 2020-07-24 16:15:04 +0200 | [diff] [blame] | 23 | static inline void mfence(void) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 24 | { |
| 25 | asm volatile("mfence":::); |
| 26 | } |
| 27 | |
| 28 | static u8 sampledqs(u32 addr, u8 lane, u8 channel) |
| 29 | { |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 30 | u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; |
| 31 | |
Angel Pons | bc15e01 | 2021-01-12 23:38:44 +0100 | [diff] [blame] | 32 | /* Reset the DQS probe, on both channels? */ |
| 33 | for (u8 i = 0; i < TOTAL_CHANNELS; i++) { |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 34 | mchbar_clrbits8(RESET_CNTL(i), 1 << 1); |
Angel Pons | bc15e01 | 2021-01-12 23:38:44 +0100 | [diff] [blame] | 35 | udelay(1); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 36 | mchbar_setbits8(RESET_CNTL(i), 1 << 1); |
Angel Pons | bc15e01 | 2021-01-12 23:38:44 +0100 | [diff] [blame] | 37 | udelay(1); |
| 38 | } |
Angel Pons | 879c4de | 2020-07-24 16:15:04 +0200 | [diff] [blame] | 39 | mfence(); |
Elyes HAOUAS | 2dbc095 | 2019-05-22 21:44:48 +0200 | [diff] [blame] | 40 | /* Read strobe */ |
Arthur Heymans | 4d06ff0 | 2021-07-02 10:05:09 +0200 | [diff] [blame] | 41 | read32p(addr); |
Angel Pons | 879c4de | 2020-07-24 16:15:04 +0200 | [diff] [blame] | 42 | mfence(); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 43 | return mchbar_read8(sample_offset) >> 6 & 1; |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 44 | } |
| 45 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 46 | static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 47 | { |
| 48 | u32 reg32; |
| 49 | u16 reg16; |
| 50 | u8 reg8; |
| 51 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 52 | printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n", |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 53 | timing->coarse, timing->medium, timing->tap, timing->pi); |
| 54 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 55 | reg32 = mchbar_read32(0x400 * channel + 0x248); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 56 | reg32 &= ~0xf0000; |
| 57 | reg32 |= timing->coarse << 16; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 58 | mchbar_write32(0x400 * channel + 0x248, reg32); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 59 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 60 | reg16 = mchbar_read16(0x400 * channel + 0x58c); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 61 | reg16 &= ~(3 << (lane * 2)); |
| 62 | reg16 |= timing->medium << (lane * 2); |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 63 | mchbar_write16(0x400 * channel + 0x58c, reg16); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 64 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 65 | reg8 = mchbar_read8(0x400 * channel + 0x560 + lane * 4); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 66 | reg8 &= ~0x7f; |
| 67 | reg8 |= timing->tap; |
| 68 | reg8 |= timing->pi << 4; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 69 | mchbar_write8(0x400 * channel + 0x560 + lane * 4, reg8); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | static int increase_medium(struct rec_timing *timing) |
| 73 | { |
| 74 | if (timing->medium < 3) { |
| 75 | timing->medium++; |
| 76 | } else if (timing->coarse < MAX_COARSE) { |
| 77 | timing->medium = 0; |
| 78 | timing->coarse++; |
| 79 | } else { |
| 80 | printk(BIOS_ERR, "Cannot increase medium any further.\n"); |
| 81 | return -1; |
| 82 | } |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | static int decrease_medium(struct rec_timing *timing) |
| 87 | { |
| 88 | if (timing->medium > 0) { |
| 89 | timing->medium--; |
| 90 | } else if (timing->coarse > 0) { |
| 91 | timing->medium = 3; |
| 92 | timing->coarse--; |
| 93 | } else { |
| 94 | printk(BIOS_ERR, "Cannot lower medium any further.\n"); |
| 95 | return -1; |
| 96 | } |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static int increase_tap(struct rec_timing *timing) |
| 101 | { |
| 102 | if (timing->tap == 14) { |
| 103 | if (increase_medium(timing)) |
| 104 | return -1; |
| 105 | timing->tap = 0; |
| 106 | } else { |
| 107 | timing->tap++; |
| 108 | } |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | static int decrease_tap(struct rec_timing *timing) |
| 113 | { |
| 114 | if (timing->tap > 0) { |
| 115 | timing->tap--; |
| 116 | } else { |
| 117 | if (decrease_medium(timing)) |
| 118 | return -1; |
| 119 | timing->tap = 14; |
| 120 | } |
| 121 | return 0; |
| 122 | } |
| 123 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 124 | static int decr_coarse_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 125 | { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 126 | printk(RAM_DEBUG, " Decreasing coarse until high to low transition is found\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 127 | while (sampledqs(addr, lane, channel) != DQS_LOW) { |
| 128 | if (timing->coarse == 0) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 129 | printk(BIOS_CRIT, "Couldn't find DQS-high 0 indicator, halt\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 130 | return -1; |
| 131 | } |
| 132 | timing->coarse--; |
| 133 | program_timing(timing, channel, lane); |
| 134 | } |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 135 | printk(RAM_DEBUG, " DQS low at coarse=%d medium=%d\n", |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 136 | timing->coarse, timing->medium); |
| 137 | return 0; |
| 138 | } |
| 139 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 140 | static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 141 | { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 142 | printk(RAM_DEBUG, " Increasing TAP until low to high transition is found\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 143 | /* |
| 144 | * We use a do while loop since it happens that the strobe read |
| 145 | * is inconsistent, with the strobe already high. The current |
| 146 | * code flow results in failure later when finding the preamble, |
| 147 | * at which DQS needs to be high is often not the case if TAP was |
| 148 | * not increased at least once here. Work around this by incrementing |
| 149 | * TAP at least once to guarantee searching for preamble start at |
| 150 | * DQS high. |
| 151 | * This seems to be the result of hysteresis on some settings, where |
| 152 | * the DQS probe is influenced by its previous value. |
| 153 | */ |
| 154 | if (sampledqs(addr, lane, channel) == DQS_HIGH) { |
| 155 | printk(BIOS_WARNING, |
| 156 | "DQS already HIGH... DQS probe is inconsistent!\n" |
| 157 | "Continuing....\n"); |
| 158 | } |
| 159 | do { |
| 160 | if (increase_tap(timing)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 161 | printk(BIOS_CRIT, "Could not find DQS-high on fine search.\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 162 | return -1; |
| 163 | } |
| 164 | program_timing(timing, channel, lane); |
| 165 | } while (sampledqs(addr, lane, channel) != DQS_HIGH); |
| 166 | |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 167 | printk(RAM_DEBUG, " DQS high at coarse=%d medium=%d tap:%d\n", |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 168 | timing->coarse, timing->medium, timing->tap); |
| 169 | return 0; |
| 170 | } |
| 171 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 172 | static int find_dqs_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 173 | { |
| 174 | /* Look for DQS low, using quarter steps. */ |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 175 | printk(RAM_DEBUG, " Increasing medium until DQS LOW is found\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 176 | while (sampledqs(addr, lane, channel) != DQS_LOW) { |
| 177 | if (increase_medium(timing)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 178 | printk(BIOS_CRIT, "Coarse > 15: DQS tuning failed, halt\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 179 | return -1; |
| 180 | } |
| 181 | program_timing(timing, channel, lane); |
| 182 | } |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 183 | printk(RAM_DEBUG, " DQS low at coarse=%d medium=%d\n", |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 184 | timing->coarse, timing->medium); |
| 185 | return 0; |
| 186 | } |
| 187 | static int find_dqs_high(u8 channel, u8 lane, u32 addr, |
| 188 | struct rec_timing *timing) |
| 189 | { |
| 190 | /* Look for DQS high, using quarter steps. */ |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 191 | printk(RAM_DEBUG, " Increasing medium until DQS HIGH is found\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 192 | while (sampledqs(addr, lane, channel) != DQS_HIGH) { |
| 193 | if (increase_medium(timing)) { |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 194 | printk(BIOS_CRIT, "Coarse > 16: DQS tuning failed, halt\n"); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 195 | return -1; |
| 196 | } |
| 197 | program_timing(timing, channel, lane); |
| 198 | } |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 199 | printk(RAM_DEBUG, " DQS high at coarse=%d medium=%d\n", |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 200 | timing->coarse, timing->medium); |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | static int find_dqs_edge_lowhigh(u8 channel, u8 lane, |
| 205 | u32 addr, struct rec_timing *timing) |
| 206 | { |
| 207 | /* Medium search for DQS high. */ |
| 208 | if (find_dqs_high(channel, lane, addr, timing)) |
| 209 | return -1; |
| 210 | |
| 211 | /* Go back and perform finer search. */ |
| 212 | if (decrease_medium(timing)) |
| 213 | return -1; |
| 214 | program_timing(timing, channel, lane); |
| 215 | if (fine_search_dqs_high(channel, lane, addr, timing) < 0) |
| 216 | return -1; |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | static int find_preamble(u8 channel, u8 lane, u32 addr, |
| 222 | struct rec_timing *timing) |
| 223 | { |
| 224 | /* Add a quarter step */ |
| 225 | if (increase_medium(timing)) |
| 226 | return -1; |
| 227 | program_timing(timing, channel, lane); |
| 228 | /* Verify we are at high */ |
| 229 | if (sampledqs(addr, lane, channel) != DQS_HIGH) { |
| 230 | printk(BIOS_CRIT, "Not at DQS high, d'oh\n"); |
| 231 | return -1; |
| 232 | } |
| 233 | |
| 234 | /* Decrease coarse until LOW is found */ |
| 235 | if (decr_coarse_low(channel, lane, addr, timing)) |
| 236 | return -1; |
| 237 | return 0; |
| 238 | } |
| 239 | |
| 240 | static int calibrate_receive_enable(u8 channel, u8 lane, |
| 241 | u32 addr, struct rec_timing *timing) |
| 242 | { |
| 243 | program_timing(timing, channel, lane); |
| 244 | /* Set receive enable bit */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 245 | mchbar_clrsetbits16(0x400 * channel + 0x588, 3 << (lane * 2), 1 << (lane * 2)); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 246 | |
| 247 | if (find_dqs_low(channel, lane, addr, timing)) |
| 248 | return -1; |
| 249 | |
| 250 | /* Advance a little further. */ |
| 251 | if (increase_medium(timing)) { |
| 252 | /* A finer search could be implemented */ |
| 253 | printk(BIOS_WARNING, "Cannot increase medium further"); |
| 254 | return -1; |
| 255 | } |
| 256 | program_timing(timing, channel, lane); |
| 257 | |
| 258 | if (find_dqs_edge_lowhigh(channel, lane, addr, timing)) |
| 259 | return -1; |
| 260 | |
| 261 | /* Go back on fine search */ |
| 262 | if (decrease_tap(timing)) |
| 263 | return -1; |
| 264 | timing->pi = 3; |
| 265 | program_timing(timing, channel, lane); |
| 266 | |
| 267 | if (find_preamble(channel, lane, addr, timing)) |
| 268 | return -1; |
| 269 | |
| 270 | if (find_dqs_edge_lowhigh(channel, lane, addr, timing)) |
| 271 | return -1; |
| 272 | if (decrease_tap(timing)) |
| 273 | return -1; |
| 274 | timing->pi = 7; |
| 275 | program_timing(timing, channel, lane); |
| 276 | |
| 277 | /* Unset receive enable bit */ |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 278 | mchbar_clrbits16(0x400 * channel + 0x588, 3 << (lane * 2)); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 279 | return 0; |
| 280 | } |
| 281 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 282 | void rcven(struct sysinfo *s) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 283 | { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 284 | int rank; |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 285 | u8 channel, lane, reg8; |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 286 | /* |
| 287 | * Using the macros below the compiler warns about this possibly being |
| 288 | * unitialised. |
| 289 | */ |
| 290 | u32 addr = 0; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 291 | struct rec_timing timing[TOTAL_BYTELANES]; |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 292 | u8 mincoarse; |
| 293 | |
Arthur Heymans | a4e8f67b | 2017-12-16 21:04:46 +0100 | [diff] [blame] | 294 | printk(BIOS_DEBUG, "Starting DQS receiver enable calibration\n"); |
| 295 | |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 296 | mchbar_clrbits8(0x5d8, 3 << 2); |
| 297 | mchbar_clrbits8(0x9d8, 3 << 2); |
| 298 | mchbar_clrbits8(0x5dc, 1 << 7); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 299 | FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 300 | mincoarse = 0xff; |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 301 | /* |
| 302 | * Receive enable calibration happens on the first populated |
| 303 | * rank on each channel. |
| 304 | */ |
| 305 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) { |
| 306 | addr = test_address(channel, rank); |
| 307 | break; |
| 308 | } |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 309 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 310 | printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n", |
| 311 | channel, lane, addr); |
| 312 | timing[lane].coarse = (s->selected_timings.CAS + 1); |
| 313 | switch (lane) { |
| 314 | default: |
| 315 | case 0: |
| 316 | case 1: |
| 317 | timing[lane].medium = 0; |
| 318 | break; |
| 319 | case 2: |
| 320 | case 3: |
| 321 | timing[lane].medium = 1; |
| 322 | break; |
| 323 | case 4: |
| 324 | case 5: |
| 325 | timing[lane].medium = 2; |
| 326 | break; |
| 327 | case 6: |
| 328 | case 7: |
| 329 | timing[lane].medium = 3; |
| 330 | break; |
| 331 | } |
| 332 | timing[lane].tap = 0; |
| 333 | timing[lane].pi = 0; |
| 334 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 335 | if (calibrate_receive_enable(channel, lane, addr, &timing[lane])) |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 336 | die("Receive enable calibration failed\n"); |
| 337 | if (mincoarse > timing[lane].coarse) |
| 338 | mincoarse = timing[lane].coarse; |
| 339 | } |
| 340 | printk(BIOS_DEBUG, "Found min coarse value = %d\n", mincoarse); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 341 | s->rcven_t[channel].min_common_coarse = mincoarse; |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 342 | printk(BIOS_DEBUG, "Receive enable, final timings:\n"); |
| 343 | /* Normalise coarse */ |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 344 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 345 | if (timing[lane].coarse == 0) |
| 346 | reg8 = 0; |
| 347 | else |
| 348 | reg8 = timing[lane].coarse - mincoarse; |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 349 | printk(BIOS_DEBUG, |
| 350 | "ch %d lane %d: coarse offset: %d;medium: %d; tap: %d\n", |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 351 | channel, lane, reg8, timing[lane].medium, |
| 352 | timing[lane].tap); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 353 | s->rcven_t[channel].coarse_offset[lane] = reg8; |
| 354 | s->rcven_t[channel].medium[lane] = timing[lane].medium; |
| 355 | s->rcven_t[channel].tap[lane] = timing[lane].tap; |
| 356 | s->rcven_t[channel].pi[lane] = timing[lane].pi; |
Angel Pons | a5146f3 | 2021-03-27 09:35:57 +0100 | [diff] [blame] | 357 | mchbar_clrsetbits16(0x400 * channel + 0x5fa, 3 << (lane * 2), |
| 358 | reg8 << (lane * 2)); |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 359 | } |
| 360 | /* simply use timing[0] to program mincoarse */ |
| 361 | timing[0].coarse = mincoarse; |
| 362 | program_timing(&timing[0], channel, 0); |
| 363 | } |
| 364 | } |