Blame - src/mainboard/lenovo/x60/cmos.layout - coreboot

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Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	1	#
				2	# This file is part of the coreboot project.
				3	#
				4	# Copyright (C) 2007-2008 coresystems GmbH
				5	#
				6	# This program is free software; you can redistribute it and/or
				7	# modify it under the terms of the GNU General Public License as
				8	# published by the Free Software Foundation; version 2 of
				9	# the License.
				10	#
				11	# This program is distributed in the hope that it will be useful,
				12	# but WITHOUT ANY WARRANTY; without even the implied warranty of
				13	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				14	# GNU General Public License for more details.
				15	#
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	16
				17	# -----------------------------------------------------------------
				18	entries
				19
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	20	# -----------------------------------------------------------------
				21	# Status Register A
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	22	# -----------------------------------------------------------------
				23	# Status Register B
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	24	# -----------------------------------------------------------------
				25	# Status Register C
				26	#96 4 r 0 status_c_rsvd
				27	#100 1 r 0 uf_flag
				28	#101 1 r 0 af_flag
				29	#102 1 r 0 pf_flag
				30	#103 1 r 0 irqf_flag
				31	# -----------------------------------------------------------------
				32	# Status Register D
				33	#104 7 r 0 status_d_rsvd
				34	#111 1 r 0 valid_cmos_ram
				35	# -----------------------------------------------------------------
				36	# Diagnostic Status Register
				37	#112 8 r 0 diag_rsvd1
				38
				39	# -----------------------------------------------------------------
				40	0 120 r 0 reserved_memory
				41	#120 264 r 0 unused
				42
				43	# -----------------------------------------------------------------
				44	# RTC_BOOT_BYTE (coreboot hardcoded)
				45	384 1 e 4 boot_option
Nico Huber	d23ee5d	2016-08-11 22:45:55 +0200	[diff] [blame^]	46	388 4 h 0 reboot_counter
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	47	#390 2 r 0 unused?
				48
				49	# -----------------------------------------------------------------
				50	# coreboot config options: console
				51	392 3 e 5 baud_rate
				52	395 4 e 6 debug_level
				53	#399 1 r 0 unused
				54
Alexander Couzens	f8970f5	2015-10-10 16:04:59 +0200	[diff] [blame]	55	#400 8 r 0 reserved for century byte
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	56
				57	# coreboot config options: southbridge
				58	408 1 e 1 nmi
				59	#409 2 e 7 power_on_after_fail
				60	#411 5 r 0 unused
				61
				62	# coreboot config options: bootloader
				63	416 512 s 0 boot_devices
				64	928 8 h 0 boot_default
				65	936 1 e 8 cmos_defaults_loaded
				66	937 1 e 1 lpt
Alexander Couzens	f8970f5	2015-10-10 16:04:59 +0200	[diff] [blame]	67	#938 6 r 0 unused
				68
				69	# coreboot config options: cpu
				70	944 1 e 2 hyper_threading
				71	#945 7 r 0 unused
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	72
				73	# coreboot config options: check sums
				74	984 16 h 0 check_sum
				75	#1000 24 r 0 amd_reserved
				76
Elyes HAOUAS	8ab989e	2016-07-30 17:46:17 +0200	[diff] [blame]	77	# RAM initialization internal data
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	78	1024 8 r 0 C0WL0REOST
				79	1032 8 r 0 C1WL0REOST
				80	1040 8 r 0 RCVENMT
				81	1048 4 r 0 C0DRT1
				82	1052 4 r 0 C1DRT1
				83
Sven Schnelle	1b8068e	2011-06-05 20:47:49 +0200	[diff] [blame]	84	1064 8 h 0 volume
Sven Schnelle	4297a9a	2011-06-12 14:35:11 +0200	[diff] [blame]	85	1072 8 h 0 tft_brightness
Sven Schnelle	d5992b8	2011-12-07 14:30:58 -0800	[diff] [blame]	86	1080 1 e 9 first_battery
Paul Menzel	55b0593	2013-11-13 23:05:23 +0100	[diff] [blame]	87	1081 1 e 1 bluetooth
Vladimir Serbinenko	f422a44	2013-11-13 21:53:23 +0100	[diff] [blame]	88	1082 1 e 1 wwan
Vladimir Serbinenko	8e7e525	2014-01-11 03:45:53 +0100	[diff] [blame]	89	1083 1 e 1 wlan
Vladimir Serbinenko	eada34f	2014-01-11 04:22:35 +0100	[diff] [blame]	90	1084 1 e 1 trackpoint
Vladimir Serbinenko	fc7090b	2014-01-11 10:29:14 +0100	[diff] [blame]	91	1085 1 e 1 fn_ctrl_swap
Vladimir Serbinenko	11a7c84	2014-01-11 10:55:31 +0100	[diff] [blame]	92	1086 1 e 1 sticky_fn
Vladimir Serbinenko	9a3b9c4	2014-01-11 20:56:47 +0100	[diff] [blame]	93	1087 1 e 1 power_management_beeps
Vladimir Serbinenko	add3f7f	2014-01-11 20:58:20 +0100	[diff] [blame]	94	1088 1 e 1 low_battery_beep
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	95	# -----------------------------------------------------------------
				96
				97	enumerations
				98
				99	#ID value text
				100	1 0 Disable
				101	1 1 Enable
				102	2 0 Enable
				103	2 1 Disable
				104	4 0 Fallback
				105	4 1 Normal
				106	5 0 115200
				107	5 1 57600
				108	5 2 38400
				109	5 3 19200
				110	5 4 9600
				111	5 5 4800
				112	5 6 2400
				113	5 7 1200
				114	6 1 Emergency
				115	6 2 Alert
				116	6 3 Critical
				117	6 4 Error
				118	6 5 Warning
				119	6 6 Notice
				120	6 7 Info
				121	6 8 Debug
				122	6 9 Spew
				123	7 0 Disable
				124	7 1 Enable
				125	7 2 Keep
				126	8 0 No
				127	8 1 Yes
Sven Schnelle	d5992b8	2011-12-07 14:30:58 -0800	[diff] [blame]	128	9 0 Secondary
				129	9 1 Primary
Sven Schnelle	e2ca71e	2011-02-14 20:02:47 +0000	[diff] [blame]	130
				131	# -----------------------------------------------------------------
				132	checksums
				133
				134	checksum 392 983 984