Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | # Lock Down |
| 3 | register "common_soc_config" = "{ |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 4 | .i2c[0] = { |
| 5 | .speed = I2C_SPEED_FAST, |
| 6 | .rise_time_ns = 80, |
| 7 | .fall_time_ns = 110, |
| 8 | }, |
| 9 | }" |
| 10 | |
| 11 | # CPU (soc/intel/cannonlake/cpu.c) |
| 12 | # Power limit |
| 13 | register "power_limits_config" = "{ |
| 14 | .tdp_pl1_override = 20, |
| 15 | .tdp_pl2_override = 30, |
| 16 | }" |
| 17 | |
| 18 | # Enable Enhanced Intel SpeedStep |
| 19 | register "eist_enable" = "1" |
| 20 | |
| 21 | # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) |
| 22 | register "SaGv" = "SaGv_Enabled" |
| 23 | register "enable_c6dram" = "1" |
| 24 | |
| 25 | # FSP Silicon (soc/intel/cannonlake/fsp_params.c) |
| 26 | # Serial I/O |
| 27 | register "SerialIoDevMode" = "{ |
| 28 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 29 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 30 | }" |
| 31 | |
| 32 | # Misc |
| 33 | register "AcousticNoiseMitigation" = "1" |
| 34 | |
| 35 | # Power |
| 36 | register "PchPmSlpS3MinAssert" = "3" # 50ms |
| 37 | register "PchPmSlpS4MinAssert" = "1" # 1s |
| 38 | register "PchPmSlpSusMinAssert" = "2" # 500ms |
| 39 | register "PchPmSlpAMinAssert" = "4" # 2s |
| 40 | |
| 41 | # Thermal |
| 42 | register "tcc_offset" = "12" |
| 43 | |
| 44 | # Serial IRQ Continuous |
| 45 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 46 | |
| 47 | # PM Util (soc/intel/cannonlake/pmutil.c) |
| 48 | # GPE configuration |
| 49 | # Note that GPE events called out in ASL code rely on this |
| 50 | # route. i.e. If this route changes then the affected GPE |
| 51 | # offset bits also need to be changed. |
| 52 | register "gpe0_dw0" = "PMC_GPP_C" |
| 53 | register "gpe0_dw1" = "PMC_GPP_D" |
| 54 | register "gpe0_dw2" = "PMC_GPP_E" |
| 55 | |
| 56 | # Actual device tree |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 57 | device cpu_cluster 0 on end |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 58 | |
| 59 | device domain 0 on |
| 60 | device pci 00.0 on end # Host Bridge |
| 61 | device pci 02.0 on # Integrated Graphics Device |
| 62 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 63 | end |
| 64 | device pci 04.0 on # SA Thermal device |
| 65 | register "Device4Enable" = "1" |
| 66 | end |
| 67 | device pci 12.0 on end # Thermal Subsystem |
| 68 | device pci 12.5 off end # UFS SCS |
| 69 | device pci 12.6 off end # GSPI #2 |
| 70 | device pci 13.0 off end # Integrated Sensor Hub |
| 71 | device pci 14.0 on # USB xHCI |
Felix Singer | d163253 | 2023-10-26 15:02:46 +0200 | [diff] [blame^] | 72 | register "usb2_ports" = "{ |
| 73 | [0] = USB2_PORT_MID(OC_SKIP), /* USB-A */ |
| 74 | [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */ |
| 75 | [2] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C */ |
| 76 | [3] = USB2_PORT_MID(OC_SKIP), /* USB-A */ |
| 77 | [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */ |
| 78 | [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| 79 | }" |
| 80 | register "usb3_ports" = "{ |
| 81 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-A */ |
| 82 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G on galp3-c, NC on darp5 */ |
| 83 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C */ |
| 84 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-A */ |
| 85 | [4] = USB3_PORT_EMPTY, /* Used by TBT */ |
| 86 | [5] = USB3_PORT_EMPTY, /* Used by TBT */ |
| 87 | }" |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 88 | end |
| 89 | device pci 14.1 off end # USB xDCI (OTG) |
| 90 | device pci 14.3 on # CNVi wifi |
| 91 | chip drivers/wifi/generic |
| 92 | register "wake" = "PME_B0_EN_BIT" |
Nico Huber | 81d4c80 | 2021-09-07 16:50:09 +0200 | [diff] [blame] | 93 | device generic 0 on end |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 94 | end |
| 95 | end |
| 96 | device pci 14.5 off end # SDCard |
| 97 | device pci 15.0 on end # I2C #0 |
| 98 | device pci 15.1 off end # I2C #1 |
| 99 | device pci 15.2 off end # I2C #2 |
| 100 | device pci 15.3 off end # I2C #3 |
Tim Crawford | 12a98ff | 2021-11-22 08:57:08 -0700 | [diff] [blame] | 101 | device pci 16.0 on end # Management Engine Interface 1 |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 102 | device pci 16.1 off end # Management Engine Interface 2 |
| 103 | device pci 16.2 off end # Management Engine IDE-R |
| 104 | device pci 16.3 off end # Management Engine KT Redirection |
| 105 | device pci 16.4 off end # Management Engine Interface 3 |
| 106 | device pci 16.5 off end # Management Engine Interface 4 |
| 107 | device pci 17.0 on # SATA |
Felix Singer | d163253 | 2023-10-26 15:02:46 +0200 | [diff] [blame^] | 108 | register "SataPortsEnable" = "{ |
| 109 | [0] = 1, |
| 110 | [2] = 1, |
| 111 | }" |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 112 | end |
| 113 | device pci 19.0 off end # I2C #4 |
| 114 | device pci 19.1 off end # I2C #5 |
| 115 | device pci 19.2 on end # UART #2 |
| 116 | device pci 1a.0 off end # eMMC |
| 117 | device pci 1c.0 on end # PCI Express Port 1 |
| 118 | device pci 1c.1 off end # PCI Express Port 2 |
| 119 | device pci 1c.2 off end # PCI Express Port 3 |
| 120 | device pci 1c.3 off end # PCI Express Port 4 |
| 121 | device pci 1c.4 on # PCI Express Port 5 |
| 122 | # PCI Express Root port #5 x4, Clock 4 (TBT) |
| 123 | register "PcieRpEnable[4]" = "1" |
| 124 | register "PcieRpLtrEnable[4]" = "1" |
| 125 | register "PcieRpHotPlug[4]" = "1" |
| 126 | register "PcieClkSrcUsage[4]" = "4" |
| 127 | register "PcieClkSrcClkReq[4]" = "4" |
| 128 | end |
| 129 | device pci 1c.5 off end # PCI Express Port 6 |
| 130 | device pci 1c.6 off end # PCI Express Port 7 |
| 131 | device pci 1c.7 off end # PCI Express Port 8 |
| 132 | device pci 1d.0 on # PCI Express Port 9 |
| 133 | # PCI Express Root port #9 x1, Clock 3 (LAN) |
| 134 | register "PcieRpEnable[8]" = "1" |
| 135 | register "PcieRpLtrEnable[8]" = "1" |
| 136 | register "PcieClkSrcUsage[3]" = "8" |
| 137 | register "PcieClkSrcClkReq[3]" = "3" |
| 138 | end |
| 139 | device pci 1d.1 on # PCI Express Port 10 |
| 140 | # PCI Express Root port #10 x1, Clock 2 (WLAN) |
| 141 | register "PcieRpEnable[9]" = "1" |
| 142 | register "PcieRpLtrEnable[9]" = "0" |
| 143 | register "PcieClkSrcUsage[2]" = "9" |
| 144 | register "PcieClkSrcClkReq[2]" = "2" |
| 145 | end |
| 146 | device pci 1d.2 off end # PCI Express Port 11 |
| 147 | device pci 1d.3 off end # PCI Express Port 12 |
| 148 | device pci 1d.4 on # PCI Express Port 13 |
| 149 | # PCI Express Root port #13 x4, Clock 5 (NVMe) |
| 150 | register "PcieRpEnable[12]" = "1" |
| 151 | register "PcieRpLtrEnable[12]" = "1" |
| 152 | register "PcieClkSrcUsage[5]" = "12" |
| 153 | register "PcieClkSrcClkReq[5]" = "5" |
| 154 | end |
| 155 | device pci 1d.5 off end # PCI Express Port 14 |
| 156 | device pci 1d.6 off end # PCI Express Port 15 |
| 157 | device pci 1d.7 off end # PCI Express Port 16 |
| 158 | device pci 1e.0 off end # UART #0 |
| 159 | device pci 1e.1 off end # UART #1 |
| 160 | device pci 1e.2 off end # GSPI #0 |
| 161 | device pci 1e.3 off end # GSPI #1 |
| 162 | device pci 1f.0 on # LPC Interface |
| 163 | register "gen1_dec" = "0x000c0081" |
| 164 | register "gen2_dec" = "0x00040069" |
| 165 | register "gen3_dec" = "0x00fc0e01" |
| 166 | register "gen4_dec" = "0x00fc0f01" |
| 167 | chip drivers/pc80/tpm |
| 168 | device pnp 0c31.0 on end |
| 169 | end |
| 170 | end |
| 171 | device pci 1f.1 off end # P2SB |
Tim Wawrzynczak | b7b5115 | 2021-07-01 08:38:30 -0600 | [diff] [blame] | 172 | device pci 1f.2 hidden end # Power Management Controller |
Tim Crawford | 3647e86 | 2021-03-25 16:40:53 -0600 | [diff] [blame] | 173 | device pci 1f.3 on # Intel HDA |
| 174 | register "PchHdaAudioLinkHda" = "1" |
| 175 | register "PchHdaAudioLinkDmic0" = "1" |
| 176 | register "PchHdaAudioLinkDmic1" = "1" |
| 177 | end |
| 178 | device pci 1f.4 on end # SMBus |
| 179 | device pci 1f.5 on end # PCH SPI |
| 180 | device pci 1f.6 off end # GbE |
| 181 | end |
| 182 | end |