Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 4 | #include <stdint.h> |
| 5 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | #include <device/pci_def.h> |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 9 | #include <device/device.h> |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 10 | #include <device/smbus_host.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 11 | #include <spd.h> |
| 12 | #include <console/console.h> |
| 13 | #include <lib.h> |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 14 | #include <delay.h> |
Arthur Heymans | 049347f | 2017-05-12 11:54:08 +0200 | [diff] [blame] | 15 | #include <timestamp.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 16 | #include "gm45.h" |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 17 | #include "chip.h" |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 18 | |
| 19 | static const gmch_gfx_t gmch_gfx_types[][5] = { |
| 20 | /* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */ |
| 21 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 22 | { GMCH_GM47, GMCH_GM45, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_GM49 }, |
| 23 | { GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45 }, |
| 24 | { GMCH_UNKNOWN, GMCH_GL43, GMCH_GL40, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 25 | { GMCH_UNKNOWN, GMCH_GS45, GMCH_GS40, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 26 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 27 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 28 | { GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45 }, |
| 29 | }; |
| 30 | |
| 31 | void get_gmch_info(sysinfo_t *sysinfo) |
| 32 | { |
| 33 | sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); |
| 34 | if ((sysinfo->stepping > STEPPING_B3) && |
Elyes HAOUAS | 7503cd1 | 2022-01-29 09:33:08 +0100 | [diff] [blame] | 35 | (sysinfo->stepping != STEPPING_CONVERSION_A1)) |
| 36 | die("Unknown stepping.\n"); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 37 | if (sysinfo->stepping <= STEPPING_B3) |
| 38 | printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); |
| 39 | else |
| 40 | printk(BIOS_DEBUG, "Conversion stepping A1\n"); |
| 41 | |
| 42 | const u32 eax = cpuid_ext(0x04, 0).eax; |
| 43 | sysinfo->cores = ((eax >> 26) & 0x3f) + 1; |
| 44 | printk(BIOS_SPEW, "%d CPU cores\n", sysinfo->cores); |
| 45 | |
| 46 | u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_CAPID0+8); |
| 47 | if (!(capid & (1<<(79-64)))) { |
| 48 | printk(BIOS_SPEW, "iTPM enabled\n"); |
| 49 | } |
| 50 | |
| 51 | capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0+4); |
| 52 | if (!(capid & (1<<(57-32)))) { |
| 53 | printk(BIOS_SPEW, "ME enabled\n"); |
| 54 | } |
| 55 | |
| 56 | if (!(capid & (1<<(56-32)))) { |
| 57 | printk(BIOS_SPEW, "AMT enabled\n"); |
| 58 | } |
| 59 | |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 60 | sysinfo->max_ddr2_mt = (capid & (1<<(53-32)))?667:800; |
| 61 | printk(BIOS_SPEW, "capable of DDR2 of %d MHz or lower\n", sysinfo->max_ddr2_mt); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 62 | |
| 63 | if (!(capid & (1<<(48-32)))) { |
| 64 | printk(BIOS_SPEW, "VT-d enabled\n"); |
| 65 | } |
| 66 | |
| 67 | const u32 gfx_variant = (capid>>(42-32)) & 0x7; |
| 68 | const u32 render_freq = ((capid>>(50-32) & 0x1) << 2) | ((capid>>(35-32)) & 0x3); |
| 69 | if (render_freq <= 4) |
| 70 | sysinfo->gfx_type = gmch_gfx_types[gfx_variant][render_freq]; |
| 71 | else |
| 72 | sysinfo->gfx_type = GMCH_UNKNOWN; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 73 | switch (sysinfo->gfx_type) { |
| 74 | case GMCH_GM45: |
| 75 | printk(BIOS_SPEW, "GMCH: GM45\n"); |
| 76 | break; |
| 77 | case GMCH_GM47: |
| 78 | printk(BIOS_SPEW, "GMCH: GM47\n"); |
| 79 | break; |
| 80 | case GMCH_GM49: |
| 81 | printk(BIOS_SPEW, "GMCH: GM49\n"); |
| 82 | break; |
| 83 | case GMCH_GE45: |
| 84 | printk(BIOS_SPEW, "GMCH: GE45\n"); |
| 85 | break; |
| 86 | case GMCH_GL40: |
| 87 | printk(BIOS_SPEW, "GMCH: GL40\n"); |
| 88 | break; |
| 89 | case GMCH_GL43: |
| 90 | printk(BIOS_SPEW, "GMCH: GL43\n"); |
| 91 | break; |
| 92 | case GMCH_GS40: |
| 93 | printk(BIOS_SPEW, "GMCH: GS40\n"); |
| 94 | break; |
| 95 | case GMCH_GS45: |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 96 | printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", |
| 97 | sysinfo->gs45_low_power_mode ? "low" : "high"); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 98 | break; |
| 99 | case GMCH_PM45: |
| 100 | printk(BIOS_SPEW, "GMCH: PM45\n"); |
| 101 | break; |
| 102 | case GMCH_UNKNOWN: |
| 103 | printk(BIOS_SPEW, "unknown GMCH\n"); |
| 104 | break; |
| 105 | } |
| 106 | |
| 107 | sysinfo->txt_enabled = !(capid & (1 << (37-32))); |
| 108 | if (sysinfo->txt_enabled) { |
| 109 | printk(BIOS_SPEW, "TXT enabled\n"); |
| 110 | } |
| 111 | |
| 112 | switch (render_freq) { |
| 113 | case 4: |
| 114 | sysinfo->max_render_mhz = 800; |
| 115 | break; |
| 116 | case 0: |
| 117 | sysinfo->max_render_mhz = 667; |
| 118 | break; |
| 119 | case 1: |
| 120 | sysinfo->max_render_mhz = 533; |
| 121 | break; |
| 122 | case 2: |
| 123 | sysinfo->max_render_mhz = 400; |
| 124 | break; |
| 125 | case 3: |
| 126 | sysinfo->max_render_mhz = 333; |
| 127 | break; |
| 128 | default: |
| 129 | printk(BIOS_SPEW, "Unknown render frequency\n"); |
| 130 | sysinfo->max_render_mhz = 0; |
| 131 | break; |
| 132 | } |
| 133 | if (sysinfo->max_render_mhz != 0) { |
| 134 | printk(BIOS_SPEW, "Render frequency: %d MHz\n", sysinfo->max_render_mhz); |
| 135 | } |
| 136 | |
| 137 | if (!(capid & (1<<(33-32)))) { |
| 138 | printk(BIOS_SPEW, "IGD enabled\n"); |
| 139 | } |
| 140 | |
| 141 | if (!(capid & (1<<(32-32)))) { |
| 142 | printk(BIOS_SPEW, "PCIe-to-GMCH enabled\n"); |
| 143 | } |
| 144 | |
| 145 | capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0); |
| 146 | |
| 147 | u32 ddr_cap = capid>>30 & 0x3; |
| 148 | switch (ddr_cap) { |
| 149 | case 0: |
| 150 | sysinfo->max_ddr3_mt = 1067; |
| 151 | break; |
| 152 | case 1: |
| 153 | sysinfo->max_ddr3_mt = 800; |
| 154 | break; |
| 155 | case 2: |
| 156 | case 3: |
| 157 | printk(BIOS_SPEW, "GMCH not DDR3 capable\n"); |
| 158 | sysinfo->max_ddr3_mt = 0; |
| 159 | break; |
| 160 | } |
| 161 | if (sysinfo->max_ddr3_mt != 0) { |
| 162 | printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt); |
| 163 | } |
| 164 | |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 165 | const unsigned int max_fsb = (capid >> 28) & 0x3; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 166 | switch (max_fsb) { |
| 167 | case 1: |
| 168 | sysinfo->max_fsb_mhz = 1067; |
| 169 | break; |
| 170 | case 2: |
| 171 | sysinfo->max_fsb_mhz = 800; |
| 172 | break; |
| 173 | case 3: |
| 174 | sysinfo->max_fsb_mhz = 667; |
| 175 | break; |
| 176 | default: |
| 177 | die("unknown FSB capability\n"); |
| 178 | break; |
| 179 | } |
| 180 | if (sysinfo->max_fsb_mhz != 0) { |
| 181 | printk(BIOS_SPEW, "GMCH supports FSB with up to %d MHz\n", sysinfo->max_fsb_mhz); |
| 182 | } |
| 183 | sysinfo->max_fsb = max_fsb - 1; |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * Detect if the system went through an interrupted RAM init or is incon- |
| 188 | * sistent. If so, initiate a cold reboot. Otherwise mark the system to be |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 189 | * in RAM init, so this function would detect it on an erroneous reboot. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 190 | */ |
| 191 | void enter_raminit_or_reset(void) |
| 192 | { |
| 193 | /* Interrupted RAM init or inconsistent system? */ |
| 194 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 195 | |
| 196 | if (reg8 & (1 << 2)) { /* S4-assertion-width violation */ |
| 197 | /* Ignore S4-assertion-width violation like original BIOS. */ |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 198 | printk(BIOS_WARNING, "Ignoring S4-assertion-width violation.\n"); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 199 | /* Bit2 is R/WC, so it will clear itself below. */ |
| 200 | } |
| 201 | |
| 202 | if (reg8 & (1 << 7)) { /* interrupted RAM init */ |
| 203 | /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. |
| 204 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 205 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); |
| 206 | */ |
| 207 | |
| 208 | /* Clear bit7. */ |
| 209 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~(1 << 7)); |
| 210 | |
| 211 | printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); |
| 212 | gm45_early_reset(); |
| 213 | } |
| 214 | /* Mark system to be in RAM init. */ |
| 215 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); |
| 216 | } |
| 217 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 218 | /* For a detected DIMM, test the value of an SPD byte to |
| 219 | match the expected value after masking some bits. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 220 | static int test_dimm(sysinfo_t *const sysinfo, |
| 221 | int dimm, int addr, int bitmask, int expected) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 222 | { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 223 | return (smbus_read_byte(sysinfo->spd_map[dimm], addr) & bitmask) == expected; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | /* This function dies if dimm is unsuitable for the chipset. */ |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 227 | static void verify_ddr2_dimm(sysinfo_t *const sysinfo, int dimm) |
| 228 | { |
| 229 | if (!test_dimm(sysinfo, dimm, 20, 0x04, 0x04)) |
| 230 | die("Chipset only supports SO-DIMM\n"); |
| 231 | |
| 232 | if (!test_dimm(sysinfo, dimm, 6, 0xff, 0x40) || |
| 233 | !test_dimm(sysinfo, dimm, 11, 0xff, 0x00)) |
| 234 | die("Chipset doesn't support ECC RAM\n"); |
| 235 | |
| 236 | if (!test_dimm(sysinfo, dimm, 5, 0x07, 0) && |
| 237 | !test_dimm(sysinfo, dimm, 5, 0x07, 1)) |
| 238 | die("Chipset wants single or dual ranked DIMMs\n"); |
| 239 | |
| 240 | /* |
| 241 | * Generally supports: |
| 242 | * x8/x16 |
| 243 | * 4 or 8 banks |
| 244 | * 10 column address bits |
| 245 | * 13, 14 or 15 (x8 only) row address bits |
| 246 | * |
| 247 | * FIXME: There seems to be an exception for 256Gb x16 chips. Not |
| 248 | * covered by the numbers above (9 column address bits?). |
| 249 | */ |
| 250 | if (!test_dimm(sysinfo, dimm, 13, 0xff, 8) && |
| 251 | !test_dimm(sysinfo, dimm, 13, 0xff, 16)) |
| 252 | die("Chipset requires x8 or x16 width\n"); |
| 253 | |
| 254 | if (!test_dimm(sysinfo, dimm, 17, 0xff, 4) && |
| 255 | !test_dimm(sysinfo, dimm, 17, 0xff, 8)) |
| 256 | die("Chipset requires 4 or 8 banks\n"); |
| 257 | |
| 258 | if (!test_dimm(sysinfo, dimm, 4, 0xff, 10)) |
| 259 | die("Chipset requires 10 column address bits\n"); |
| 260 | |
| 261 | if (!test_dimm(sysinfo, dimm, 3, 0xff, 13) && |
| 262 | !test_dimm(sysinfo, dimm, 3, 0xff, 14) && |
| 263 | !(test_dimm(sysinfo, dimm, 3, 0xff, 15) && |
| 264 | test_dimm(sysinfo, dimm, 13, 0xff, 8))) |
| 265 | die("Chipset requires 13, 14 or 15 (with x8) row address bits"); |
| 266 | } |
| 267 | |
| 268 | /* For every detected DIMM, test if it's suitable for the chipset. */ |
| 269 | static void verify_ddr2(sysinfo_t *const sysinfo, int mask) |
| 270 | { |
| 271 | int cur; |
| 272 | for (cur = 0; mask; mask >>= 1, ++cur) { |
| 273 | if (mask & 1) |
| 274 | verify_ddr2_dimm(sysinfo, cur); |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | /* This function dies if dimm is unsuitable for the chipset. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 279 | static void verify_ddr3_dimm(sysinfo_t *const sysinfo, int dimm) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 280 | { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 281 | if (!test_dimm(sysinfo, dimm, 3, 15, 3)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 282 | die("Chipset only supports SO-DIMM\n"); |
| 283 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 284 | if (!test_dimm(sysinfo, dimm, 8, 0x18, 0)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 285 | die("Chipset doesn't support ECC RAM\n"); |
| 286 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 287 | if (!test_dimm(sysinfo, dimm, 7, 0x38, 0) && |
| 288 | !test_dimm(sysinfo, dimm, 7, 0x38, 8)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 289 | die("Chipset wants single or double sided DIMMs\n"); |
| 290 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 291 | if (!test_dimm(sysinfo, dimm, 7, 7, 1) && |
| 292 | !test_dimm(sysinfo, dimm, 7, 7, 2)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 293 | die("Chipset requires x8 or x16 width\n"); |
| 294 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 295 | if (!test_dimm(sysinfo, dimm, 4, 0x0f, 0) && |
| 296 | !test_dimm(sysinfo, dimm, 4, 0x0f, 1) && |
| 297 | !test_dimm(sysinfo, dimm, 4, 0x0f, 2) && |
| 298 | !test_dimm(sysinfo, dimm, 4, 0x0f, 3)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 299 | die("Chipset requires 256Mb, 512Mb, 1Gb or 2Gb chips."); |
| 300 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 301 | if (!test_dimm(sysinfo, dimm, 4, 0x70, 0)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 302 | die("Chipset requires 8 banks on DDR3\n"); |
| 303 | |
| 304 | /* How to check if burst length is 8? |
| 305 | Other values are not supported, are they even possible? */ |
| 306 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 307 | if (!test_dimm(sysinfo, dimm, 10, 0xff, 1)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 308 | die("Code assumes 1/8ns MTB\n"); |
| 309 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 310 | if (!test_dimm(sysinfo, dimm, 11, 0xff, 8)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 311 | die("Code assumes 1/8ns MTB\n"); |
| 312 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 313 | if (!test_dimm(sysinfo, dimm, 62, 0x9f, 0) && |
| 314 | !test_dimm(sysinfo, dimm, 62, 0x9f, 1) && |
| 315 | !test_dimm(sysinfo, dimm, 62, 0x9f, 2) && |
| 316 | !test_dimm(sysinfo, dimm, 62, 0x9f, 3) && |
| 317 | !test_dimm(sysinfo, dimm, 62, 0x9f, 5)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 318 | die("Only raw card types A, B, C, D and F are supported.\n"); |
| 319 | } |
| 320 | |
| 321 | /* For every detected DIMM, test if it's suitable for the chipset. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 322 | static void verify_ddr3(sysinfo_t *const sysinfo, int mask) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 323 | { |
| 324 | int cur = 0; |
| 325 | while (mask) { |
| 326 | if (mask & 1) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 327 | verify_ddr3_dimm(sysinfo, cur); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 328 | } |
| 329 | mask >>= 1; |
| 330 | cur++; |
| 331 | } |
| 332 | } |
| 333 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 334 | typedef struct { |
| 335 | int dimm_mask; |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 336 | struct spd_dimminfo { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 337 | unsigned int rows; |
| 338 | unsigned int cols; |
| 339 | unsigned int chip_capacity; |
| 340 | unsigned int banks; |
| 341 | unsigned int ranks; |
| 342 | unsigned int cas_latencies; |
| 343 | unsigned int tAAmin; |
| 344 | unsigned int tCKmin; |
| 345 | unsigned int width; |
| 346 | unsigned int tRAS; |
| 347 | unsigned int tRP; |
| 348 | unsigned int tRCD; |
| 349 | unsigned int tWR; |
| 350 | unsigned int page_size; |
| 351 | unsigned int raw_card; |
| 352 | } channel[2]; |
| 353 | } spdinfo_t; |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 354 | /** |
| 355 | * \brief Decode SPD tck cycle time |
| 356 | * |
| 357 | * Decodes a raw SPD data from a DDR2 DIMM. |
| 358 | * Returns cycle time in 1/256th ns. |
| 359 | */ |
| 360 | static unsigned int spd_decode_tck_time(u8 c) |
| 361 | { |
| 362 | u8 high, low; |
| 363 | |
| 364 | high = c >> 4; |
| 365 | |
| 366 | switch (c & 0xf) { |
| 367 | case 0xa: |
| 368 | low = 25; |
| 369 | break; |
| 370 | case 0xb: |
| 371 | low = 33; |
| 372 | break; |
| 373 | case 0xc: |
| 374 | low = 66; |
| 375 | break; |
| 376 | case 0xd: |
| 377 | low = 75; |
| 378 | break; |
| 379 | case 0xe: |
| 380 | case 0xf: |
| 381 | die("Invalid tck setting. lower nibble is 0x%x\n", c & 0xf); |
| 382 | default: |
| 383 | low = (c & 0xf) * 10; |
| 384 | } |
| 385 | |
| 386 | return ((high * 100 + low) << 8) / 100; |
| 387 | } |
| 388 | static void collect_ddr2_dimm(struct spd_dimminfo *const di, const int smb_addr) |
| 389 | { |
| 390 | static const int tCK_offsets[] = { 9, 23, 25 }; |
| 391 | |
| 392 | di->rows = smbus_read_byte(smb_addr, 3); |
| 393 | di->cols = smbus_read_byte(smb_addr, 4); |
| 394 | di->banks = smbus_read_byte(smb_addr, 17); |
| 395 | di->width = smbus_read_byte(smb_addr, 13) / 8; /* in bytes */ |
| 396 | |
| 397 | /* 0: 256Mb .. 3: 2Gb */ |
| 398 | di->chip_capacity = |
| 399 | di->rows + di->cols |
| 400 | + (di->width == 1 ? 3 : 4) /* 1B: 2^3 bits, 2B: 2^4 bits */ |
| 401 | + (di->banks == 4 ? 2 : 3) /* 4 banks: 2^2, 8 banks: 2^3 */ |
| 402 | - 28; |
| 403 | |
| 404 | di->page_size = di->width * (1 << di->cols); /* in bytes */ |
| 405 | |
| 406 | di->ranks = (smbus_read_byte(smb_addr, 5) & 7) + 1; |
| 407 | |
| 408 | di->cas_latencies = smbus_read_byte(smb_addr, 18); |
| 409 | /* assuming tCKmin for the highest CAS is the absolute minimum */ |
| 410 | di->tCKmin = spd_decode_tck_time(smbus_read_byte(smb_addr, 9)); |
| 411 | |
| 412 | /* try to reconstruct tAAmin from available data (I hate DDR2 SPDs) */ |
| 413 | unsigned int i; |
| 414 | unsigned int cas = 7; |
| 415 | di->tAAmin = UINT32_MAX; /* we don't have UINT_MAX? */ |
| 416 | for (i = 0; i < ARRAY_SIZE(tCK_offsets); ++i, --cas) { |
| 417 | for (; cas > 1; --cas) |
| 418 | if (di->cas_latencies & (1 << cas)) |
| 419 | break; |
| 420 | if (cas <= 1) |
| 421 | break; |
| 422 | |
| 423 | const unsigned int tCK_enc = |
| 424 | smbus_read_byte(smb_addr, tCK_offsets[i]); |
| 425 | const unsigned int tAA = spd_decode_tck_time(tCK_enc) * cas; |
| 426 | if (tAA < di->tAAmin) |
| 427 | di->tAAmin = tAA; |
| 428 | } |
| 429 | |
| 430 | /* convert to 1/256ns */ |
| 431 | di->tRAS = smbus_read_byte(smb_addr, 30) << 8; /* given in ns */ |
| 432 | di->tRP = smbus_read_byte(smb_addr, 27) << 6; /* given in 1/4ns */ |
| 433 | di->tRCD = smbus_read_byte(smb_addr, 29) << 6; /* given in 1/4ns */ |
| 434 | di->tWR = smbus_read_byte(smb_addr, 36) << 6; /* given in 1/4ns */ |
| 435 | |
| 436 | di->raw_card = 0; /* Use same path as for DDR3 type A. */ |
| 437 | } |
| 438 | /* |
| 439 | * This function collects RAM characteristics from SPD, assuming that RAM |
| 440 | * is generally within chipset's requirements, since verify_ddr2() passed. |
| 441 | */ |
| 442 | static void collect_ddr2(sysinfo_t *const sysinfo, spdinfo_t *const config) |
| 443 | { |
| 444 | int cur; |
| 445 | for (cur = 0; cur < 2; ++cur) { |
| 446 | if (config->dimm_mask & (1 << (2 * cur))) { |
| 447 | collect_ddr2_dimm(&config->channel[cur], |
| 448 | sysinfo->spd_map[2 * cur]); |
| 449 | } |
| 450 | } |
| 451 | } |
| 452 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 453 | /* |
| 454 | * This function collects RAM characteristics from SPD, assuming that RAM |
| 455 | * is generally within chipset's requirements, since verify_ddr3() passed. |
| 456 | */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 457 | static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 458 | { |
| 459 | int mask = config->dimm_mask; |
| 460 | int cur = 0; |
| 461 | while (mask != 0) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 462 | /* FIXME: support several dimms on same channel. */ |
| 463 | if ((mask & 1) && sysinfo->spd_map[2 * cur]) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 464 | int tmp; |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 465 | const int smb_addr = sysinfo->spd_map[2 * cur]; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 466 | |
| 467 | config->channel[cur].rows = ((smbus_read_byte(smb_addr, 5) >> 3) & 7) + 12; |
| 468 | config->channel[cur].cols = (smbus_read_byte(smb_addr, 5) & 7) + 9; |
| 469 | |
| 470 | config->channel[cur].chip_capacity = smbus_read_byte(smb_addr, 4) & 0xf; |
| 471 | |
| 472 | config->channel[cur].banks = 8; /* GM45 only accepts this for DDR3. |
| 473 | verify_ddr3() fails for other values. */ |
| 474 | config->channel[cur].ranks = ((smbus_read_byte(smb_addr, 7) >> 3) & 7) + 1; |
| 475 | |
| 476 | config->channel[cur].cas_latencies = |
| 477 | ((smbus_read_byte(smb_addr, 15) << 8) | smbus_read_byte(smb_addr, 14)) |
| 478 | << 4; /* so bit x is CAS x */ |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 479 | config->channel[cur].tAAmin = smbus_read_byte(smb_addr, 16) * 32; /* convert from MTB to 1/256 ns */ |
| 480 | config->channel[cur].tCKmin = smbus_read_byte(smb_addr, 12) * 32; /* convert from MTB to 1/256 ns */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 481 | |
| 482 | config->channel[cur].width = smbus_read_byte(smb_addr, 7) & 7; |
| 483 | config->channel[cur].page_size = config->channel[cur].width * |
| 484 | (1 << config->channel[cur].cols); /* in Bytes */ |
| 485 | |
| 486 | tmp = smbus_read_byte(smb_addr, 21); |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 487 | config->channel[cur].tRAS = (smbus_read_byte(smb_addr, 22) | ((tmp & 0xf) << 8)) * 32; |
| 488 | config->channel[cur].tRP = smbus_read_byte(smb_addr, 20) * 32; |
| 489 | config->channel[cur].tRCD = smbus_read_byte(smb_addr, 18) * 32; |
| 490 | config->channel[cur].tWR = smbus_read_byte(smb_addr, 17) * 32; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 491 | |
| 492 | config->channel[cur].raw_card = smbus_read_byte(smb_addr, 62) & 0x1f; |
| 493 | } |
| 494 | cur++; |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 495 | mask >>= 2; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 496 | } |
| 497 | } |
| 498 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 499 | static fsb_clock_t read_fsb_clock(void) |
| 500 | { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 501 | switch (mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 502 | case 6: |
| 503 | return FSB_CLOCK_1067MHz; |
| 504 | case 2: |
| 505 | return FSB_CLOCK_800MHz; |
| 506 | case 3: |
| 507 | return FSB_CLOCK_667MHz; |
| 508 | default: |
| 509 | die("Unsupported FSB clock.\n"); |
| 510 | } |
| 511 | } |
| 512 | static mem_clock_t clock_index(const unsigned int clock) |
| 513 | { |
| 514 | switch (clock) { |
| 515 | case 533: return MEM_CLOCK_533MHz; |
| 516 | case 400: return MEM_CLOCK_400MHz; |
| 517 | case 333: return MEM_CLOCK_333MHz; |
| 518 | default: die("Unknown clock value.\n"); |
| 519 | } |
| 520 | return -1; /* Won't be reached. */ |
| 521 | } |
| 522 | static void normalize_clock(unsigned int *const clock) |
| 523 | { |
| 524 | if (*clock >= 533) |
| 525 | *clock = 533; |
| 526 | else if (*clock >= 400) |
| 527 | *clock = 400; |
| 528 | else if (*clock >= 333) |
| 529 | *clock = 333; |
| 530 | else |
| 531 | *clock = 0; |
| 532 | } |
| 533 | static void lower_clock(unsigned int *const clock) |
| 534 | { |
| 535 | --*clock; |
| 536 | normalize_clock(clock); |
| 537 | } |
| 538 | static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo, |
| 539 | const spdinfo_t *const spdinfo) |
| 540 | { |
| 541 | /* various constraints must be fulfilled: |
| 542 | CAS * tCK < 20ns == 160MTB |
| 543 | tCK_max >= tCK >= tCK_min |
| 544 | CAS >= roundup(tAA_min/tCK) |
| 545 | CAS supported |
| 546 | Clock(MHz) = 1000 / tCK(ns) |
| 547 | Clock(MHz) = 8000 / tCK(MTB) |
| 548 | AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz |
| 549 | */ |
| 550 | int i; |
| 551 | |
| 552 | /* Calculate common cas_latencies mask, tCKmin and tAAmin. */ |
| 553 | unsigned int cas_latencies = (unsigned int)-1; |
| 554 | unsigned int tCKmin = 0, tAAmin = 0; |
| 555 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 556 | cas_latencies &= spdinfo->channel[i].cas_latencies; |
| 557 | if (spdinfo->channel[i].tCKmin > tCKmin) |
| 558 | tCKmin = spdinfo->channel[i].tCKmin; |
| 559 | if (spdinfo->channel[i].tAAmin > tAAmin) |
| 560 | tAAmin = spdinfo->channel[i].tAAmin; |
| 561 | } |
| 562 | |
| 563 | /* Get actual value of fsb clock. */ |
| 564 | sysinfo->selected_timings.fsb_clock = read_fsb_clock(); |
| 565 | unsigned int fsb_mhz = 0; |
| 566 | switch (sysinfo->selected_timings.fsb_clock) { |
| 567 | case FSB_CLOCK_1067MHz: fsb_mhz = 1067; break; |
| 568 | case FSB_CLOCK_800MHz: fsb_mhz = 800; break; |
| 569 | case FSB_CLOCK_667MHz: fsb_mhz = 667; break; |
| 570 | } |
| 571 | |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 572 | unsigned int clock = 256000 / tCKmin; |
| 573 | const unsigned int max_ddr_clock = (sysinfo->spd_type == DDR2) |
| 574 | ? sysinfo->max_ddr2_mt / 2 |
| 575 | : sysinfo->max_ddr3_mt / 2; |
| 576 | if ((clock > max_ddr_clock) || (clock > fsb_mhz / 2)) { |
| 577 | int new_clock = MIN(max_ddr_clock, fsb_mhz / 2); |
| 578 | printk(BIOS_INFO, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 579 | clock, new_clock); |
| 580 | clock = new_clock; |
| 581 | } |
| 582 | normalize_clock(&clock); |
| 583 | |
| 584 | /* Find compatible clock / CAS pair. */ |
| 585 | unsigned int tCKproposed; |
| 586 | unsigned int CAS; |
| 587 | while (1) { |
| 588 | if (!clock) |
| 589 | die("Couldn't find compatible clock / CAS settings.\n"); |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 590 | tCKproposed = 256000 / clock; |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 591 | CAS = DIV_ROUND_UP(tAAmin, tCKproposed); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 592 | printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", CAS, tCKproposed); |
| 593 | for (; CAS <= DDR3_MAX_CAS; ++CAS) |
| 594 | if (cas_latencies & (1 << CAS)) |
| 595 | break; |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 596 | if ((CAS <= DDR3_MAX_CAS) && (CAS * tCKproposed < 32 * 160)) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 597 | /* Found good CAS. */ |
| 598 | printk(BIOS_SPEW, "Found compatible clock / CAS pair: %u / %u.\n", clock, CAS); |
| 599 | break; |
| 600 | } |
| 601 | lower_clock(&clock); |
| 602 | } |
| 603 | sysinfo->selected_timings.CAS = CAS; |
| 604 | sysinfo->selected_timings.mem_clock = clock_index(clock); |
| 605 | |
| 606 | return tCKproposed; |
| 607 | } |
| 608 | |
| 609 | static void calculate_derived_timings(sysinfo_t *const sysinfo, |
| 610 | const unsigned int tCLK, |
| 611 | const spdinfo_t *const spdinfo) |
| 612 | { |
| 613 | int i; |
| 614 | |
| 615 | /* Calculate common tRASmin, tRPmin, tRCDmin and tWRmin. */ |
| 616 | unsigned int tRASmin = 0, tRPmin = 0, tRCDmin = 0, tWRmin = 0; |
| 617 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 618 | if (spdinfo->channel[i].tRAS > tRASmin) |
| 619 | tRASmin = spdinfo->channel[i].tRAS; |
| 620 | if (spdinfo->channel[i].tRP > tRPmin) |
| 621 | tRPmin = spdinfo->channel[i].tRP; |
| 622 | if (spdinfo->channel[i].tRCD > tRCDmin) |
| 623 | tRCDmin = spdinfo->channel[i].tRCD; |
| 624 | if (spdinfo->channel[i].tWR > tWRmin) |
| 625 | tWRmin = spdinfo->channel[i].tWR; |
| 626 | } |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 627 | tRASmin = DIV_ROUND_UP(tRASmin, tCLK); |
| 628 | tRPmin = DIV_ROUND_UP(tRPmin, tCLK); |
| 629 | tRCDmin = DIV_ROUND_UP(tRCDmin, tCLK); |
| 630 | tWRmin = DIV_ROUND_UP(tWRmin, tCLK); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 631 | |
| 632 | /* Lookup tRFC and calculate common tRFCmin. */ |
| 633 | const unsigned int tRFC_from_clock_and_cap[][4] = { |
| 634 | /* CAP_256M CAP_512M CAP_1G CAP_2G */ |
| 635 | /* 533MHz */ { 40, 56, 68, 104 }, |
| 636 | /* 400MHz */ { 30, 42, 51, 78 }, |
| 637 | /* 333MHz */ { 25, 35, 43, 65 }, |
| 638 | }; |
| 639 | unsigned int tRFCmin = 0; |
| 640 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 641 | const unsigned int tRFC = tRFC_from_clock_and_cap |
| 642 | [sysinfo->selected_timings.mem_clock][spdinfo->channel[i].chip_capacity]; |
| 643 | if (tRFC > tRFCmin) |
| 644 | tRFCmin = tRFC; |
| 645 | } |
| 646 | |
| 647 | /* Calculate common tRD from CAS and FSB and DRAM clocks. */ |
| 648 | unsigned int tRDmin = sysinfo->selected_timings.CAS; |
| 649 | switch (sysinfo->selected_timings.fsb_clock) { |
| 650 | case FSB_CLOCK_667MHz: |
| 651 | tRDmin += 1; |
| 652 | break; |
| 653 | case FSB_CLOCK_800MHz: |
| 654 | tRDmin += 2; |
| 655 | break; |
| 656 | case FSB_CLOCK_1067MHz: |
| 657 | tRDmin += 3; |
| 658 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) |
| 659 | tRDmin += 1; |
| 660 | break; |
| 661 | } |
| 662 | |
| 663 | /* Calculate common tRRDmin. */ |
| 664 | unsigned int tRRDmin = 0; |
| 665 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 666 | unsigned int tRRD = 2 + (spdinfo->channel[i].page_size / 1024); |
| 667 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) |
| 668 | tRRD += (spdinfo->channel[i].page_size / 1024); |
| 669 | if (tRRD > tRRDmin) |
| 670 | tRRDmin = tRRD; |
| 671 | } |
| 672 | |
| 673 | /* Lookup and calculate common tFAWmin. */ |
| 674 | unsigned int tFAW_from_pagesize_and_clock[][3] = { |
| 675 | /* 533MHz 400MHz 333MHz */ |
| 676 | /* 1K */ { 20, 15, 13 }, |
| 677 | /* 2K */ { 27, 20, 17 }, |
| 678 | }; |
| 679 | unsigned int tFAWmin = 0; |
| 680 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 681 | const unsigned int tFAW = tFAW_from_pagesize_and_clock |
| 682 | [spdinfo->channel[i].page_size / 1024 - 1] |
| 683 | [sysinfo->selected_timings.mem_clock]; |
| 684 | if (tFAW > tFAWmin) |
| 685 | tFAWmin = tFAW; |
| 686 | } |
| 687 | |
| 688 | /* Refresh rate is fixed. */ |
| 689 | unsigned int tWL; |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 690 | if (sysinfo->spd_type == DDR2) { |
| 691 | tWL = sysinfo->selected_timings.CAS - 1; |
| 692 | } else if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 693 | tWL = 6; |
| 694 | } else { |
| 695 | tWL = 5; |
| 696 | } |
| 697 | |
| 698 | printk(BIOS_SPEW, "Timing values:\n" |
| 699 | " tCLK: %3u\n" |
| 700 | " tRAS: %3u\n" |
| 701 | " tRP: %3u\n" |
| 702 | " tRCD: %3u\n" |
| 703 | " tRFC: %3u\n" |
| 704 | " tWR: %3u\n" |
| 705 | " tRD: %3u\n" |
| 706 | " tRRD: %3u\n" |
| 707 | " tFAW: %3u\n" |
| 708 | " tWL: %3u\n", |
| 709 | tCLK, tRASmin, tRPmin, tRCDmin, tRFCmin, tWRmin, tRDmin, tRRDmin, tFAWmin, tWL); |
| 710 | |
| 711 | sysinfo->selected_timings.tRAS = tRASmin; |
| 712 | sysinfo->selected_timings.tRP = tRPmin; |
| 713 | sysinfo->selected_timings.tRCD = tRCDmin; |
| 714 | sysinfo->selected_timings.tRFC = tRFCmin; |
| 715 | sysinfo->selected_timings.tWR = tWRmin; |
| 716 | sysinfo->selected_timings.tRD = tRDmin; |
| 717 | sysinfo->selected_timings.tRRD = tRRDmin; |
| 718 | sysinfo->selected_timings.tFAW = tFAWmin; |
| 719 | sysinfo->selected_timings.tWL = tWL; |
| 720 | } |
| 721 | |
| 722 | static void collect_dimm_config(sysinfo_t *const sysinfo) |
| 723 | { |
| 724 | int i; |
| 725 | spdinfo_t spdinfo; |
| 726 | |
| 727 | spdinfo.dimm_mask = 0; |
| 728 | sysinfo->spd_type = 0; |
| 729 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 730 | for (i = 0; i < 4; i++) |
| 731 | if (sysinfo->spd_map[i]) { |
| 732 | const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2); |
| 733 | printk (BIOS_DEBUG, "%x:%x:%x\n", |
| 734 | i, sysinfo->spd_map[i], |
| 735 | spd); |
| 736 | if ((spd == 7) || (spd == 8) || (spd == 0xb)) { |
| 737 | spdinfo.dimm_mask |= 1 << i; |
| 738 | if (sysinfo->spd_type && sysinfo->spd_type != spd) { |
| 739 | die("Multiple types of DIMM installed in the system, don't do that!\n"); |
| 740 | } |
| 741 | sysinfo->spd_type = spd; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 742 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 743 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 744 | if (spdinfo.dimm_mask == 0) { |
| 745 | die("Could not find any DIMM.\n"); |
| 746 | } |
| 747 | |
| 748 | /* Normalize spd_type to 1, 2, 3. */ |
| 749 | sysinfo->spd_type = (sysinfo->spd_type & 1) | ((sysinfo->spd_type & 8) >> 2); |
| 750 | printk(BIOS_SPEW, "DDR mask %x, DDR %d\n", spdinfo.dimm_mask, sysinfo->spd_type); |
| 751 | |
| 752 | if (sysinfo->spd_type == DDR2) { |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 753 | verify_ddr2(sysinfo, spdinfo.dimm_mask); |
| 754 | collect_ddr2(sysinfo, &spdinfo); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 755 | } else if (sysinfo->spd_type == DDR3) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 756 | verify_ddr3(sysinfo, spdinfo.dimm_mask); |
| 757 | collect_ddr3(sysinfo, &spdinfo); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 758 | } else { |
| 759 | die("Will never support DDR1.\n"); |
| 760 | } |
| 761 | |
| 762 | for (i = 0; i < 2; i++) { |
| 763 | if ((spdinfo.dimm_mask >> (i*2)) & 1) { |
| 764 | printk(BIOS_SPEW, "Bank %d populated:\n" |
| 765 | " Raw card type: %4c\n" |
| 766 | " Row addr bits: %4u\n" |
| 767 | " Col addr bits: %4u\n" |
| 768 | " byte width: %4u\n" |
| 769 | " page size: %4u\n" |
| 770 | " banks: %4u\n" |
| 771 | " ranks: %4u\n" |
| 772 | " tAAmin: %3u\n" |
| 773 | " tCKmin: %3u\n" |
| 774 | " Max clock: %3u MHz\n" |
| 775 | " CAS: 0x%04x\n", |
| 776 | i, spdinfo.channel[i].raw_card + 'A', |
| 777 | spdinfo.channel[i].rows, spdinfo.channel[i].cols, |
| 778 | spdinfo.channel[i].width, spdinfo.channel[i].page_size, |
| 779 | spdinfo.channel[i].banks, spdinfo.channel[i].ranks, |
| 780 | spdinfo.channel[i].tAAmin, spdinfo.channel[i].tCKmin, |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 781 | 256000 / spdinfo.channel[i].tCKmin, spdinfo.channel[i].cas_latencies); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 782 | } |
| 783 | } |
| 784 | |
| 785 | FOR_EACH_CHANNEL(i) { |
| 786 | sysinfo->dimms[i].card_type = |
| 787 | (spdinfo.dimm_mask & (1 << (i * 2))) ? spdinfo.channel[i].raw_card + 0xa : 0; |
| 788 | } |
| 789 | |
| 790 | /* Find common memory clock and CAS. */ |
| 791 | const unsigned int tCLK = find_common_clock_cas(sysinfo, &spdinfo); |
| 792 | |
| 793 | /* Calculate other timings from clock and CAS. */ |
| 794 | calculate_derived_timings(sysinfo, tCLK, &spdinfo); |
| 795 | |
| 796 | /* Initialize DIMM infos. */ |
| 797 | /* Always prefer interleaved over async channel mode. */ |
| 798 | FOR_EACH_CHANNEL(i) { |
| 799 | IF_CHANNEL_POPULATED(sysinfo->dimms, i) { |
| 800 | sysinfo->dimms[i].banks = spdinfo.channel[i].banks; |
| 801 | sysinfo->dimms[i].ranks = spdinfo.channel[i].ranks; |
| 802 | |
| 803 | /* .width is 1 for x8 or 2 for x16, bus width is 8 bytes. */ |
| 804 | const unsigned int chips_per_rank = 8 / spdinfo.channel[i].width; |
| 805 | |
| 806 | sysinfo->dimms[i].chip_width = spdinfo.channel[i].width; |
| 807 | sysinfo->dimms[i].chip_capacity = spdinfo.channel[i].chip_capacity; |
| 808 | sysinfo->dimms[i].page_size = spdinfo.channel[i].page_size * chips_per_rank; |
| 809 | sysinfo->dimms[i].rank_capacity_mb = |
| 810 | /* offset of chip_capacity is 8 (256M), therefore, add 8 |
| 811 | chip_capacity is in Mbit, we want MByte, therefore, subtract 3 */ |
| 812 | (1 << (spdinfo.channel[i].chip_capacity + 8 - 3)) * chips_per_rank; |
| 813 | } |
| 814 | } |
| 815 | if (CHANNEL_IS_POPULATED(sysinfo->dimms, 0) && |
| 816 | CHANNEL_IS_POPULATED(sysinfo->dimms, 1)) |
| 817 | sysinfo->selected_timings.channel_mode = CHANNEL_MODE_DUAL_INTERLEAVED; |
| 818 | else |
| 819 | sysinfo->selected_timings.channel_mode = CHANNEL_MODE_SINGLE; |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 820 | |
| 821 | if (sysinfo->spd_type == DDR2) |
| 822 | die("DDR2 support not complete yet\n"); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 823 | } |
| 824 | |
| 825 | static void reset_on_bad_warmboot(void) |
| 826 | { |
| 827 | /* Check self refresh channel status. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 828 | const u32 reg = mchbar_read32(PMSTS_MCHBAR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 829 | /* Clear status bits. R/WC */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 830 | mchbar_write32(PMSTS_MCHBAR, reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 831 | if ((reg & PMSTS_WARM_RESET) && !(reg & PMSTS_BOTH_SELFREFRESH)) { |
| 832 | printk(BIOS_INFO, "DRAM was not in self refresh " |
| 833 | "during warm boot, reset required.\n"); |
| 834 | gm45_early_reset(); |
| 835 | } |
| 836 | } |
| 837 | |
| 838 | static void set_system_memory_frequency(const timings_t *const timings) |
| 839 | { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 840 | mchbar_clrbits16(CLKCFG_MCHBAR + 0x60, 1 << 15); |
| 841 | mchbar_clrbits16(CLKCFG_MCHBAR + 0x48, 1 << 15); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 842 | |
| 843 | /* Calculate wanted frequency setting. */ |
| 844 | const int want_freq = 6 - timings->mem_clock; |
| 845 | |
| 846 | /* Read current memory frequency. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 847 | const u32 clkcfg = mchbar_read32(CLKCFG_MCHBAR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 848 | int cur_freq = (clkcfg & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT; |
| 849 | if (0 == cur_freq) { |
| 850 | /* Try memory frequency from scratchpad. */ |
| 851 | printk(BIOS_DEBUG, "Reading current memory frequency from scratchpad.\n"); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 852 | cur_freq = (mchbar_read16(SSKPD_MCHBAR) & SSKPD_CLK_MASK) >> SSKPD_CLK_SHIFT; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 853 | } |
| 854 | |
| 855 | if (cur_freq != want_freq) { |
| 856 | printk(BIOS_DEBUG, "Changing memory frequency: old %x, new %x.\n", cur_freq, want_freq); |
| 857 | /* When writing new frequency setting, reset, then set update bit. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 858 | mchbar_clrsetbits32(CLKCFG_MCHBAR, CLKCFG_UPDATE | CLKCFG_MEMCLK_MASK, |
| 859 | want_freq << CLKCFG_MEMCLK_SHIFT); |
| 860 | mchbar_clrsetbits32(CLKCFG_MCHBAR, CLKCFG_MEMCLK_MASK, |
| 861 | want_freq << CLKCFG_MEMCLK_SHIFT | CLKCFG_UPDATE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 862 | /* Reset update bit. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 863 | mchbar_clrbits32(CLKCFG_MCHBAR, CLKCFG_UPDATE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 864 | } |
| 865 | |
| 866 | if ((timings->fsb_clock == FSB_CLOCK_1067MHz) && (timings->mem_clock == MEM_CLOCK_667MT)) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 867 | mchbar_write32(CLKCFG_MCHBAR + 0x16, 0x000030f0); |
| 868 | mchbar_write32(CLKCFG_MCHBAR + 0x64, 0x000050c1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 869 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 870 | mchbar_clrsetbits32(CLKCFG_MCHBAR, 1 << 12, 1 << 17); |
| 871 | mchbar_setbits32(CLKCFG_MCHBAR, 1 << 17 | 1 << 12); |
| 872 | mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 12); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 873 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 874 | mchbar_write32(CLKCFG_MCHBAR + 0x04, 0x9bad1f1f); |
| 875 | mchbar_write8(CLKCFG_MCHBAR + 0x08, 0xf4); |
| 876 | mchbar_write8(CLKCFG_MCHBAR + 0x0a, 0x43); |
| 877 | mchbar_write8(CLKCFG_MCHBAR + 0x0c, 0x10); |
| 878 | mchbar_write8(CLKCFG_MCHBAR + 0x0d, 0x80); |
| 879 | mchbar_write32(CLKCFG_MCHBAR + 0x50, 0x0b0e151b); |
| 880 | mchbar_write8(CLKCFG_MCHBAR + 0x54, 0xb4); |
| 881 | mchbar_write8(CLKCFG_MCHBAR + 0x55, 0x10); |
| 882 | mchbar_write8(CLKCFG_MCHBAR + 0x56, 0x08); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 883 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 884 | mchbar_setbits32(CLKCFG_MCHBAR, 1 << 10); |
| 885 | mchbar_setbits32(CLKCFG_MCHBAR, 1 << 11); |
| 886 | mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 10); |
| 887 | mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 11); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 888 | } |
| 889 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 890 | mchbar_setbits32(CLKCFG_MCHBAR + 0x48, 0x3f << 24); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 891 | } |
| 892 | |
| 893 | int raminit_read_vco_index(void) |
| 894 | { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 895 | switch (mchbar_read8(HPLLVCO_MCHBAR) & 0x7) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 896 | case VCO_2666: |
| 897 | return 0; |
| 898 | case VCO_3200: |
| 899 | return 1; |
| 900 | case VCO_4000: |
| 901 | return 2; |
| 902 | case VCO_5333: |
| 903 | return 3; |
| 904 | default: |
| 905 | die("Unknown VCO frequency.\n"); |
| 906 | return 0; |
| 907 | } |
| 908 | } |
| 909 | static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo) |
| 910 | { |
| 911 | const int gfx_idx = ((sysinfo->gfx_type == GMCH_GS45) && |
| 912 | !sysinfo->gs45_low_power_mode) |
| 913 | ? (GMCH_GS45 + 1) : sysinfo->gfx_type; |
| 914 | |
| 915 | /* Render and sampler frequency values seem to be some kind of factor. */ |
| 916 | const u16 render_freq_from_vco_and_gfxtype[][10] = { |
| 917 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 918 | /* VCO 2666 */ { 0xd, 0xd, 0xe, 0xd, 0xb, 0xd, 0xb, 0xa, 0xd }, |
| 919 | /* VCO 3200 */ { 0xd, 0xe, 0xf, 0xd, 0xb, 0xd, 0xb, 0x9, 0xd }, |
| 920 | /* VCO 4000 */ { 0xc, 0xd, 0xf, 0xc, 0xa, 0xc, 0xa, 0x9, 0xc }, |
| 921 | /* VCO 5333 */ { 0xb, 0xc, 0xe, 0xb, 0x9, 0xb, 0x9, 0x8, 0xb }, |
| 922 | }; |
| 923 | const u16 sampler_freq_from_vco_and_gfxtype[][10] = { |
| 924 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 925 | /* VCO 2666 */ { 0xc, 0xc, 0xd, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, |
| 926 | /* VCO 3200 */ { 0xc, 0xd, 0xe, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, |
| 927 | /* VCO 4000 */ { 0xa, 0xc, 0xd, 0xa, 0x8, 0xa, 0x8, 0x8, 0xa }, |
| 928 | /* VCO 5333 */ { 0xa, 0xa, 0xc, 0xa, 0x7, 0xa, 0x7, 0x6, 0xa }, |
| 929 | }; |
| 930 | const u16 display_clock_select_from_gfxtype[] = { |
| 931 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 932 | 1, 1, 1, 1, 1, 1, 1, 0, 1 |
| 933 | }; |
| 934 | |
| 935 | if (pci_read_config16(GCFGC_PCIDEV, 0) != 0x8086) { |
| 936 | printk(BIOS_DEBUG, "Skipping IGD memory frequency setting.\n"); |
| 937 | return; |
| 938 | } |
| 939 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 940 | mchbar_write16(0x119e, 0xa800); |
| 941 | mchbar_clrsetbits16(0x11c0, 0xff << 8, 0x01 << 8); |
| 942 | mchbar_write16(0x119e, 0xb800); |
| 943 | mchbar_setbits8(0x0f10, 1 << 7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 944 | |
| 945 | /* Read VCO. */ |
| 946 | const int vco_idx = raminit_read_vco_index(); |
| 947 | printk(BIOS_DEBUG, "Setting IGD memory frequencies for VCO #%d.\n", vco_idx); |
| 948 | |
| 949 | const u32 freqcfg = |
| 950 | ((render_freq_from_vco_and_gfxtype[vco_idx][gfx_idx] |
| 951 | << GCFGC_CR_SHIFT) & GCFGC_CR_MASK) | |
| 952 | ((sampler_freq_from_vco_and_gfxtype[vco_idx][gfx_idx] |
| 953 | << GCFGC_CS_SHIFT) & GCFGC_CS_MASK); |
| 954 | |
| 955 | /* Set frequencies, clear update bit. */ |
| 956 | u32 gcfgc = pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET); |
| 957 | gcfgc &= ~(GCFGC_CS_MASK | GCFGC_UPDATE | GCFGC_CR_MASK); |
| 958 | gcfgc |= freqcfg; |
| 959 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); |
| 960 | |
| 961 | /* Set frequencies, set update bit. */ |
| 962 | gcfgc = pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET); |
| 963 | gcfgc &= ~(GCFGC_CS_MASK | GCFGC_CR_MASK); |
| 964 | gcfgc |= freqcfg | GCFGC_UPDATE; |
| 965 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); |
| 966 | |
| 967 | /* Clear update bit. */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 968 | pci_and_config16(GCFGC_PCIDEV, GCFGC_OFFSET, ~GCFGC_UPDATE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 969 | |
| 970 | /* Set display clock select bit. */ |
| 971 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, |
| 972 | (pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_CD_MASK) | |
| 973 | (display_clock_select_from_gfxtype[gfx_idx] << GCFGC_CD_SHIFT)); |
| 974 | } |
| 975 | |
| 976 | static void configure_dram_control_mode(const timings_t *const timings, const dimminfo_t *const dimms) |
| 977 | { |
| 978 | int ch, r; |
| 979 | |
| 980 | FOR_EACH_CHANNEL(ch) { |
| 981 | unsigned int mchbar = CxDRC0_MCHBAR(ch); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 982 | u32 cxdrc = mchbar_read32(mchbar); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 983 | cxdrc &= ~CxDRC0_RANKEN_MASK; |
| 984 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 985 | cxdrc |= CxDRC0_RANKEN(r); |
| 986 | cxdrc = (cxdrc & ~CxDRC0_RMS_MASK) | |
| 987 | /* Always 7.8us for DDR3: */ |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 988 | /* FIXME DDR2: SPD+12? */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 989 | CxDRC0_RMS_78US; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 990 | mchbar_write32(mchbar, cxdrc); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 991 | |
| 992 | mchbar = CxDRC1_MCHBAR(ch); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 993 | cxdrc = mchbar_read32(mchbar); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 994 | cxdrc |= CxDRC1_NOTPOP_MASK; |
| 995 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 996 | cxdrc &= ~CxDRC1_NOTPOP(r); |
| 997 | cxdrc |= CxDRC1_MUSTWR; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 998 | mchbar_write32(mchbar, cxdrc); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 999 | |
| 1000 | mchbar = CxDRC2_MCHBAR(ch); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1001 | cxdrc = mchbar_read32(mchbar); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1002 | cxdrc |= CxDRC2_NOTPOP_MASK; |
| 1003 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 1004 | cxdrc &= ~CxDRC2_NOTPOP(r); |
| 1005 | cxdrc |= CxDRC2_MUSTWR; |
| 1006 | if (timings->mem_clock == MEM_CLOCK_1067MT) |
| 1007 | cxdrc |= CxDRC2_CLK1067MT; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1008 | mchbar_write32(mchbar, cxdrc); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1009 | } |
| 1010 | } |
| 1011 | |
| 1012 | static void rcomp_initialization(const stepping_t stepping, const int sff) |
| 1013 | { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 1014 | /* Program RCOMP codes. */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1015 | if (sff) |
| 1016 | die("SFF platform unsupported in RCOMP initialization.\n"); |
| 1017 | /* Values are for DDR3. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1018 | mchbar_clrbits8(0x6ac, 0x0f); |
| 1019 | mchbar_write8(0x6b0, 0x55); |
| 1020 | mchbar_clrbits8(0x6ec, 0x0f); |
| 1021 | mchbar_write8(0x6f0, 0x66); |
| 1022 | mchbar_clrbits8(0x72c, 0x0f); |
| 1023 | mchbar_write8(0x730, 0x66); |
| 1024 | mchbar_clrbits8(0x76c, 0x0f); |
| 1025 | mchbar_write8(0x770, 0x66); |
| 1026 | mchbar_clrbits8(0x7ac, 0x0f); |
| 1027 | mchbar_write8(0x7b0, 0x66); |
| 1028 | mchbar_clrbits8(0x7ec, 0x0f); |
| 1029 | mchbar_write8(0x7f0, 0x66); |
| 1030 | mchbar_clrbits8(0x86c, 0x0f); |
| 1031 | mchbar_write8(0x870, 0x55); |
| 1032 | mchbar_clrbits8(0x8ac, 0x0f); |
| 1033 | mchbar_write8(0x8b0, 0x66); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1034 | /* ODT multiplier bits. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1035 | mchbar_clrsetbits32(0x04d0, 7 << 3 | 7 << 0, 2 << 3 | 2 << 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1036 | |
| 1037 | /* Perform RCOMP calibration for DDR3. */ |
| 1038 | raminit_rcomp_calibration(stepping); |
| 1039 | |
| 1040 | /* Run initial RCOMP. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1041 | mchbar_setbits32(0x418, 1 << 17); |
| 1042 | mchbar_clrbits32(0x40c, 1 << 23); |
| 1043 | mchbar_clrbits32(0x41c, 1 << 7 | 1 << 3); |
| 1044 | mchbar_setbits32(0x400, 1); |
| 1045 | while (mchbar_read32(0x400) & 1) {} |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1046 | |
| 1047 | /* Run second RCOMP. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1048 | mchbar_setbits32(0x40c, 1 << 19); |
| 1049 | mchbar_setbits32(0x400, 1); |
| 1050 | while (mchbar_read32(0x400) & 1) {} |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1051 | |
| 1052 | /* Cleanup and start periodic RCOMP. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1053 | mchbar_clrbits32(0x40c, 1 << 19); |
| 1054 | mchbar_setbits32(0x40c, 1 << 23); |
| 1055 | mchbar_clrbits32(0x418, 1 << 17); |
| 1056 | mchbar_setbits32(0x41c, 1 << 7 | 1 << 3); |
| 1057 | mchbar_setbits32(0x400, 1 << 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1058 | } |
| 1059 | |
| 1060 | static void dram_powerup(const int resume) |
| 1061 | { |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 1062 | udelay(200); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1063 | mchbar_clrsetbits32(CLKCFG_MCHBAR, 1 << 3, 3 << 21); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1064 | if (!resume) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1065 | mchbar_setbits32(0x1434, 1 << 10); |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 1066 | udelay(1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1067 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1068 | mchbar_setbits32(0x1434, 1 << 6); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1069 | if (!resume) { |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 1070 | udelay(1); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1071 | mchbar_setbits32(0x1434, 1 << 9); |
| 1072 | mchbar_clrbits32(0x1434, 1 << 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1073 | udelay(500); |
| 1074 | } |
| 1075 | } |
| 1076 | static void dram_program_timings(const timings_t *const timings) |
| 1077 | { |
| 1078 | /* Values are for DDR3. */ |
| 1079 | const int burst_length = 8; |
| 1080 | const int tWTR = 4, tRTP = 1; |
| 1081 | int i; |
| 1082 | |
| 1083 | FOR_EACH_CHANNEL(i) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1084 | u32 reg = mchbar_read32(CxDRT0_MCHBAR(i)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1085 | const int btb_wtp = timings->tWL + burst_length/2 + timings->tWR; |
| 1086 | const int btb_wtr = timings->tWL + burst_length/2 + tWTR; |
| 1087 | reg = (reg & ~(CxDRT0_BtB_WtP_MASK | CxDRT0_BtB_WtR_MASK)) | |
| 1088 | ((btb_wtp << CxDRT0_BtB_WtP_SHIFT) & CxDRT0_BtB_WtP_MASK) | |
| 1089 | ((btb_wtr << CxDRT0_BtB_WtR_SHIFT) & CxDRT0_BtB_WtR_MASK); |
| 1090 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 1091 | reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); |
| 1092 | reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); |
| 1093 | } else { |
| 1094 | reg = (reg & ~(0x7 << 15)) | ((10 - timings->CAS) << 15); |
| 1095 | reg = (reg & ~(0xf << 10)) | ((timings->CAS - 4) << 10); |
| 1096 | } |
| 1097 | reg = (reg & ~(0x7 << 5)) | (3 << 5); |
| 1098 | reg = (reg & ~(0x7 << 0)) | (1 << 0); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1099 | mchbar_write32(CxDRT0_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1100 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1101 | reg = mchbar_read32(CxDRT1_MCHBAR(i)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1102 | reg = (reg & ~(0x03 << 28)) | ((tRTP & 0x03) << 28); |
| 1103 | reg = (reg & ~(0x1f << 21)) | ((timings->tRAS & 0x1f) << 21); |
| 1104 | reg = (reg & ~(0x07 << 10)) | (((timings->tRRD - 2) & 0x07) << 10); |
| 1105 | reg = (reg & ~(0x07 << 5)) | (((timings->tRCD - 2) & 0x07) << 5); |
| 1106 | reg = (reg & ~(0x07 << 0)) | (((timings->tRP - 2) & 0x07) << 0); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1107 | mchbar_write32(CxDRT1_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1108 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1109 | reg = mchbar_read32(CxDRT2_MCHBAR(i)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1110 | reg = (reg & ~(0x1f << 17)) | ((timings->tFAW & 0x1f) << 17); |
| 1111 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 1112 | reg = (reg & ~(0x7 << 12)) | (0x2 << 12); |
| 1113 | reg = (reg & ~(0xf << 6)) | (0x9 << 6); |
| 1114 | } else { |
| 1115 | reg = (reg & ~(0x7 << 12)) | (0x3 << 12); |
| 1116 | reg = (reg & ~(0xf << 6)) | (0xc << 6); |
| 1117 | } |
| 1118 | reg = (reg & ~(0x1f << 0)) | (0x13 << 0); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1119 | mchbar_write32(CxDRT2_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1120 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1121 | reg = mchbar_read32(CxDRT3_MCHBAR(i)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1122 | reg |= 0x3 << 28; |
| 1123 | reg = (reg & ~(0x03 << 26)); |
| 1124 | reg = (reg & ~(0x07 << 23)) | (((timings->CAS - 3) & 0x07) << 23); |
| 1125 | reg = (reg & ~(0xff << 13)) | ((timings->tRFC & 0xff) << 13); |
| 1126 | reg = (reg & ~(0x07 << 0)) | (((timings->tWL - 2) & 0x07) << 0); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1127 | mchbar_write32(CxDRT3_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1128 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1129 | reg = mchbar_read32(CxDRT4_MCHBAR(i)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1130 | static const u8 timings_by_clock[4][3] = { |
| 1131 | /* 333MHz 400MHz 533MHz |
| 1132 | 667MT 800MT 1067MT */ |
| 1133 | { 0x07, 0x0a, 0x0d }, |
| 1134 | { 0x3a, 0x46, 0x5d }, |
| 1135 | { 0x0c, 0x0e, 0x18 }, |
| 1136 | { 0x21, 0x28, 0x35 }, |
| 1137 | }; |
| 1138 | const int clk_idx = 2 - timings->mem_clock; |
| 1139 | reg = (reg & ~(0x01f << 27)) | (timings_by_clock[0][clk_idx] << 27); |
| 1140 | reg = (reg & ~(0x3ff << 17)) | (timings_by_clock[1][clk_idx] << 17); |
| 1141 | reg = (reg & ~(0x03f << 10)) | (timings_by_clock[2][clk_idx] << 10); |
| 1142 | reg = (reg & ~(0x1ff << 0)) | (timings_by_clock[3][clk_idx] << 0); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1143 | mchbar_write32(CxDRT4_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1144 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1145 | reg = mchbar_read32(CxDRT5_MCHBAR(i)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1146 | if (timings->mem_clock == MEM_CLOCK_1067MT) |
| 1147 | reg = (reg & ~(0xf << 28)) | (0x8 << 28); |
| 1148 | reg = (reg & ~(0x00f << 22)) | ((burst_length/2 + timings->CAS + 2) << 22); |
| 1149 | reg = (reg & ~(0x3ff << 12)) | (0x190 << 12); |
| 1150 | reg = (reg & ~(0x00f << 4)) | ((timings->CAS - 2) << 4); |
| 1151 | reg = (reg & ~(0x003 << 2)) | (0x001 << 2); |
| 1152 | reg = (reg & ~(0x003 << 0)); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1153 | mchbar_write32(CxDRT5_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1154 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1155 | reg = mchbar_read32(CxDRT6_MCHBAR(i)); |
Nico Huber | 0c314f9 | 2019-08-11 13:56:30 +0200 | [diff] [blame] | 1156 | /* FIXME DDR2: SPD+12? */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1157 | reg = (reg & ~(0xffff << 16)) | (0x066a << 16); /* always 7.8us refresh rate for DDR3 */ |
| 1158 | reg |= (1 << 2); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1159 | mchbar_write32(CxDRT6_MCHBAR(i), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | static void dram_program_banks(const dimminfo_t *const dimms) |
| 1164 | { |
| 1165 | int ch, r; |
| 1166 | |
| 1167 | FOR_EACH_CHANNEL(ch) { |
| 1168 | const int tRPALL = dimms[ch].banks == 8; |
| 1169 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1170 | u32 reg = mchbar_read32(CxDRT1_MCHBAR(ch)) & ~(0x01 << 15); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1171 | IF_CHANNEL_POPULATED(dimms, ch) |
| 1172 | reg |= tRPALL << 15; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1173 | mchbar_write32(CxDRT1_MCHBAR(ch), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1174 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1175 | reg = mchbar_read32(CxDRA_MCHBAR(ch)) & ~CxDRA_BANKS_MASK; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1176 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { |
| 1177 | reg |= CxDRA_BANKS(r, dimms[ch].banks); |
| 1178 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1179 | mchbar_write32(CxDRA_MCHBAR(ch), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1180 | } |
| 1181 | } |
| 1182 | |
| 1183 | static void odt_setup(const timings_t *const timings, const int sff) |
| 1184 | { |
| 1185 | /* Values are for DDR3. */ |
| 1186 | int ch; |
| 1187 | |
| 1188 | FOR_EACH_CHANNEL(ch) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1189 | u32 reg = mchbar_read32(CxODT_HIGH(ch)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1190 | if (sff && (timings->mem_clock != MEM_CLOCK_1067MT)) |
| 1191 | reg &= ~(0x3 << (61 - 32)); |
| 1192 | else |
| 1193 | reg |= 0x3 << (61 - 32); |
| 1194 | reg = (reg & ~(0x3 << (52 - 32))) | (0x2 << (52 - 32)); |
| 1195 | reg = (reg & ~(0x7 << (48 - 32))) | ((timings->CAS - 3) << (48 - 32)); |
| 1196 | reg = (reg & ~(0xf << (44 - 32))) | (0x7 << (44 - 32)); |
| 1197 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 1198 | reg = (reg & ~(0xf << (40 - 32))) | ((12 - timings->CAS) << (40 - 32)); |
| 1199 | reg = (reg & ~(0xf << (36 - 32))) | (( 2 + timings->CAS) << (36 - 32)); |
| 1200 | } else { |
| 1201 | reg = (reg & ~(0xf << (40 - 32))) | ((13 - timings->CAS) << (40 - 32)); |
| 1202 | reg = (reg & ~(0xf << (36 - 32))) | (( 1 + timings->CAS) << (36 - 32)); |
| 1203 | } |
| 1204 | reg = (reg & ~(0xf << (32 - 32))) | (0x7 << (32 - 32)); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1205 | mchbar_write32(CxODT_HIGH(ch), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1206 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1207 | reg = mchbar_read32(CxODT_LOW(ch)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1208 | reg = (reg & ~(0x7 << 28)) | (0x2 << 28); |
| 1209 | reg = (reg & ~(0x3 << 22)) | (0x2 << 22); |
| 1210 | reg = (reg & ~(0x7 << 12)) | (0x2 << 12); |
| 1211 | reg = (reg & ~(0x7 << 4)) | (0x2 << 4); |
| 1212 | switch (timings->mem_clock) { |
| 1213 | case MEM_CLOCK_667MT: |
| 1214 | reg = (reg & ~0x7); |
| 1215 | break; |
| 1216 | case MEM_CLOCK_800MT: |
| 1217 | reg = (reg & ~0x7) | 0x2; |
| 1218 | break; |
| 1219 | case MEM_CLOCK_1067MT: |
| 1220 | reg = (reg & ~0x7) | 0x5; |
| 1221 | break; |
| 1222 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1223 | mchbar_write32(CxODT_LOW(ch), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | static void misc_settings(const timings_t *const timings, |
| 1228 | const stepping_t stepping) |
| 1229 | { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1230 | mchbar_clrsetbits32(0x1260, 1 << 24 | 0x1f, timings->tRD); |
| 1231 | mchbar_clrsetbits32(0x1360, 1 << 24 | 0x1f, timings->tRD); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1232 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1233 | mchbar_clrsetbits8(0x1268, 0xf, timings->tWL); |
| 1234 | mchbar_clrsetbits8(0x1368, 0xf, timings->tWL); |
| 1235 | mchbar_clrsetbits8(0x12a0, 0xf, 0xa); |
| 1236 | mchbar_clrsetbits8(0x13a0, 0xf, 0xa); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1237 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1238 | mchbar_clrsetbits32(0x218, 7 << 29 | 7 << 25 | 3 << 22 | 3 << 10, |
| 1239 | 4 << 29 | 3 << 25 | 0 << 22 | 1 << 10); |
| 1240 | mchbar_clrsetbits32(0x220, 7 << 16, 1 << 21 | 1 << 16); |
| 1241 | mchbar_clrsetbits32(0x224, 7 << 8, 3 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1242 | if (stepping >= STEPPING_B1) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1243 | mchbar_setbits8(0x234, 1 << 3); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1244 | } |
| 1245 | |
| 1246 | static void clock_crossing_setup(const fsb_clock_t fsb, |
| 1247 | const mem_clock_t ddr3clock, |
| 1248 | const dimminfo_t *const dimms) |
| 1249 | { |
| 1250 | int ch; |
| 1251 | |
| 1252 | static const u32 values_from_fsb_and_mem[][3][4] = { |
| 1253 | /* FSB 1067MHz */{ |
| 1254 | /* DDR3-1067 */ { 0x00000000, 0x00000000, 0x00180006, 0x00810060 }, |
| 1255 | /* DDR3-800 */ { 0x00000000, 0x00000000, 0x0000001c, 0x000300e0 }, |
| 1256 | /* DDR3-667 */ { 0x00000000, 0x00001c00, 0x03c00038, 0x0007e000 }, |
| 1257 | }, |
| 1258 | /* FSB 800MHz */{ |
| 1259 | /* DDR3-1067 */ { 0, 0, 0, 0 }, |
| 1260 | /* DDR3-800 */ { 0x00000000, 0x00000000, 0x0030000c, 0x000300c0 }, |
| 1261 | /* DDR3-667 */ { 0x00000000, 0x00000380, 0x0060001c, 0x00030c00 }, |
| 1262 | }, |
| 1263 | /* FSB 667MHz */{ |
| 1264 | /* DDR3-1067 */ { 0, 0, 0, 0 }, |
| 1265 | /* DDR3-800 */ { 0, 0, 0, 0 }, |
| 1266 | /* DDR3-667 */ { 0x00000000, 0x00000000, 0x0030000c, 0x000300c0 }, |
| 1267 | }, |
| 1268 | }; |
| 1269 | |
| 1270 | const u32 *data = values_from_fsb_and_mem[fsb][ddr3clock]; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1271 | mchbar_write32(0x0208, data[3]); |
| 1272 | mchbar_write32(0x020c, data[2]); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1273 | if (((fsb == FSB_CLOCK_1067MHz) || (fsb == FSB_CLOCK_800MHz)) && (ddr3clock == MEM_CLOCK_667MT)) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1274 | mchbar_write32(0x0210, data[1]); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1275 | |
| 1276 | static const u32 from_fsb_and_mem[][3] = { |
| 1277 | /* DDR3-1067 DDR3-800 DDR3-667 */ |
| 1278 | /* FSB 1067MHz */{ 0x40100401, 0x10040220, 0x08040110, }, |
| 1279 | /* FSB 800MHz */{ 0x00000000, 0x40100401, 0x00080201, }, |
| 1280 | /* FSB 667MHz */{ 0x00000000, 0x00000000, 0x40100401, }, |
| 1281 | }; |
| 1282 | FOR_EACH_CHANNEL(ch) { |
| 1283 | const unsigned int mchbar = 0x1258 + (ch * 0x0100); |
| 1284 | if ((fsb == FSB_CLOCK_1067MHz) && (ddr3clock == MEM_CLOCK_800MT) && CHANNEL_IS_CARDF(dimms, ch)) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1285 | mchbar_write32(mchbar, 0x08040120); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1286 | else |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1287 | mchbar_write32(mchbar, from_fsb_and_mem[fsb][ddr3clock]); |
| 1288 | mchbar_write32(mchbar + 4, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1289 | } |
| 1290 | } |
| 1291 | |
Angel Pons | 3e33be2 | 2020-09-16 12:50:59 +0200 | [diff] [blame] | 1292 | /* Program egress VC1 isoch timings. */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1293 | static void vc1_program_timings(const fsb_clock_t fsb) |
| 1294 | { |
| 1295 | const u32 timings_by_fsb[][2] = { |
| 1296 | /* FSB 1067MHz */ { 0x1a, 0x01380138 }, |
| 1297 | /* FSB 800MHz */ { 0x14, 0x00f000f0 }, |
| 1298 | /* FSB 667MHz */ { 0x10, 0x00c000c0 }, |
| 1299 | }; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1300 | epbar_write8(EPVC1ITC, timings_by_fsb[fsb][0]); |
| 1301 | epbar_write32(EPVC1IST + 0, timings_by_fsb[fsb][1]); |
| 1302 | epbar_write32(EPVC1IST + 4, timings_by_fsb[fsb][1]); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1303 | } |
| 1304 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1305 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 1306 | #define HOST_BRIDGE PCI_DEVFN(0, 0) |
| 1307 | |
| 1308 | static unsigned int get_mmio_size(void) |
| 1309 | { |
| 1310 | const struct device *dev; |
| 1311 | const struct northbridge_intel_gm45_config *cfg = NULL; |
| 1312 | |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 1313 | dev = pcidev_path_on_root(HOST_BRIDGE); |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1314 | if (dev) |
| 1315 | cfg = dev->chip_info; |
| 1316 | |
| 1317 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 1318 | if (!cfg || cfg->pci_mmio_size == 0) |
| 1319 | return DEFAULT_PCI_MMIO_SIZE; |
| 1320 | else |
| 1321 | return cfg->pci_mmio_size; |
| 1322 | } |
| 1323 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1324 | /* @prejedec if not zero, set rank size to 128MB and page size to 4KB. */ |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1325 | static void program_memory_map(const dimminfo_t *const dimms, const channel_mode_t mode, const int prejedec, u16 ggc) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1326 | { |
| 1327 | int ch, r; |
| 1328 | |
| 1329 | /* Program rank boundaries (CxDRBy). */ |
| 1330 | unsigned int base = 0; /* start of next rank in MB */ |
| 1331 | unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ |
| 1332 | FOR_EACH_CHANNEL(ch) { |
| 1333 | if (mode == CHANNEL_MODE_DUAL_INTERLEAVED) |
| 1334 | /* In interleaved mode, start every channel from 0. */ |
| 1335 | base = 0; |
| 1336 | for (r = 0; r < RANKS_PER_CHANNEL; r += 2) { |
| 1337 | /* Fixed capacity for pre-jedec config. */ |
| 1338 | const unsigned int rank_capacity_mb = |
| 1339 | prejedec ? 128 : dimms[ch].rank_capacity_mb; |
| 1340 | u32 reg = 0; |
| 1341 | |
| 1342 | /* Program bounds in CxDRBy. */ |
| 1343 | IF_RANK_POPULATED(dimms, ch, r) { |
| 1344 | base += rank_capacity_mb; |
| 1345 | total_mb[ch] += rank_capacity_mb; |
| 1346 | } |
| 1347 | reg |= CxDRBy_BOUND_MB(r, base); |
| 1348 | IF_RANK_POPULATED(dimms, ch, r+1) { |
| 1349 | base += rank_capacity_mb; |
| 1350 | total_mb[ch] += rank_capacity_mb; |
| 1351 | } |
| 1352 | reg |= CxDRBy_BOUND_MB(r+1, base); |
| 1353 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1354 | mchbar_write32(CxDRBy_MCHBAR(ch, r), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1355 | } |
| 1356 | } |
| 1357 | |
| 1358 | /* Program page size (CxDRA). */ |
| 1359 | FOR_EACH_CHANNEL(ch) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1360 | u32 reg = mchbar_read32(CxDRA_MCHBAR(ch)) & ~CxDRA_PAGESIZE_MASK; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1361 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { |
| 1362 | /* Fixed page size for pre-jedec config. */ |
| 1363 | const unsigned int page_size = /* dimm page size in bytes */ |
| 1364 | prejedec ? 4096 : dimms[ch].page_size; |
| 1365 | reg |= CxDRA_PAGESIZE(r, log2(page_size)); |
| 1366 | /* deferred to f5_27: reg |= CxDRA_BANKS(r, dimms[ch].banks); */ |
| 1367 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1368 | mchbar_write32(CxDRA_MCHBAR(ch), reg); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1369 | } |
| 1370 | |
| 1371 | /* Calculate memory mapping, all values in MB. */ |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1372 | |
| 1373 | u32 uma_sizem = 0; |
| 1374 | if (!prejedec) { |
| 1375 | if (!(ggc & 2)) { |
| 1376 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 1377 | |
| 1378 | /* Graphics memory */ |
| 1379 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 1380 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 1381 | |
| 1382 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 1383 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 1384 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 1385 | |
| 1386 | uma_sizem = (gms_sizek + gsm_sizek) >> 10; |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1387 | } |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1388 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 1389 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 1390 | pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1391 | uma_sizem += 2; |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1392 | } |
| 1393 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1394 | const unsigned int mmio_size = get_mmio_size(); |
| 1395 | const unsigned int MMIOstart = 4096 - mmio_size + uma_sizem; |
Vladimir Serbinenko | 9907be4 | 2014-08-12 21:51:28 +0200 | [diff] [blame] | 1396 | const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; |
| 1397 | const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1398 | const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE; |
| 1399 | const unsigned int claimCapable = |
| 1400 | !(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0 + 4) & (1 << (47 - 32))); |
| 1401 | |
| 1402 | const unsigned int TOM = total_mb[0] + total_mb[1]; |
| 1403 | unsigned int TOMminusME = TOM - usedMEsize; |
| 1404 | unsigned int TOLUD = (TOMminusME < MMIOstart) ? TOMminusME : MMIOstart; |
| 1405 | unsigned int TOUUD = TOMminusME; |
| 1406 | unsigned int REMAPbase = 0xffff, REMAPlimit = 0; |
| 1407 | |
| 1408 | if (claimCapable && (TOMminusME >= (MMIOstart + 64))) { |
| 1409 | /* 64MB alignment: We'll lose some MBs here, if ME is on. */ |
| 1410 | TOMminusME &= ~(64 - 1); |
| 1411 | /* 64MB alignment: Loss will be reclaimed. */ |
| 1412 | TOLUD &= ~(64 - 1); |
| 1413 | if (TOMminusME > 4096) { |
| 1414 | REMAPbase = TOMminusME; |
| 1415 | REMAPlimit = REMAPbase + (4096 - TOLUD); |
| 1416 | } else { |
| 1417 | REMAPbase = 4096; |
| 1418 | REMAPlimit = REMAPbase + (TOMminusME - TOLUD); |
| 1419 | } |
| 1420 | TOUUD = REMAPlimit; |
| 1421 | /* REMAPlimit is an inclusive bound, all others exclusive. */ |
| 1422 | REMAPlimit -= 64; |
| 1423 | } |
| 1424 | |
| 1425 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, (TOM >> 7) & 0x1ff); |
| 1426 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, TOLUD << 4); |
| 1427 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, TOUUD); |
| 1428 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); |
| 1429 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff); |
| 1430 | |
| 1431 | /* Program channel mode. */ |
| 1432 | switch (mode) { |
| 1433 | case CHANNEL_MODE_SINGLE: |
| 1434 | printk(BIOS_DEBUG, "Memory configured in single-channel mode.\n"); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1435 | mchbar_clrbits32(DCC_MCHBAR, DCC_INTERLEAVED); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1436 | break; |
| 1437 | case CHANNEL_MODE_DUAL_ASYNC: |
Elyes HAOUAS | c9a717d | 2020-02-16 09:52:09 +0100 | [diff] [blame] | 1438 | printk(BIOS_DEBUG, "Memory configured in dual-channel asymmetric mode.\n"); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1439 | mchbar_clrbits32(DCC_MCHBAR, DCC_INTERLEAVED); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1440 | break; |
| 1441 | case CHANNEL_MODE_DUAL_INTERLEAVED: |
| 1442 | printk(BIOS_DEBUG, "Memory configured in dual-channel interleaved mode.\n"); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1443 | mchbar_clrbits32(DCC_MCHBAR, DCC_NO_CHANXOR | 1 << 9); |
| 1444 | mchbar_setbits32(DCC_MCHBAR, DCC_INTERLEAVED); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1445 | break; |
| 1446 | } |
| 1447 | |
| 1448 | printk(BIOS_SPEW, "Memory map:\n" |
| 1449 | "TOM = %5uMB\n" |
| 1450 | "TOLUD = %5uMB\n" |
| 1451 | "TOUUD = %5uMB\n" |
| 1452 | "REMAP:\t base = %5uMB\n" |
Vladimir Serbinenko | 9907be4 | 2014-08-12 21:51:28 +0200 | [diff] [blame] | 1453 | "\t limit = %5uMB\n" |
| 1454 | "usedMEsize: %dMB\n", |
| 1455 | TOM, TOLUD, TOUUD, REMAPbase, REMAPlimit, usedMEsize); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1456 | } |
| 1457 | static void prejedec_memory_map(const dimminfo_t *const dimms, channel_mode_t mode) |
| 1458 | { |
| 1459 | /* Never use dual-interleaved mode in pre-jedec config. */ |
| 1460 | if (CHANNEL_MODE_DUAL_INTERLEAVED == mode) |
| 1461 | mode = CHANNEL_MODE_DUAL_ASYNC; |
| 1462 | |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1463 | program_memory_map(dimms, mode, 1, 0); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1464 | mchbar_setbits32(DCC_MCHBAR, DCC_NO_CHANXOR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1465 | } |
| 1466 | |
| 1467 | static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, |
| 1468 | const dimminfo_t *const dimms, |
| 1469 | const stepping_t stepping) |
| 1470 | { |
| 1471 | const int clk1067 = (ddr3clock == MEM_CLOCK_1067MT); |
| 1472 | const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; |
| 1473 | |
| 1474 | int ch; |
| 1475 | |
| 1476 | if (stepping < STEPPING_B1) |
| 1477 | die("Stepping <B1 unsupported in clock-multiplexer selection.\n"); |
| 1478 | |
| 1479 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1480 | int mixed = 0; |
| 1481 | if ((1 == ch) && (!CHANNEL_IS_POPULATED(dimms, 0) || (cardF[0] != cardF[1]))) |
| 1482 | mixed = 4 << 11; |
| 1483 | const unsigned int b = 0x14b0 + (ch * 0x0100); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1484 | mchbar_write32(b + 0x1c, (mchbar_read32(b + 0x1c) & ~(7 << 11)) | |
| 1485 | ((( cardF[ch])?1:0) << 11) | mixed); |
| 1486 | mchbar_write32(b + 0x18, (mchbar_read32(b + 0x18) & ~(7 << 11)) | mixed); |
| 1487 | mchbar_write32(b + 0x14, (mchbar_read32(b + 0x14) & ~(7 << 11)) | |
| 1488 | (((!clk1067 && !cardF[ch])?0:1) << 11) | mixed); |
| 1489 | mchbar_write32(b + 0x10, (mchbar_read32(b + 0x10) & ~(7 << 11)) | |
| 1490 | ((( clk1067 && !cardF[ch])?1:0) << 11) | mixed); |
| 1491 | mchbar_write32(b + 0x0c, (mchbar_read32(b + 0x0c) & ~(7 << 11)) | |
| 1492 | ((( cardF[ch])?3:2) << 11) | mixed); |
| 1493 | mchbar_write32(b + 0x08, (mchbar_read32(b + 0x08) & ~(7 << 11)) | |
| 1494 | (2 << 11) | mixed); |
| 1495 | mchbar_write32(b + 0x04, (mchbar_read32(b + 0x04) & ~(7 << 11)) | |
| 1496 | (((!clk1067 && !cardF[ch])?2:3) << 11) | mixed); |
| 1497 | mchbar_write32(b + 0x00, (mchbar_read32(b + 0x00) & ~(7 << 11)) | |
| 1498 | ((( clk1067 && !cardF[ch])?3:2) << 11) | mixed); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1499 | } |
| 1500 | } |
Nico Huber | d131183 | 2019-08-11 17:48:44 +0200 | [diff] [blame^] | 1501 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1502 | static void ddr3_write_io_init(const mem_clock_t ddr3clock, |
| 1503 | const dimminfo_t *const dimms, |
| 1504 | const stepping_t stepping, |
| 1505 | const int sff) |
| 1506 | { |
| 1507 | const int a1step = stepping >= STEPPING_CONVERSION_A1; |
| 1508 | const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; |
| 1509 | |
| 1510 | int ch; |
| 1511 | |
| 1512 | if (stepping < STEPPING_B1) |
| 1513 | die("Stepping <B1 unsupported in write i/o initialization.\n"); |
| 1514 | if (sff) |
| 1515 | die("SFF platform unsupported in write i/o initialization.\n"); |
| 1516 | |
| 1517 | static const u32 ddr3_667_800_by_stepping_ddr3_and_card[][2][2][4] = { |
| 1518 | { /* Stepping B3 and below */ |
| 1519 | { /* 667 MHz */ |
| 1520 | { 0xa3255008, 0x26888209, 0x26288208, 0x6188040f }, |
| 1521 | { 0x7524240b, 0xa5255608, 0x232b8508, 0x5528040f }, |
| 1522 | }, |
| 1523 | { /* 800 MHz */ |
| 1524 | { 0xa6255308, 0x26888209, 0x212b7508, 0x6188040f }, |
| 1525 | { 0x7524240b, 0xa6255708, 0x132b7508, 0x5528040f }, |
| 1526 | }, |
| 1527 | }, |
| 1528 | { /* Conversion stepping A1 and above */ |
| 1529 | { /* 667 MHz */ |
| 1530 | { 0xc5257208, 0x26888209, 0x26288208, 0x6188040f }, |
| 1531 | { 0x7524240b, 0xc5257608, 0x232b8508, 0x5528040f }, |
| 1532 | }, |
| 1533 | { /* 800 MHz */ |
| 1534 | { 0xb6256308, 0x26888209, 0x212b7508, 0x6188040f }, |
| 1535 | { 0x7524240b, 0xb6256708, 0x132b7508, 0x5528040f }, |
| 1536 | } |
| 1537 | }}; |
| 1538 | |
| 1539 | static const u32 ddr3_1067_by_channel_and_card[][2][4] = { |
| 1540 | { /* Channel A */ |
| 1541 | { 0xb2254708, 0x002b7408, 0x132b8008, 0x7228060f }, |
| 1542 | { 0xb0255008, 0xa4254108, 0x4528b409, 0x9428230f }, |
| 1543 | }, |
| 1544 | { /* Channel B */ |
| 1545 | { 0xa4254208, 0x022b6108, 0x132b8208, 0x9228210f }, |
| 1546 | { 0x6024140b, 0x92244408, 0x252ba409, 0x9328360c }, |
| 1547 | }, |
| 1548 | }; |
| 1549 | |
| 1550 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1551 | if ((1 == ch) && CHANNEL_IS_POPULATED(dimms, 0) && (cardF[0] == cardF[1])) |
| 1552 | /* Only write if second channel population differs. */ |
| 1553 | continue; |
| 1554 | const u32 *const data = (ddr3clock != MEM_CLOCK_1067MT) |
| 1555 | ? ddr3_667_800_by_stepping_ddr3_and_card[a1step][2 - ddr3clock][cardF[ch]] |
| 1556 | : ddr3_1067_by_channel_and_card[ch][cardF[ch]]; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1557 | mchbar_write32(CxWRTy_MCHBAR(ch, 0), data[0]); |
| 1558 | mchbar_write32(CxWRTy_MCHBAR(ch, 1), data[1]); |
| 1559 | mchbar_write32(CxWRTy_MCHBAR(ch, 2), data[2]); |
| 1560 | mchbar_write32(CxWRTy_MCHBAR(ch, 3), data[3]); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1561 | } |
| 1562 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1563 | mchbar_write32(0x1490, 0x00e70067); |
| 1564 | mchbar_write32(0x1494, 0x000d8000); |
| 1565 | mchbar_write32(0x1590, 0x00e70067); |
| 1566 | mchbar_write32(0x1594, 0x000d8000); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1567 | } |
Nico Huber | d131183 | 2019-08-11 17:48:44 +0200 | [diff] [blame^] | 1568 | |
| 1569 | static void ddr_read_io_init(const mem_clock_t ddr_clock, |
| 1570 | const dimminfo_t *const dimms, |
| 1571 | const int sff) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1572 | { |
| 1573 | int ch; |
| 1574 | |
| 1575 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1576 | u32 addr, tmp; |
| 1577 | const unsigned int base = 0x14b0 + (ch * 0x0100); |
| 1578 | for (addr = base + 0x1c; addr >= base; addr -= 4) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1579 | tmp = mchbar_read32(addr); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1580 | tmp &= ~((3 << 25) | (1 << 8) | (7 << 16) | (0xf << 20) | (1 << 27)); |
| 1581 | tmp |= (1 << 27); |
Nico Huber | d131183 | 2019-08-11 17:48:44 +0200 | [diff] [blame^] | 1582 | switch (ddr_clock) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1583 | case MEM_CLOCK_667MT: |
| 1584 | tmp |= (1 << 16) | (4 << 20); |
| 1585 | break; |
| 1586 | case MEM_CLOCK_800MT: |
| 1587 | tmp |= (2 << 16) | (3 << 20); |
| 1588 | break; |
| 1589 | case MEM_CLOCK_1067MT: |
| 1590 | if (!sff) |
| 1591 | tmp |= (2 << 16) | (1 << 20); |
| 1592 | else |
| 1593 | tmp |= (2 << 16) | (2 << 20); |
| 1594 | break; |
| 1595 | default: |
| 1596 | die("Wrong clock"); |
| 1597 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1598 | mchbar_write32(addr, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1599 | } |
| 1600 | } |
| 1601 | } |
| 1602 | |
Nico Huber | d131183 | 2019-08-11 17:48:44 +0200 | [diff] [blame^] | 1603 | static void ddr3_memory_io_init(const mem_clock_t ddr3clock, |
| 1604 | const dimminfo_t *const dimms, |
| 1605 | const stepping_t stepping, |
| 1606 | const int sff) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1607 | { |
| 1608 | u32 tmp; |
| 1609 | |
| 1610 | if (stepping < STEPPING_B1) |
| 1611 | die("Stepping <B1 unsupported in " |
| 1612 | "system-memory i/o initialization.\n"); |
| 1613 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1614 | tmp = mchbar_read32(0x1400); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1615 | tmp &= ~(3<<13); |
| 1616 | tmp |= (1<<9) | (1<<13); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1617 | mchbar_write32(0x1400, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1618 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1619 | tmp = mchbar_read32(0x140c); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1620 | tmp &= ~(0xff | (1<<11) | (1<<12) | |
| 1621 | (1<<16) | (1<<18) | (1<<27) | (0xf<<28)); |
| 1622 | tmp |= (1<<7) | (1<<11) | (1<<16); |
| 1623 | switch (ddr3clock) { |
| 1624 | case MEM_CLOCK_667MT: |
| 1625 | tmp |= 9 << 28; |
| 1626 | break; |
| 1627 | case MEM_CLOCK_800MT: |
| 1628 | tmp |= 7 << 28; |
| 1629 | break; |
| 1630 | case MEM_CLOCK_1067MT: |
| 1631 | tmp |= 8 << 28; |
| 1632 | break; |
| 1633 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1634 | mchbar_write32(0x140c, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1635 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1636 | mchbar_clrbits32(0x1440, 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1637 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1638 | tmp = mchbar_read32(0x1414); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1639 | tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); |
| 1640 | tmp |= (3<<11); |
| 1641 | switch (ddr3clock) { |
| 1642 | case MEM_CLOCK_667MT: |
| 1643 | tmp |= (2 << 24) | (10 << 16); |
| 1644 | break; |
| 1645 | case MEM_CLOCK_800MT: |
| 1646 | tmp |= (3 << 24) | (7 << 16); |
| 1647 | break; |
| 1648 | case MEM_CLOCK_1067MT: |
| 1649 | tmp |= (4 << 24) | (4 << 16); |
| 1650 | break; |
| 1651 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1652 | mchbar_write32(0x1414, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1653 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1654 | mchbar_clrbits32(0x1418, 1 << 3 | 1 << 11 | 1 << 19 | 1 << 27); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1655 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1656 | mchbar_clrbits32(0x141c, 1 << 3 | 1 << 11 | 1 << 19 | 1 << 27); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1657 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1658 | mchbar_setbits32(0x1428, 1 << 14); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1659 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1660 | tmp = mchbar_read32(0x142c); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1661 | tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24)); |
| 1662 | tmp |= (0x3 << 20) | (5 << 24); |
| 1663 | switch (ddr3clock) { |
| 1664 | case MEM_CLOCK_667MT: |
| 1665 | tmp |= (2 << 8) | 0xc; |
| 1666 | break; |
| 1667 | case MEM_CLOCK_800MT: |
| 1668 | tmp |= (3 << 8) | 0xa; |
| 1669 | break; |
| 1670 | case MEM_CLOCK_1067MT: |
| 1671 | tmp |= (4 << 8) | 0x7; |
| 1672 | break; |
| 1673 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1674 | mchbar_write32(0x142c, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1675 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1676 | tmp = mchbar_read32(0x400); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1677 | tmp &= ~((3 << 4) | (3 << 16) | (3 << 30)); |
| 1678 | tmp |= (2 << 4) | (2 << 16); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1679 | mchbar_write32(0x400, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1680 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1681 | mchbar_clrbits32(0x404, 0xf << 20); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1682 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1683 | mchbar_clrbits32(0x40c, 1 << 6); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1684 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1685 | tmp = mchbar_read32(0x410); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1686 | tmp &= ~(7 << 28); |
| 1687 | tmp |= 2 << 28; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1688 | mchbar_write32(0x410, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1689 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1690 | tmp = mchbar_read32(0x41c); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1691 | tmp &= ~0x77; |
| 1692 | tmp |= 0x11; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1693 | mchbar_write32(0x41c, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1694 | |
| 1695 | ddr3_select_clock_mux(ddr3clock, dimms, stepping); |
| 1696 | |
| 1697 | ddr3_write_io_init(ddr3clock, dimms, stepping, sff); |
| 1698 | |
Nico Huber | d131183 | 2019-08-11 17:48:44 +0200 | [diff] [blame^] | 1699 | ddr_read_io_init(ddr3clock, dimms, sff); |
| 1700 | } |
| 1701 | |
| 1702 | static void ddr2_select_clock_mux(const dimminfo_t *const dimms) |
| 1703 | { |
| 1704 | int ch; |
| 1705 | unsigned int o; |
| 1706 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1707 | const unsigned int b = 0x14b0 + (ch * 0x0100); |
| 1708 | for (o = 0; o < 0x20; o += 4) |
| 1709 | mchbar_clrbits32(b + o, 7 << 11); |
| 1710 | } |
| 1711 | } |
| 1712 | |
| 1713 | static void ddr2_write_io_init(const dimminfo_t *const dimms) |
| 1714 | { |
| 1715 | int s; |
| 1716 | |
| 1717 | mchbar_clrsetbits32(CxWRTy_MCHBAR(0, 0), 0xf7bff71f, 0x008b0008); |
| 1718 | |
| 1719 | for (s = 1; s < 4; ++s) { |
| 1720 | mchbar_clrsetbits32(CxWRTy_MCHBAR(0, s), 0xf7bff71f, 0x00800000); |
| 1721 | } |
| 1722 | |
| 1723 | mchbar_clrsetbits32(0x1490, 0xf7fff77f, 0x00800000); |
| 1724 | mchbar_clrsetbits32(0x1494, 0xf71f8000, 0x00040000); |
| 1725 | |
| 1726 | mchbar_clrsetbits32(CxWRTy_MCHBAR(1, 0), 0xf7bff71f, 0x00890008); |
| 1727 | |
| 1728 | for (s = 1; s < 4; ++s) { |
| 1729 | mchbar_clrsetbits32(CxWRTy_MCHBAR(1, s), 0xf7bff71f, 0x00890000); |
| 1730 | } |
| 1731 | |
| 1732 | mchbar_clrsetbits32(0x1590, 0xf7fff77f, 0x00800000); |
| 1733 | mchbar_clrsetbits32(0x1594, 0xf71f8000, 0x00040000); |
| 1734 | } |
| 1735 | |
| 1736 | static void ddr2_memory_io_init(const mem_clock_t ddr2clock, |
| 1737 | const dimminfo_t *const dimms, |
| 1738 | const stepping_t stepping, |
| 1739 | const int sff) |
| 1740 | { |
| 1741 | u32 tmp; |
| 1742 | u32 tmp2; |
| 1743 | |
| 1744 | if (stepping < STEPPING_B1) |
| 1745 | die("Stepping <B1 unsupported in DDR2 memory i/o initialization.\n"); |
| 1746 | if (sff) |
| 1747 | die("SFF platform unsupported in DDR2 memory i/o initialization.\n"); |
| 1748 | |
| 1749 | tmp = mchbar_read32(0x140c); |
| 1750 | tmp &= ~(0xff | (1<<11) | (0xf<<28)); |
| 1751 | tmp |= (1<<0) | (1<<12) | (1<<16) | (1<<18) | (1<<27); |
| 1752 | mchbar_write32(0x140c, tmp); |
| 1753 | |
| 1754 | tmp = mchbar_read32(0x1440); |
| 1755 | tmp &= ~(1<<5); |
| 1756 | tmp |= (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<6); |
| 1757 | mchbar_write32(0x1440, tmp); |
| 1758 | |
| 1759 | tmp = mchbar_read32(0x1414); |
| 1760 | tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); |
| 1761 | tmp |= (3<<11); |
| 1762 | tmp2 = mchbar_read32(0x142c); |
| 1763 | tmp2 &= ~((0xf << 8) | (0x7 << 20) | 0xf); |
| 1764 | tmp2 |= (0x3 << 20); |
| 1765 | switch (ddr2clock) { |
| 1766 | case MEM_CLOCK_667MT: |
| 1767 | tmp |= (2 << 24) | (10 << 16); |
| 1768 | tmp2 |= (2 << 8) | 0xc; |
| 1769 | break; |
| 1770 | case MEM_CLOCK_800MT: |
| 1771 | tmp |= (3 << 24) | (7 << 16); |
| 1772 | tmp2 |= (3 << 8) | 0xa; |
| 1773 | break; |
| 1774 | default: |
| 1775 | die("Wrong clock"); |
| 1776 | } |
| 1777 | mchbar_write32(0x1414, tmp); |
| 1778 | mchbar_write32(0x142c, tmp2); |
| 1779 | |
| 1780 | mchbar_clrbits32(0x1418, (1<<3) | (1<<11) | (1<<19) | (1<<27)); |
| 1781 | mchbar_clrbits32(0x141c, (1<<3) | (1<<11) | (1<<19) | (1<<27)); |
| 1782 | |
| 1783 | tmp = mchbar_read32(0x400); |
| 1784 | tmp &= ~((3 << 4) | (3 << 16) | (3 << 30)); |
| 1785 | tmp |= (2 << 4) | (2 << 16); |
| 1786 | mchbar_write32(0x400, tmp); |
| 1787 | |
| 1788 | mchbar_clrbits32(0x404, 0xf << 20); |
| 1789 | |
| 1790 | mchbar_clrbits32(0x40c, 1 << 6); |
| 1791 | |
| 1792 | tmp = mchbar_read32(0x410); |
| 1793 | tmp &= ~(0xf << 28); |
| 1794 | tmp |= 2 << 28; |
| 1795 | mchbar_write32(0x410, tmp); |
| 1796 | |
| 1797 | tmp = mchbar_read32(0x41c); |
| 1798 | tmp &= ~((7<<0) | (7<<4)); |
| 1799 | tmp |= (1<<0) | (1<<3) | (1<<4) | (1<<7); |
| 1800 | mchbar_write32(0x41c, tmp); |
| 1801 | |
| 1802 | ddr2_select_clock_mux(dimms); |
| 1803 | |
| 1804 | ddr2_write_io_init(dimms); |
| 1805 | |
| 1806 | ddr_read_io_init(ddr2clock, dimms, sff); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1807 | } |
| 1808 | |
Nico Huber | c984788 | 2019-08-11 16:23:21 +0200 | [diff] [blame] | 1809 | static void jedec_command(const uintptr_t rankaddr, const u32 cmd, const u32 val) |
| 1810 | { |
| 1811 | mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, cmd); |
| 1812 | read32p(rankaddr | val); |
| 1813 | } |
| 1814 | |
| 1815 | static void jedec_init_ddr3(const timings_t *const timings, |
| 1816 | const dimminfo_t *const dimms) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1817 | { |
| 1818 | if ((timings->tWR < 5) || (timings->tWR > 12)) |
| 1819 | die("tWR value unsupported in Jedec initialization.\n"); |
| 1820 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1821 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1822 | |
| 1823 | /* 5 6 7 8 9 10 11 12 */ |
| 1824 | static const u8 wr_lut[] = { 1, 2, 3, 4, 5, 5, 6, 6 }; |
| 1825 | |
| 1826 | const int WL = ((timings->tWL - 5) & 7) << 6; |
| 1827 | const int ODT_120OHMS = (1 << 9); |
| 1828 | const int ODS_34OHMS = (1 << 4); |
| 1829 | const int WR = (wr_lut[timings->tWR - 5] & 7) << 12; |
| 1830 | const int DLL1 = 1 << 11; |
| 1831 | const int CAS = ((timings->CAS - 4) & 7) << 7; |
| 1832 | const int INTERLEAVED = 1 << 6;/* This is READ Burst Type == interleaved. */ |
| 1833 | |
| 1834 | int ch, r; |
| 1835 | FOR_EACH_POPULATED_RANK(dimms, ch, r) { |
| 1836 | /* We won't do this in dual-interleaved mode, |
Felix Held | 7f9f3d0 | 2019-06-07 14:47:28 +0200 | [diff] [blame] | 1837 | so don't care about the offset. |
| 1838 | Mirrored ranks aren't taken into account here. */ |
Nico Huber | c984788 | 2019-08-11 16:23:21 +0200 | [diff] [blame] | 1839 | const uintptr_t rankaddr = raminit_get_rank_addr(ch, r); |
| 1840 | printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", (u32)rankaddr); |
| 1841 | |
| 1842 | jedec_command(rankaddr, DCC_SET_EREGx(2), WL); |
| 1843 | jedec_command(rankaddr, DCC_SET_EREGx(3), 0); |
| 1844 | jedec_command(rankaddr, DCC_SET_EREGx(1), ODT_120OHMS | ODS_34OHMS); |
| 1845 | jedec_command(rankaddr, DCC_SET_MREG, WR | DLL1 | CAS | INTERLEAVED); |
| 1846 | jedec_command(rankaddr, DCC_SET_MREG, WR | CAS | INTERLEAVED); |
| 1847 | } |
| 1848 | } |
| 1849 | |
| 1850 | static void jedec_init_ddr2(const timings_t *const timings, |
| 1851 | const dimminfo_t *const dimms) |
| 1852 | { |
| 1853 | /* All bit offsets are off by 3 (2^3 bytes bus width). */ |
| 1854 | |
| 1855 | /* Mode Register (MR) settings */ |
| 1856 | const int WR = ((timings->tWR - 1) & 7) << 12; |
| 1857 | const int DLLreset = 1 << 11; |
| 1858 | const int CAS = (timings->CAS & 7) << 7; |
| 1859 | const int BTinterleaved = 1 << 6; |
| 1860 | const int BL8 = 3 << 3; |
| 1861 | |
| 1862 | /* Extended Mode Register 1 (EMR1) */ |
| 1863 | const int OCDdefault = 7 << 10; |
| 1864 | const int ODT_150OHMS = 1 << 9 | 0 << 5; |
| 1865 | |
| 1866 | int ch, r; |
| 1867 | FOR_EACH_POPULATED_RANK(dimms, ch, r) { |
| 1868 | /* We won't do this in dual-interleaved mode, |
| 1869 | so don't care about the offset. |
| 1870 | Mirrored ranks aren't taken into account here. */ |
| 1871 | const uintptr_t rankaddr = raminit_get_rank_addr(ch, r); |
| 1872 | printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", (u32)rankaddr); |
| 1873 | |
| 1874 | jedec_command(rankaddr, DCC_CMD_ABP, 0); |
| 1875 | jedec_command(rankaddr, DCC_SET_EREGx(2), 0); |
| 1876 | jedec_command(rankaddr, DCC_SET_EREGx(3), 0); |
| 1877 | jedec_command(rankaddr, DCC_SET_EREGx(1), ODT_150OHMS); |
| 1878 | jedec_command(rankaddr, DCC_SET_MREG, WR | DLLreset | CAS | BTinterleaved | BL8); |
| 1879 | jedec_command(rankaddr, DCC_CMD_ABP, 0); |
| 1880 | jedec_command(rankaddr, DCC_CMD_CBR, 0); |
| 1881 | udelay(1); |
| 1882 | read32((void *)(rankaddr)); |
| 1883 | |
| 1884 | jedec_command(rankaddr, DCC_SET_MREG, WR | CAS | BTinterleaved | BL8); |
| 1885 | jedec_command(rankaddr, DCC_SET_EREGx(1), OCDdefault | ODT_150OHMS); |
| 1886 | jedec_command(rankaddr, DCC_SET_EREGx(1), ODT_150OHMS); |
| 1887 | } |
| 1888 | } |
| 1889 | |
| 1890 | static void jedec_init(const int spd_type, |
| 1891 | const timings_t *const timings, |
| 1892 | const dimminfo_t *const dimms) |
| 1893 | { |
| 1894 | /* Pre-jedec settings */ |
| 1895 | mchbar_setbits32(0x40, 1 << 1); |
| 1896 | mchbar_setbits32(0x230, 3 << 1); |
| 1897 | mchbar_setbits32(0x238, 3 << 24); |
| 1898 | mchbar_setbits32(0x23c, 3 << 24); |
| 1899 | |
| 1900 | /* Normal write pointer operation */ |
| 1901 | mchbar_setbits32(0x14f0, 1 << 9); |
| 1902 | mchbar_setbits32(0x15f0, 1 << 9); |
| 1903 | |
| 1904 | mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP); |
| 1905 | |
| 1906 | pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); |
| 1907 | |
| 1908 | pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); |
| 1909 | udelay(2); |
| 1910 | |
| 1911 | if (spd_type == DDR2) { |
| 1912 | jedec_init_ddr2(timings, dimms); |
| 1913 | } else if (spd_type == DDR3) { |
| 1914 | jedec_init_ddr3(timings, dimms); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1915 | } |
| 1916 | } |
| 1917 | |
| 1918 | static void ddr3_calibrate_zq(void) { |
| 1919 | udelay(2); |
| 1920 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1921 | u32 tmp = mchbar_read32(DCC_MCHBAR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1922 | tmp &= ~(7 << 16); |
| 1923 | tmp |= (5 << 16); /* ZQ calibration mode */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1924 | mchbar_write32(DCC_MCHBAR, tmp); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1925 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1926 | mchbar_setbits32(CxDRT6_MCHBAR(0), 1 << 3); |
| 1927 | mchbar_setbits32(CxDRT6_MCHBAR(1), 1 << 3); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1928 | |
| 1929 | udelay(1); |
| 1930 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1931 | mchbar_clrbits32(CxDRT6_MCHBAR(0), 1 << 3); |
| 1932 | mchbar_clrbits32(CxDRT6_MCHBAR(1), 1 << 3); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1933 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1934 | mchbar_setbits32(DCC_MCHBAR, 7 << 16); /* Normal operation */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1935 | } |
| 1936 | |
| 1937 | static void post_jedec_sequence(const int cores) { |
| 1938 | const int quadcore = cores == 4; |
| 1939 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1940 | mchbar_clrbits32(0x0040, 1 << 1); |
| 1941 | mchbar_clrbits32(0x0230, 3 << 1); |
| 1942 | mchbar_setbits32(0x0230, 1 << 15); |
| 1943 | mchbar_clrbits32(0x0230, 1 << 19); |
| 1944 | mchbar_write32(0x1250, 0x6c4); |
| 1945 | mchbar_write32(0x1350, 0x6c4); |
| 1946 | mchbar_write32(0x1254, 0x871a066d); |
| 1947 | mchbar_write32(0x1354, 0x871a066d); |
| 1948 | mchbar_setbits32(0x0238, 1 << 26); |
| 1949 | mchbar_clrbits32(0x0238, 3 << 24); |
| 1950 | mchbar_setbits32(0x0238, 1 << 23); |
| 1951 | mchbar_clrsetbits32(0x0238, 7 << 20, 3 << 20); |
| 1952 | mchbar_clrsetbits32(0x0238, 7 << 17, 6 << 17); |
| 1953 | mchbar_clrsetbits32(0x0238, 7 << 14, 6 << 14); |
| 1954 | mchbar_clrsetbits32(0x0238, 7 << 11, 6 << 11); |
| 1955 | mchbar_clrsetbits32(0x0238, 7 << 8, 6 << 8); |
| 1956 | mchbar_clrbits32(0x023c, 3 << 24); |
| 1957 | mchbar_clrbits32(0x023c, 1 << 23); |
| 1958 | mchbar_clrsetbits32(0x023c, 7 << 20, 3 << 20); |
| 1959 | mchbar_clrsetbits32(0x023c, 7 << 17, 6 << 17); |
| 1960 | mchbar_clrsetbits32(0x023c, 7 << 14, 6 << 14); |
| 1961 | mchbar_clrsetbits32(0x023c, 7 << 11, 6 << 11); |
| 1962 | mchbar_clrsetbits32(0x023c, 7 << 8, 6 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1963 | |
| 1964 | if (quadcore) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1965 | mchbar_setbits32(0xb14, 0xbfbf << 16); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1966 | } |
| 1967 | } |
| 1968 | |
| 1969 | static void dram_optimizations(const timings_t *const timings, |
| 1970 | const dimminfo_t *const dimms) |
| 1971 | { |
| 1972 | int ch; |
| 1973 | |
| 1974 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1975 | const unsigned int mchbar = CxDRC1_MCHBAR(ch); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1976 | u32 cxdrc1 = mchbar_read32(mchbar); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1977 | cxdrc1 &= ~CxDRC1_SSDS_MASK; |
| 1978 | if (dimms[ch].ranks == 1) |
| 1979 | cxdrc1 |= CxDRC1_SS; |
| 1980 | else |
| 1981 | cxdrc1 |= CxDRC1_DS; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1982 | mchbar_write32(mchbar, cxdrc1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1983 | } |
| 1984 | } |
| 1985 | |
| 1986 | u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank) |
| 1987 | { |
| 1988 | if (!channel && !rank) |
| 1989 | return 0; /* Address of first rank */ |
| 1990 | |
| 1991 | /* Read the bound of the previous rank. */ |
| 1992 | if (rank > 0) { |
| 1993 | rank--; |
| 1994 | } else { |
| 1995 | rank = 3; /* Highest rank per channel */ |
| 1996 | channel--; |
| 1997 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 1998 | const u32 reg = mchbar_read32(CxDRBy_MCHBAR(channel, rank)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1999 | /* Bound is in 32MB. */ |
| 2000 | return ((reg & CxDRBy_BOUND_MASK(rank)) >> CxDRBy_BOUND_SHIFT(rank)) << 25; |
| 2001 | } |
| 2002 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 2003 | void raminit_reset_readwrite_pointers(void) |
| 2004 | { |
| 2005 | mchbar_setbits32(0x1234, 1 << 6); |
| 2006 | mchbar_clrbits32(0x1234, 1 << 6); |
| 2007 | mchbar_setbits32(0x1334, 1 << 6); |
| 2008 | mchbar_clrbits32(0x1334, 1 << 6); |
| 2009 | mchbar_clrbits32(0x14f0, 1 << 9); |
| 2010 | mchbar_setbits32(0x14f0, 1 << 9); |
| 2011 | mchbar_setbits32(0x14f0, 1 << 10); |
| 2012 | mchbar_clrbits32(0x15f0, 1 << 9); |
| 2013 | mchbar_setbits32(0x15f0, 1 << 9); |
| 2014 | mchbar_setbits32(0x15f0, 1 << 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2015 | } |
| 2016 | |
| 2017 | void raminit(sysinfo_t *const sysinfo, const int s3resume) |
| 2018 | { |
| 2019 | const dimminfo_t *const dimms = sysinfo->dimms; |
| 2020 | const timings_t *const timings = &sysinfo->selected_timings; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2021 | |
| 2022 | int ch; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2023 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 2024 | timestamp_add_now(TS_INITRAM_START); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2025 | |
| 2026 | /* Wait for some bit, maybe TXT clear. */ |
| 2027 | if (sysinfo->txt_enabled) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 2028 | while (!(read8((u8 *)0xfed40000) & (1 << 7))) {} |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2029 | } |
| 2030 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2031 | /* Collect information about DIMMs and find common settings. */ |
| 2032 | collect_dimm_config(sysinfo); |
| 2033 | |
| 2034 | /* Check for bad warm boot. */ |
| 2035 | reset_on_bad_warmboot(); |
| 2036 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2037 | /***** From now on, program according to collected infos: *****/ |
| 2038 | |
| 2039 | /* Program DRAM type. */ |
| 2040 | switch (sysinfo->spd_type) { |
| 2041 | case DDR2: |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 2042 | mchbar_setbits8(0x1434, 1 << 7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2043 | break; |
| 2044 | case DDR3: |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 2045 | mchbar_setbits8(0x1434, 3 << 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2046 | break; |
| 2047 | } |
| 2048 | |
| 2049 | /* Program system memory frequency. */ |
| 2050 | set_system_memory_frequency(timings); |
| 2051 | /* Program IGD memory frequency. */ |
| 2052 | set_igd_memory_frequencies(sysinfo); |
| 2053 | |
| 2054 | /* Configure DRAM control mode for populated channels. */ |
| 2055 | configure_dram_control_mode(timings, dimms); |
| 2056 | |
| 2057 | /* Initialize RCOMP. */ |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 2058 | rcomp_initialization(sysinfo->stepping, sysinfo->sff); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2059 | |
| 2060 | /* Power-up DRAM. */ |
| 2061 | dram_powerup(s3resume); |
| 2062 | /* Program DRAM timings. */ |
| 2063 | dram_program_timings(timings); |
| 2064 | /* Program number of banks. */ |
| 2065 | dram_program_banks(dimms); |
| 2066 | /* Enable DRAM clock pairs for populated DIMMs. */ |
| 2067 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 2068 | mchbar_setbits32(CxDCLKDIS_MCHBAR(ch), CxDCLKDIS_ENABLE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2069 | |
| 2070 | /* Enable On-Die Termination. */ |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 2071 | odt_setup(timings, sysinfo->sff); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2072 | /* Miscellaneous settings. */ |
| 2073 | misc_settings(timings, sysinfo->stepping); |
| 2074 | /* Program clock crossing registers. */ |
| 2075 | clock_crossing_setup(timings->fsb_clock, timings->mem_clock, dimms); |
| 2076 | /* Program egress VC1 timings. */ |
| 2077 | vc1_program_timings(timings->fsb_clock); |
| 2078 | /* Perform system-memory i/o initialization. */ |
Nico Huber | d131183 | 2019-08-11 17:48:44 +0200 | [diff] [blame^] | 2079 | if (sysinfo->spd_type == DDR2) { |
| 2080 | ddr2_memory_io_init(timings->mem_clock, dimms, |
| 2081 | sysinfo->stepping, sysinfo->sff); |
| 2082 | } else { |
| 2083 | ddr3_memory_io_init(timings->mem_clock, dimms, |
| 2084 | sysinfo->stepping, sysinfo->sff); |
| 2085 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2086 | |
| 2087 | /* Initialize memory map with dummy values of 128MB per rank with a |
| 2088 | page size of 4KB. This makes the JEDEC initialization code easier. */ |
| 2089 | prejedec_memory_map(dimms, timings->channel_mode); |
| 2090 | if (!s3resume) |
| 2091 | /* Perform JEDEC initialization of DIMMS. */ |
Nico Huber | c984788 | 2019-08-11 16:23:21 +0200 | [diff] [blame] | 2092 | jedec_init(sysinfo->spd_type, timings, dimms); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2093 | /* Some programming steps after JEDEC initialization. */ |
| 2094 | post_jedec_sequence(sysinfo->cores); |
| 2095 | |
| 2096 | /* Announce normal operation, initialization completed. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 2097 | mchbar_setbits32(DCC_MCHBAR, 0x7 << 16 | 0x1 << 19); |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 2098 | |
| 2099 | pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); |
| 2100 | |
| 2101 | pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2102 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2103 | /* Take a breath (the reader). */ |
| 2104 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2105 | /* Perform ZQ calibration for DDR3. */ |
Nico Huber | 4a86b3b | 2019-08-11 16:28:05 +0200 | [diff] [blame] | 2106 | if (sysinfo->spd_type == DDR3) |
| 2107 | ddr3_calibrate_zq(); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2108 | |
| 2109 | /* Perform receive-enable calibration. */ |
| 2110 | raminit_receive_enable_calibration(timings, dimms); |
| 2111 | /* Lend clock values from receive-enable calibration. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 2112 | mchbar_clrsetbits32(CxDRT5_MCHBAR(0), 0xf0, |
| 2113 | (((mchbar_read32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4); |
| 2114 | mchbar_clrsetbits32(CxDRT5_MCHBAR(1), 0xf0, |
| 2115 | (((mchbar_read32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2116 | |
| 2117 | /* Perform read/write training for high clock rate. */ |
| 2118 | if (timings->mem_clock == MEM_CLOCK_1067MT) { |
| 2119 | raminit_read_training(dimms, s3resume); |
| 2120 | raminit_write_training(timings->mem_clock, dimms, s3resume); |
| 2121 | } |
| 2122 | |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 2123 | igd_compute_ggc(sysinfo); |
| 2124 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2125 | /* Program final memory map (with real values). */ |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 2126 | program_memory_map(dimms, timings->channel_mode, 0, sysinfo->ggc); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2127 | |
| 2128 | /* Some last optimizations. */ |
| 2129 | dram_optimizations(timings, dimms); |
| 2130 | |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 2131 | /* Mark raminit being finished. :-) */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 2132 | pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 2133 | |
| 2134 | raminit_thermal(sysinfo); |
| 2135 | init_igd(sysinfo); |
Arthur Heymans | 049347f | 2017-05-12 11:54:08 +0200 | [diff] [blame] | 2136 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 2137 | timestamp_add_now(TS_INITRAM_END); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2138 | } |