Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 4 | #include <cf9_reset.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 6 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 7 | #include "gm45.h" |
| 8 | |
| 9 | void gm45_early_reset(void/*const timings_t *const timings*/) |
| 10 | { |
| 11 | int ch, r; |
| 12 | |
| 13 | /* Reset DRAM power-up settings in CLKCFG (they are not |
| 14 | affected by system reset but may disrupt raminit). */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 15 | mchbar_clrsetbits32(CLKCFG_MCHBAR, 3 << 21, 1 << 3); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 16 | |
| 17 | /*\ Next settings are the real purpose of this function: |
| 18 | If these steps are not performed, reset results in power off. \*/ |
| 19 | |
| 20 | /* Initialize some DRAM settings to 1 populated rank of 128MB. */ |
| 21 | FOR_EACH_CHANNEL(ch) { |
| 22 | /* Configure DRAM control mode. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 23 | mchbar_clrsetbits32(CxDRC0_MCHBAR(ch), CxDRC0_RANKEN_MASK, |
| 24 | (ch ? 0 : CxDRC0_RANKEN(0))); |
| 25 | mchbar_write32(CxDRC1_MCHBAR(ch), |
| 26 | (mchbar_read32(CxDRC1_MCHBAR(ch)) | CxDRC1_NOTPOP_MASK) & |
| 27 | ~(ch ? 0 : CxDRC1_NOTPOP(0))); |
| 28 | mchbar_write32(CxDRC2_MCHBAR(ch), |
| 29 | (mchbar_read32(CxDRC2_MCHBAR(ch)) | CxDRC2_NOTPOP_MASK) & |
| 30 | ~(ch ? 0 : CxDRC2_NOTPOP(0))); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 31 | /*if (timings && (timings->mem_clock == MEM_CLOCK_1067MT)) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 32 | mchbar_setbits32(CxDRC2_MCHBAR(ch), CxDRC2_CLK1067MT);*/ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 33 | |
| 34 | /* Program rank boundaries (CxDRBy). */ |
| 35 | for (r = 0; r < RANKS_PER_CHANNEL; r += 2) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 36 | mchbar_write32(CxDRBy_MCHBAR(ch, r), |
| 37 | CxDRBy_BOUND_MB(r, 128) | CxDRBy_BOUND_MB(r + 1, 128)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 38 | } |
| 39 | /* Set DCC mode to no operation and do magic 0xf0 thing. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 40 | mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP); |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 41 | |
| 42 | pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); |
| 43 | |
| 44 | pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); |
| 45 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 46 | /* Normally, we would set this after successful raminit. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 47 | mchbar_setbits32(DCC_MCHBAR, 1 << 19); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 48 | |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 49 | system_reset(); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 50 | } |