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Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08001# Warning: This file is included whether or not the if is here.
2# The if controls how the evaluation occurs.
3# (See also src/Kconfig)
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08004
Stefan Reinauera48ca842015-04-04 01:58:28 +02005source "src/cpu/*/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +00006
Furquan Shaikhfd337812014-04-22 15:16:54 -07007if ARCH_X86
8
Patrick Georgi0588d192009-08-12 15:00:51 +00009config DCACHE_RAM_BASE
10 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000011
12config DCACHE_RAM_SIZE
13 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000014
Timothy Pearsonb5e46552015-06-02 13:47:36 -050015config DCACHE_BSP_STACK_SIZE
16 hex
17
Felix Heldca928c62020-04-04 01:47:37 +020018config EARLYRAM_BSP_STACK_SIZE
19 depends on RESET_VECTOR_IN_RAM
20 hex
21
Patrick Georgi0588d192009-08-12 15:00:51 +000022config SMP
23 bool
Myles Watson45bb25f2009-09-22 18:49:08 +000024 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +000025 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000026 help
27 This option is used to enable certain functions to make coreboot
28 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000029
30config MMX
31 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000032 help
33 Select MMX in your socket or model Kconfig if your CPU has MMX
Elyes HAOUAS32fecd62020-02-22 10:15:33 +010034 streaming SIMD instructions.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000035
36config SSE
37 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000038 help
39 Select SSE in your socket or model Kconfig if your CPU has SSE
Elyes HAOUAS32fecd62020-02-22 10:15:33 +010040 streaming SIMD instructions.
Stefan Reinauera7acc512010-02-25 13:40:49 +000041
42config SSE2
43 bool
Myles Watson34261952010-03-19 02:33:40 +000044 default n
Aaron Durbinb1aa6112017-06-16 15:20:57 -050045 select SSE
Stefan Reinauera7acc512010-02-25 13:40:49 +000046 help
47 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
48 streaming SIMD instructions. Some parts of coreboot can be built
49 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000050
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000051endif # ARCH_X86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050052
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060053config SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050054 bool
55 default n
56
Martin Roth4c502692015-11-05 08:03:45 -070057config USES_MICROCODE_HEADER_FILES
58 def_bool n
59 select SUPPORT_CPU_UCODE_IN_CBFS
60 help
61 This is selected by a board or chipset to set the default for the
62 microcode source choice to a list of external microcode headers
63
Nico Huberf5ca9222018-11-29 17:05:32 +010064config MICROCODE_BLOB_NOT_IN_BLOB_REPO
65 bool
66 help
67 Selected by platforms that don't maintain microcode updates in the
68 blobs repo yet.
69
70config MICROCODE_BLOB_NOT_HOOKED_UP
71 bool
72 help
73 Selected by platforms that haven't hooked microcode updates up yet.
74
75config MICROCODE_BLOB_UNDISCLOSED
76 bool
77 help
78 Selected by work-in-progress platforms that don't have microcode
79 updates available yet.
80
81config USE_CPU_MICROCODE_CBFS_BINS
82 bool
83 help
84 Automatically selected below to add binary microcode files
85 (`cpu_microcode_bins` in the makefiles) to CBFS.
86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050087choice
Stefan Reinauer9c29cfa2013-02-27 20:24:11 +010088 prompt "Include CPU microcode in CBFS" if ARCH_X86
Martin Roth4c502692015-11-05 08:03:45 -070089 default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
Nico Huberf5ca9222018-11-29 17:05:32 +010090 default CPU_MICROCODE_CBFS_NONE if MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
91 MICROCODE_BLOB_NOT_HOOKED_UP || \
92 MICROCODE_BLOB_UNDISCLOSED
93 depends on SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050094
Nico Huberf5ca9222018-11-29 17:05:32 +010095config CPU_MICROCODE_CBFS_DEFAULT_BINS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050096 bool "Generate from tree"
Nico Huberf5ca9222018-11-29 17:05:32 +010097 select USE_CPU_MICROCODE_CBFS_BINS
98 depends on !(MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
99 MICROCODE_BLOB_NOT_HOOKED_UP || \
100 MICROCODE_BLOB_UNDISCLOSED)
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500101 help
102 Select this option if you want microcode updates to be assembled when
103 building coreboot and included in the final image as a separate CBFS
104 file. Microcode will not be hard-coded into ramstage.
105
Stefan Tauner0ce2b432013-04-01 13:45:44 +0200106 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500107 time with cbfstool, if desired.
108
109 If unsure, select this option.
110
Nico Huberf5ca9222018-11-29 17:05:32 +0100111config CPU_MICROCODE_CBFS_EXTERNAL_BINS
112 bool "Include external microcode binary"
113 select USE_CPU_MICROCODE_CBFS_BINS
Nico Huberf5ca9222018-11-29 17:05:32 +0100114 help
115 Select this option if you want to include external binary files
116 in the CPUs native format. They will be included as a separate
117 file in CBFS.
118
119 A word of caution: only select this option if you are sure the
120 microcode that you have is newer than the microcode shipping with
121 coreboot.
122
123 The microcode file may be removed from the ROM image at a later
124 time with cbfstool, if desired.
125
126 If unsure, and applicable, select "Generate from tree"
127
Martin Roth4c502692015-11-05 08:03:45 -0700128config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
129 bool "Include external microcode header files"
130 help
131 Select this option if you want to include external c header files
132 containing the CPU microcode. This will be included as a separate
133 file in CBFS.
134
135 A word of caution: only select this option if you are sure the
136 microcode that you have is newer than the microcode shipping with
137 coreboot.
138
139 The microcode file may be removed from the ROM image at a later
140 time with cbfstool, if desired.
141
Nico Huberf5ca9222018-11-29 17:05:32 +0100142 If unsure, and applicable, select "Generate from tree"
Martin Roth4c502692015-11-05 08:03:45 -0700143
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500144config CPU_MICROCODE_CBFS_NONE
145 bool "Do not include microcode updates"
146 help
147 Select this option if you do not want CPU microcode included in CBFS.
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500148
149 Microcode may be added to the ROM image at a later time with cbfstool,
150 if desired.
151
Nico Huberf5ca9222018-11-29 17:05:32 +0100152 If unsure, and applicable, select "Generate from tree"
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500153
154 The GOOD:
155 Microcode updates intend to solve issues that have been discovered
156 after CPU production. The expected effect is that systems work as
157 intended with the updated microcode, but we have also seen cases where
158 issues were solved by not applying microcode updates.
159
160 The BAD:
161 Note that some operating system include these same microcode patches,
162 so you may need to also disable microcode updates in your operating
163 system for this option to have an effect.
164
165 The UGLY:
166 A word of CAUTION: some CPUs depend on microcode updates to function
167 correctly. Not updating the microcode may leave the CPU operating at
168 less than optimal performance, or may cause outright hangups.
169 There are CPUs where coreboot cannot properly initialize the CPU
170 without microcode updates
171 For example, if running with the factory microcode, some Intel
172 SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
173 will hang when changing the frequency.
174
175 Make sure you have a way of flashing the ROM externally before
176 selecting this option.
177
178endchoice
Jens Rottmann686dc0d2013-02-18 17:26:01 +0100179
Martin Roth4c502692015-11-05 08:03:45 -0700180config CPU_MICROCODE_HEADER_FILES
181 string "List of space separated microcode header files with the path"
182 depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER
183 help
184 A list of one or more microcode header files with path from the
185 coreboot directory. These should be separated by spaces.
Martin Roth3eb65ec2016-08-30 16:21:53 -0600186
187config CPU_UCODE_BINARIES
188 string "Microcode binary path and filename"
Nico Huberf5ca9222018-11-29 17:05:32 +0100189 depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS
Martin Roth3eb65ec2016-08-30 16:21:53 -0600190 default ""
191 help
192 Some platforms have microcode in the blobs directory, and these can
193 be hardcoded in the makefiles. For platforms with microcode
194 binaries that aren't in the makefile, set this option to pull
195 in the microcode.
196
197 This should contain the full path of the file for one or more
198 microcode binary files to include, separated by spaces.
199
200 If unsure, leave this blank.