| Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007 AMD |
| 5 | ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; either version 2 of the License, or |
| 10 | ## (at your option) any later version. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | ## You should have received a copy of the GNU General Public License |
| 18 | ## along with this program; if not, write to the Free Software |
| 19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | ## |
| 21 | |
| 22 | ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| 23 | # for testing with -O != s. FIXME |
| 24 | #default CONFIG_XIP_ROM_SIZE = 128 * 1024 |
| 25 | default CONFIG_XIP_ROM_SIZE = 128 * 1024 |
| 26 | include /config/failovercalculation.lb |
| 27 | |
| 28 | arch i386 end |
| 29 | |
| 30 | ## |
| 31 | ## Build the objects we have code for in this directory. |
| 32 | ## |
| 33 | |
| 34 | driver mainboard.o |
| 35 | #needed by irq_tables and mptable and acpi_tables |
| 36 | object get_bus_conf.o |
| 37 | |
| 38 | if CONFIG_GENERATE_MP_TABLE object mptable.o end |
| 39 | if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end |
| 40 | |
| 41 | if CONFIG_USE_INIT |
| 42 | makerule ./auto.o |
| 43 | depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 44 | action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| 45 | end |
| 46 | else |
| 47 | makerule ./auto.inc |
| 48 | depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 49 | action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| 50 | action "perl -e 's/\.rodata/.rom.data/g' -pi $@" |
| 51 | action "perl -e 's/\.text/.section .rom.text/g' -pi $@" |
| 52 | end |
| 53 | end |
| 54 | |
| 55 | if CONFIG_USE_FAILOVER_IMAGE |
| 56 | else |
| 57 | if CONFIG_AP_CODE_IN_CAR |
| 58 | makerule ./apc_auto.o |
| 59 | depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" |
| 60 | action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" |
| 61 | end |
| 62 | end |
| 63 | end |
| 64 | |
| 65 | |
| 66 | ## |
| 67 | ## Build our 16 bit and 32 bit coreboot entry code |
| 68 | ## |
| 69 | if CONFIG_HAVE_FAILOVER_BOOT |
| 70 | if CONFIG_USE_FAILOVER_IMAGE |
| 71 | mainboardinit cpu/x86/16bit/entry16.inc |
| 72 | ldscript /cpu/x86/16bit/entry16.lds |
| 73 | end |
| 74 | else |
| 75 | if CONFIG_USE_FALLBACK_IMAGE |
| 76 | mainboardinit cpu/x86/16bit/entry16.inc |
| 77 | ldscript /cpu/x86/16bit/entry16.lds |
| 78 | end |
| 79 | end |
| 80 | |
| 81 | mainboardinit cpu/x86/32bit/entry32.inc |
| 82 | |
| 83 | if CONFIG_USE_INIT |
| 84 | ldscript /cpu/x86/32bit/entry32.lds |
| 85 | end |
| 86 | |
| 87 | if CONFIG_USE_INIT |
| 88 | ldscript /cpu/amd/car/cache_as_ram.lds |
| 89 | end |
| 90 | |
| 91 | ## |
| 92 | ## Build our reset vector (This is where coreboot is entered) |
| 93 | ## |
| 94 | if CONFIG_HAVE_FAILOVER_BOOT |
| 95 | if CONFIG_USE_FAILOVER_IMAGE |
| 96 | mainboardinit cpu/x86/16bit/reset16.inc |
| 97 | ldscript /cpu/x86/16bit/reset16.lds |
| 98 | else |
| 99 | mainboardinit cpu/x86/32bit/reset32.inc |
| 100 | ldscript /cpu/x86/32bit/reset32.lds |
| 101 | end |
| 102 | else |
| 103 | if CONFIG_USE_FALLBACK_IMAGE |
| 104 | mainboardinit cpu/x86/16bit/reset16.inc |
| 105 | ldscript /cpu/x86/16bit/reset16.lds |
| 106 | else |
| 107 | mainboardinit cpu/x86/32bit/reset32.inc |
| 108 | ldscript /cpu/x86/32bit/reset32.lds |
| 109 | end |
| 110 | end |
| 111 | |
| 112 | ## |
| 113 | ## Include an id string (For safe flashing) |
| 114 | ## |
| 115 | mainboardinit arch/i386/lib/id.inc |
| 116 | ldscript /arch/i386/lib/id.lds |
| 117 | |
| 118 | ## |
| 119 | ## ROMSTRAP table for MCP55 |
| 120 | ## |
| 121 | if CONFIG_HAVE_FAILOVER_BOOT |
| 122 | if CONFIG_USE_FAILOVER_IMAGE |
| 123 | mainboardinit southbridge/nvidia/mcp55/romstrap.inc |
| 124 | ldscript /southbridge/nvidia/mcp55/romstrap.lds |
| 125 | end |
| 126 | else |
| 127 | if CONFIG_USE_FALLBACK_IMAGE |
| 128 | mainboardinit southbridge/nvidia/mcp55/romstrap.inc |
| 129 | ldscript /southbridge/nvidia/mcp55/romstrap.lds |
| 130 | end |
| 131 | end |
| 132 | |
| 133 | ## |
| 134 | ## Setup Cache-As-Ram |
| 135 | ## |
| 136 | mainboardinit cpu/amd/car/cache_as_ram.inc |
| 137 | |
| 138 | ### |
| 139 | ### This is the early phase of coreboot startup |
| 140 | ### Things are delicate and we test to see if we should |
| 141 | ### failover to another image. |
| 142 | ### |
| 143 | if CONFIG_HAVE_FAILOVER_BOOT |
| 144 | if CONFIG_USE_FAILOVER_IMAGE |
| 145 | ldscript /arch/i386/lib/failover_failover.lds |
| 146 | end |
| 147 | else |
| 148 | if CONFIG_USE_FALLBACK_IMAGE |
| 149 | ldscript /arch/i386/lib/failover.lds |
| 150 | end |
| 151 | end |
| 152 | |
| 153 | ## |
| 154 | ## Setup RAM |
| 155 | ## |
| 156 | if CONFIG_USE_INIT |
| 157 | initobject auto.o |
| 158 | else |
| 159 | mainboardinit ./auto.inc |
| 160 | end |
| 161 | |
| 162 | ## |
| 163 | ## Include the secondary Configuration files |
| 164 | ## |
| 165 | config chip.h |
| 166 | |
| 167 | dir /southbridge/nvidia/mcp55 |
| 168 | dir /southbridge/amd/amd8132 |
| 169 | |
| 170 | chip northbridge/amd/amdfam10/root_complex |
| 171 | device apic_cluster 0 on |
| 172 | chip cpu/amd/socket_F_1207 |
| 173 | device apic 0 on end |
| 174 | end |
| 175 | end |
| 176 | device pci_domain 0 on |
| 177 | chip northbridge/amd/amdfam10 #mc0 |
| 178 | device pci 18.0 on end |
| 179 | device pci 18.0 on end |
| 180 | device pci 18.0 on |
| 181 | # SB on link 2.0 |
| 182 | chip southbridge/nvidia/mcp55 |
| 183 | device pci 0.0 on end # HT |
| 184 | device pci 1.0 on # LPC |
| 185 | chip superio/winbond/w83627hf |
| 186 | device pnp 2e.0 off # Floppy |
| 187 | io 0x60 = 0x3f0 |
| 188 | irq 0x70 = 6 |
| 189 | drq 0x74 = 2 |
| 190 | end |
| 191 | device pnp 2e.1 off # Parallel Port |
| 192 | io 0x60 = 0x378 |
| 193 | irq 0x70 = 7 |
| 194 | end |
| 195 | device pnp 2e.2 on # Com1 |
| 196 | io 0x60 = 0x3f8 |
| 197 | irq 0x70 = 4 |
| 198 | end |
| 199 | device pnp 2e.3 off # Com2 |
| 200 | io 0x60 = 0x2f8 |
| 201 | irq 0x70 = 3 |
| 202 | end |
| 203 | device pnp 2e.5 on # Keyboard |
| 204 | io 0x60 = 0x60 |
| 205 | io 0x62 = 0x64 |
| 206 | irq 0x70 = 1 |
| 207 | irq 0x72 = 12 |
| 208 | end |
| 209 | device pnp 2e.6 off # SFI |
| 210 | io 0x62 = 0x100 |
| 211 | end |
| 212 | device pnp 2e.7 off # GPIO_GAME_MIDI |
| 213 | io 0x60 = 0x220 |
| 214 | io 0x62 = 0x300 |
| 215 | irq 0x70 = 9 |
| 216 | end |
| 217 | device pnp 2e.8 off end # WDTO_PLED |
| 218 | device pnp 2e.9 off end # GPIO_SUSLED |
| 219 | device pnp 2e.a off end # ACPI |
| 220 | device pnp 2e.b on # HW Monitor |
| 221 | io 0x60 = 0x290 |
| 222 | irq 0x70 = 5 |
| 223 | end |
| 224 | end |
| 225 | end |
| 226 | device pci 1.1 on # SM 0 |
| 227 | # chip drivers/generic/generic #dimm 0-0-0 |
| 228 | # device i2c 50 on end |
| 229 | # end |
| 230 | # chip drivers/generic/generic #dimm 0-0-1 |
| 231 | # device i2c 51 on end |
| 232 | # end |
| 233 | # chip drivers/generic/generic #dimm 0-1-0 |
| 234 | # device i2c 52 on end |
| 235 | # end |
| 236 | # chip drivers/generic/generic #dimm 0-1-1 |
| 237 | # device i2c 53 on end |
| 238 | # end |
| 239 | # chip drivers/generic/generic #dimm 1-0-0 |
| 240 | # device i2c 54 on end |
| 241 | # end |
| 242 | # chip drivers/generic/generic #dimm 1-0-1 |
| 243 | # device i2c 55 on end |
| 244 | # end |
| 245 | # chip drivers/generic/generic #dimm 1-1-0 |
| 246 | # device i2c 56 on end |
| 247 | # end |
| 248 | # chip drivers/generic/generic #dimm 1-1-1 |
| 249 | # device i2c 57 on end |
| 250 | # end |
| 251 | # chip drivers/generic/generic #dimm 2-0-0 |
| 252 | # device i2c 58 on end |
| 253 | # end |
| 254 | # chip drivers/generic/generic #dimm 2-0-1 |
| 255 | # device i2c 59 on end |
| 256 | # end |
| 257 | # chip drivers/generic/generic #dimm 2-1-0 |
| 258 | # device i2c 5a on end |
| 259 | # end |
| 260 | # chip drivers/generic/generic #dimm 2-1-1 |
| 261 | # device i2c 5b on end |
| 262 | # end |
| 263 | # chip drivers/generic/generic #dimm 3-0-0 |
| 264 | # device i2c 5c on end |
| 265 | # end |
| 266 | # chip drivers/generic/generic #dimm 3-0-1 |
| 267 | # device i2c 5d on end |
| 268 | # end |
| 269 | # chip drivers/generic/generic #dimm 3-1-0 |
| 270 | # device i2c 5e on end |
| 271 | # end |
| 272 | # chip drivers/generic/generic #dimm 3-1-1 |
| 273 | # device i2c 5f on end |
| 274 | # end |
| 275 | |
| 276 | end # SM |
| 277 | device pci 1.1 on # SM 1 |
| 278 | #PCI device smbus address will diepend on addon pci device, do we need to scan_smbus_bus? |
| 279 | # |
| 280 | chip drivers/generic/generic #MAC EEPROM |
| 281 | device i2c 51 on end |
| 282 | end |
| 283 | |
| 284 | end # SM |
| 285 | device pci 2.0 on end # USB 1.1 |
| 286 | device pci 2.1 on end # USB 2 |
| 287 | device pci 4.0 on end # IDE |
| 288 | device pci 5.0 on end # SATA 0 |
| 289 | device pci 5.1 on end # SATA 1 |
| 290 | device pci 5.2 on end # SATA 2 |
| Uwe Hermann | d0d7c01 | 2010-02-03 22:07:57 +0000 | [diff] [blame^] | 291 | device pci 6.1 off end # AZA |
| 292 | device pci 7.0 on |
| 293 | device pci 1.0 on end |
| 294 | end |
| 295 | device pci 8.0 off end |
| 296 | device pci 9.0 off end |
| Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 297 | device pci a.0 on end # PCI E 5 |
| 298 | device pci b.0 on end # PCI E 4 |
| 299 | device pci c.0 on end # PCI E 3 |
| 300 | device pci d.0 on end # PCI E 2 |
| 301 | device pci e.0 on end # PCI E 1 |
| 302 | device pci f.0 on end # PCI E 0 |
| 303 | register "ide0_enable" = "1" |
| 304 | register "sata0_enable" = "1" |
| 305 | register "sata1_enable" = "1" |
| 306 | register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 |
| 307 | register "mac_eeprom_addr" = "0x51" |
| 308 | end |
| 309 | end # device pci 18.0 |
| 310 | device pci 18.1 on end |
| 311 | device pci 18.2 on end |
| 312 | device pci 18.3 on end |
| 313 | device pci 18.4 on end |
| 314 | device pci 19.0 on end |
| Uwe Hermann | d0d7c01 | 2010-02-03 22:07:57 +0000 | [diff] [blame^] | 315 | device pci 19.0 on end |
| 316 | device pci 19.0 on |
| 317 | chip southbridge/amd/amd8132 |
| 318 | device pci 0.0 on end |
| 319 | device pci 0.1 on end |
| 320 | device pci 1.0 on |
| 321 | device pci 3.0 on end |
| 322 | device pci 3.1 on end |
| 323 | end |
| 324 | device pci 1.1 on end |
| 325 | end #amd8132 |
| 326 | end #device pci 19.0 |
| Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 327 | device pci 19.1 on end |
| 328 | device pci 19.2 on end |
| 329 | device pci 19.3 on end |
| 330 | device pci 19.4 on end |
| 331 | end # mc0 |
| 332 | |
| 333 | end # PCI domain |
| 334 | |
| 335 | # chip drivers/generic/debug |
| 336 | # device pnp 0.0 off end # chip name |
| 337 | # device pnp 0.1 on end # pci_regs_all |
| 338 | # device pnp 0.2 off end # mem |
| 339 | # device pnp 0.3 off end # cpuid |
| 340 | # device pnp 0.4 on end # smbus_regs_all |
| 341 | # device pnp 0.5 off end # dual core msr |
| 342 | # device pnp 0.6 off end # cache size |
| 343 | # device pnp 0.7 off end # tsc |
| 344 | # device pnp 0.8 off end # io |
| 345 | # device pnp 0.9 on end # io |
| 346 | # end |
| 347 | end #root_complex |