Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 4 | #include <cbmem.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 5 | #include <cpu/x86/smm.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Elyes HAOUAS | 32da343 | 2020-05-17 17:15:31 +0200 | [diff] [blame] | 9 | #include <cpu/x86/lapic_def.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 10 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | #include <soc/iomap.h> |
| 12 | #include <soc/iosf.h> |
| 13 | #include <soc/pci_devs.h> |
| 14 | #include <soc/ramstage.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 15 | #include <vendorcode/google/chromeos/chromeos.h> |
Harry Pan | 43dcbfd | 2016-08-11 14:35:04 +0800 | [diff] [blame] | 16 | #include <stddef.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 18 | /* |
| 19 | * Host Memory Map: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | * |
| 21 | * +--------------------------+ BMBOUND_HI |
| 22 | * | Usable DRAM | |
| 23 | * +--------------------------+ 4GiB |
| 24 | * | PCI Address Space | |
| 25 | * +--------------------------+ BMBOUND |
| 26 | * | TPM | |
| 27 | * +--------------------------+ IMR2 |
| 28 | * | TXE | |
| 29 | * +--------------------------+ IMR1 |
| 30 | * | iGD | |
| 31 | * +--------------------------+ |
| 32 | * | GTT | |
| 33 | * +--------------------------+ SMMRRH, IRM0 |
| 34 | * | TSEG | |
| 35 | * +--------------------------+ SMMRRL |
| 36 | * | Usable DRAM | |
| 37 | * +--------------------------+ 0 |
| 38 | * |
| 39 | * Note that there are really only a few regions that need to enumerated w.r.t. |
Frans Hendriks | b81dcc6 | 2018-12-10 10:30:37 +0100 | [diff] [blame] | 40 | * coreboot's resource model: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 41 | * |
| 42 | * +--------------------------+ BMBOUND_HI |
| 43 | * | Cacheable/Usable | |
| 44 | * +--------------------------+ 4GiB |
| 45 | * |
| 46 | * +--------------------------+ BMBOUND |
| 47 | * | Uncacheable/Reserved | |
| 48 | * +--------------------------+ SMMRRH |
| 49 | * | Cacheable/Reserved | |
| 50 | * +--------------------------+ SMMRRL |
| 51 | * | Cacheable/Usable | |
| 52 | * +--------------------------+ 0 |
| 53 | */ |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 54 | #define RES_IN_KiB(r) ((r) >> 10) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 55 | |
| 56 | uint32_t nc_read_top_of_low_memory(void) |
| 57 | { |
Kyösti Mälkki | fcbbb91 | 2020-04-20 10:21:39 +0300 | [diff] [blame] | 58 | static uint32_t tolm; |
Harry Pan | 43dcbfd | 2016-08-11 14:35:04 +0800 | [diff] [blame] | 59 | |
| 60 | if (tolm) |
| 61 | return tolm; |
| 62 | |
| 63 | tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); |
| 64 | |
| 65 | return tolm; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 66 | } |
| 67 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 68 | static void nc_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 69 | { |
| 70 | unsigned long mmconf; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 71 | unsigned long bmbound_k; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 72 | unsigned long bmbound_hi; |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 73 | uintptr_t smm_base; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 74 | size_t smm_size; |
| 75 | unsigned long tseg_base_k; |
| 76 | unsigned long tseg_top_k; |
| 77 | unsigned long fsp_res_base_k; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 78 | unsigned long base_k, size_k; |
| 79 | const unsigned long four_gig_kib = (4 << (30 - 10)); |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 80 | void *fsp_reserved_memory_area; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 81 | int index = 0; |
| 82 | |
| 83 | /* Read standard PCI resources. */ |
| 84 | pci_dev_read_resources(dev); |
| 85 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 86 | /* Determine TSEG data */ |
| 87 | smm_region(&smm_base, &smm_size); |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 88 | tseg_base_k = RES_IN_KiB(smm_base); |
| 89 | tseg_top_k = tseg_base_k + RES_IN_KiB(smm_size); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 90 | |
| 91 | /* Determine the base of the FSP reserved memory */ |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 92 | fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); |
| 93 | if (fsp_reserved_memory_area) { |
Angel Pons | 31d6cd7 | 2020-07-26 22:31:45 +0200 | [diff] [blame] | 94 | fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area); |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 95 | } else { |
| 96 | /* If no FSP reserverd area */ |
| 97 | fsp_res_base_k = tseg_base_k; |
| 98 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 99 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 100 | /* PCIe memory-mapped config space access - 256 MiB. */ |
| 101 | mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 102 | mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 103 | |
| 104 | /* 0 -> 0xa0000 */ |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 105 | base_k = RES_IN_KiB(0); |
| 106 | size_k = RES_IN_KiB(0xa0000) - base_k; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 107 | ram_resource(dev, index++, base_k, size_k); |
| 108 | |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 109 | /* High memory -> fsp_res_base - cacheable and usable */ |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 110 | base_k = RES_IN_KiB(0x100000); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 111 | size_k = fsp_res_base_k - base_k; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | ram_resource(dev, index++, base_k, size_k); |
| 113 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 114 | /* fsp_res_base -> tseg_top - Reserved */ |
| 115 | base_k = fsp_res_base_k; |
| 116 | size_k = tseg_top_k - base_k; |
| 117 | reserved_ram_resource(dev, index++, base_k, size_k); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 118 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 119 | /* TSEG TOP -> bmbound is memory backed mmio. */ |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 120 | bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory()); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 121 | mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 122 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 123 | /* |
| 124 | * The BMBOUND_HI register matches register bits of 31:24 with address |
| 125 | * bits of 35:28. Therefore, shift register to align properly. |
| 126 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 127 | bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 128 | bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 129 | if (bmbound_hi > four_gig_kib) |
Angel Pons | 31d6cd7 | 2020-07-26 22:31:45 +0200 | [diff] [blame] | 130 | ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 131 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 132 | /* |
| 133 | * Reserve everything between A segment and 1MB: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 134 | * |
| 135 | * 0xa0000 - 0xbffff: legacy VGA |
| 136 | * 0xc0000 - 0xfffff: RAM |
| 137 | */ |
| 138 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
Angel Pons | 31d6cd7 | 2020-07-26 22:31:45 +0200 | [diff] [blame] | 139 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | |
Frans Hendriks | d97eb64 | 2018-11-26 11:01:56 +0100 | [diff] [blame] | 141 | /* |
| 142 | * Reserve local APIC |
| 143 | */ |
Angel Pons | 3a713c0 | 2020-07-26 22:28:37 +0200 | [diff] [blame] | 144 | base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE); |
| 145 | size_k = RES_IN_KiB(0x00100000); |
Frans Hendriks | d97eb64 | 2018-11-26 11:01:56 +0100 | [diff] [blame] | 146 | mmio_resource(dev, index++, base_k, size_k); |
| 147 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 148 | if (CONFIG(CHROMEOS)) |
Frans Hendriks | ed7780d | 2018-12-14 07:49:18 +0100 | [diff] [blame] | 149 | chromeos_reserve_ram_oops(dev, index++); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | static struct device_operations nc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 153 | .acpi_fill_ssdt = generate_cpu_entries, |
| 154 | .read_resources = nc_read_resources, |
| 155 | .ops_pci = &soc_pci_ops, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | static const struct pci_driver nc_driver __pci_driver = { |
| 159 | .ops = &nc_ops, |
| 160 | .vendor = PCI_VENDOR_ID_INTEL, |
| 161 | .device = SOC_DEVID, |
| 162 | }; |