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review.coreboot.org / coreboot / d0310faa3bc4d3b62d17d632fbaee98c146eebe0 / . / src / southbridge / intel / ibexpeak / pch.c
blob: 9148b44a8e4e8a0322e3c80c2be0c42d55e2f176 [file] [log] [blame]
Arthur Heymansd0310fa2019-10-02 00:21:01 +0200[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright 2013 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <console/console.h>
19#include <device/pci_ops.h>
20#include <device/device.h>
21#include <device/pci.h>
22#include <device/pci_def.h>
23#include "pch.h"
24
25/* Set bit in function disable register to hide this device */
26static void pch_disable_devfn(struct device *dev)
27{
28 switch (dev->path.pci.devfn) {
29 case PCI_DEVFN(22, 0): /* MEI #1 */
30 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
31 break;
32 case PCI_DEVFN(22, 1): /* MEI #2 */
33 RCBA32_OR(FD2, PCH_DISABLE_MEI2);
34 break;
35 case PCI_DEVFN(22, 2): /* IDE-R */
36 RCBA32_OR(FD2, PCH_DISABLE_IDER);
37 break;
38 case PCI_DEVFN(22, 3): /* KT */
39 RCBA32_OR(FD2, PCH_DISABLE_KT);
40 break;
41 case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
42 RCBA32_OR(BUC, PCH_DISABLE_GBE);
43 break;
44 case PCI_DEVFN(26, 0): /* EHCI #2 */
45 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
46 break;
47 case PCI_DEVFN(27, 0): /* HD Audio Controller */
48 RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
49 break;
50 case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
51 case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
52 case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
53 case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
54 case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
55 case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
56 case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
57 case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
58 RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
59 break;
60 case PCI_DEVFN(29, 0): /* EHCI #1 */
61 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
62 break;
63 case PCI_DEVFN(31, 0): /* LPC */
64 RCBA32_OR(FD, PCH_DISABLE_LPC);
65 break;
66 case PCI_DEVFN(31, 2): /* SATA #1 */
67 RCBA32_OR(FD, PCH_DISABLE_SATA1);
68 break;
69 case PCI_DEVFN(31, 3): /* SMBUS */
70 RCBA32_OR(FD, PCH_DISABLE_SMBUS);
71 break;
72 case PCI_DEVFN(31, 5): /* SATA #22 */
73 RCBA32_OR(FD, PCH_DISABLE_SATA2);
74 break;
75 case PCI_DEVFN(31, 6): /* Thermal Subsystem */
76 RCBA32_OR(FD, PCH_DISABLE_THERMAL);
77 break;
78 }
79}
80
81void pch_enable(struct device *dev)
82{
83 u32 reg32;
84
85 if (!dev->enabled) {
86 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
87
88 /* Ensure memory, io, and bus master are all disabled */
89 reg32 = pci_read_config32(dev, PCI_COMMAND);
90 reg32 &= ~(PCI_COMMAND_MASTER |
91 PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
92 pci_write_config32(dev, PCI_COMMAND, reg32);
93
94 /* Disable this device if possible */
95 pch_disable_devfn(dev);
96 } else {
97 /* Enable SERR */
98 reg32 = pci_read_config32(dev, PCI_COMMAND);
99 reg32 |= PCI_COMMAND_SERR;
100 pci_write_config32(dev, PCI_COMMAND, reg32);
101 }
102}
103
104struct chip_operations southbridge_intel_ibexpeak_ops = {
105 CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge")
106 .enable_dev = pch_enable,
107};