blob: c0e830d4671fa29b5ee6d307d69cff36db9a2753 [file] [log] [blame]
Julien Viard de Galbert4f136402018-02-16 14:40:53 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
5 * Copyright (C) 2014 - 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <types.h>
19#include <string.h>
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010020#include <arch/acpi.h>
21#include <arch/ioapic.h>
22#include <arch/acpigen.h>
23#include <arch/smp/mpspec.h>
24#include <device/device.h>
25#include <device/pci.h>
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010026#include <cpu/x86/msr.h>
27
Julien Viard de Galbertcf2b72f2018-04-05 11:24:45 +020028#include <intelblocks/acpi.h>
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010029#include <soc/acpi.h>
30#include <soc/nvs.h>
31
32extern const unsigned char AmlCode[];
33
34void acpi_create_gnvs(global_nvs_t *gnvs)
35{
36 acpi_init_gnvs(gnvs);
37
38 /* Disable USB ports in S5 */
39 gnvs->s5u0 = 0;
40 gnvs->s5u1 = 0;
41
42 /* TPM Present */
43 gnvs->tpmp = 0;
44}