Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
| 21 | #include <arch/io.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 26 | #include <arch/acpi.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
| 28 | #include <console/console.h> |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 29 | #include <superio/smsc/sio1007/chip.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 31 | #include <northbridge/intel/sandybridge/raminit.h> |
| 32 | #include <southbridge/intel/bd82x6x/pch.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 33 | #include <arch/cpu.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 34 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 35 | #include <halt.h> |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 36 | #include <tpm.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 37 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 38 | #define SIO_PORT 0x164e |
| 39 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 40 | void pch_enable_lpc(void) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 41 | { |
| 42 | device_t dev = PCH_LPC_DEV; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 43 | |
| 44 | /* Set COM1/COM2 decode range */ |
| 45 | pci_write_config16(dev, LPC_IO_DEC, 0x0010); |
| 46 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 47 | /* Enable SuperIO + PS/2 Keyboard/Mouse */ |
| 48 | u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 49 | pci_write_config16(dev, LPC_EN, lpc_config); |
| 50 | |
| 51 | /* Map 256 bytes at 0x1600 to the LPC bus. */ |
| 52 | pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); |
| 53 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 54 | /* Map a range for the runtime_port registers to the LPC bus. */ |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 55 | pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); |
| 56 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 57 | /* Enable COM1 */ |
| 58 | if (sio1007_enable_uart_at(SIO_PORT)) { |
| 59 | pci_write_config16(dev, LPC_EN, |
| 60 | lpc_config | COMA_LPC_EN); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 61 | } |
| 62 | } |
| 63 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 64 | void rcba_config(void) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 65 | { |
| 66 | u32 reg32; |
| 67 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 68 | southbridge_configure_default_intmap(); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 69 | |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 70 | /* Disable unused devices (board specific) */ |
| 71 | reg32 = RCBA32(FD); |
| 72 | reg32 |= PCH_DISABLE_ALWAYS; |
| 73 | RCBA32(FD) = reg32; |
| 74 | } |
| 75 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 76 | void mainboard_config_superio(void) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 77 | { |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 78 | const u16 port = SIO_PORT; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 79 | const u16 runtime_port = 0x180; |
| 80 | |
| 81 | /* Turn on configuration mode. */ |
| 82 | outb(0x55, port); |
| 83 | |
| 84 | /* Set the GPIO direction, polarity, and type. */ |
| 85 | sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); |
| 86 | sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); |
| 87 | sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); |
| 88 | |
| 89 | /* Set the base address for the runtime register block. */ |
| 90 | sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); |
| 91 | sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); |
| 92 | |
| 93 | /* Turn on address decoding for it. */ |
| 94 | sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); |
| 95 | |
| 96 | /* Set the value of GPIO 10 by changing GP1, bit 0. */ |
| 97 | u8 byte; |
| 98 | byte = inb(runtime_port + 0xc); |
| 99 | byte |= (1 << 0); |
| 100 | outb(byte, runtime_port + 0xc); |
| 101 | |
| 102 | /* Turn off address decoding for it. */ |
| 103 | sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); |
| 104 | |
| 105 | /* Turn off configuration mode. */ |
| 106 | outb(0xaa, port); |
| 107 | } |
| 108 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 109 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 110 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 111 | struct pei_data pei_data_template = { |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 112 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 113 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 114 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 115 | .epbar = DEFAULT_EPBAR, |
| 116 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 117 | .smbusbar = SMBUS_IO_BASE, |
| 118 | .wdbbar = 0x4000000, |
| 119 | .wdbsize = 0x1000, |
| 120 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 121 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 122 | .pmbase = DEFAULT_PMBASE, |
| 123 | .gpiobase = DEFAULT_GPIOBASE, |
| 124 | .thermalbase = 0xfed08000, |
| 125 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 126 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 127 | .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, |
| 128 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 129 | .ec_present = 0, |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 130 | // 0 = leave channel enabled |
| 131 | // 1 = disable dimm 0 on channel |
| 132 | // 2 = disable dimm 1 on channel |
| 133 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 134 | .dimm_channel0_disabled = 2, |
| 135 | .dimm_channel1_disabled = 2, |
| 136 | .max_ddr3_freq = 1600, |
| 137 | .usb_port_config = { |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 138 | { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ |
| 139 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 140 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 141 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 142 | { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ |
| 143 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 144 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 145 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 146 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 147 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 148 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 149 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 150 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 151 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 152 | }, |
| 153 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 154 | *pei_data = pei_data_template; |
| 155 | } |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 156 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 157 | void mainboard_early_init(int s3resume) |
| 158 | { |
| 159 | } |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 160 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 161 | int mainboard_should_reset_usb(int s3resume) |
| 162 | { |
| 163 | return !s3resume; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 164 | } |