Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/io.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 26 | #include <device/pci_def.h> |
| 27 | #include <device/pnp_def.h> |
| 28 | #include <cpu/x86/lapic.h> |
| 29 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 30 | #include <arch/acpi.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 31 | #include <cbmem.h> |
| 32 | #include <console/console.h> |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame^] | 33 | #include <superio/smsc/sio1007/chip.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 34 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 35 | #include "northbridge/intel/sandybridge/raminit.h" |
| 36 | #include "southbridge/intel/bd82x6x/pch.h" |
| 37 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 38 | #include <arch/cpu.h> |
| 39 | #include <cpu/x86/bist.h> |
| 40 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 41 | #include <halt.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 42 | #include "gpio.h" |
| 43 | #if CONFIG_CHROMEOS |
| 44 | #include <vendorcode/google/chromeos/chromeos.h> |
| 45 | #endif |
| 46 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 47 | #define SIO_PORT 0x164e |
| 48 | |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 49 | static void pch_enable_lpc(void) |
| 50 | { |
| 51 | device_t dev = PCH_LPC_DEV; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 52 | |
| 53 | /* Set COM1/COM2 decode range */ |
| 54 | pci_write_config16(dev, LPC_IO_DEC, 0x0010); |
| 55 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 56 | /* Enable SuperIO + PS/2 Keyboard/Mouse */ |
| 57 | u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 58 | pci_write_config16(dev, LPC_EN, lpc_config); |
| 59 | |
| 60 | /* Map 256 bytes at 0x1600 to the LPC bus. */ |
| 61 | pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); |
| 62 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 63 | /* Map a range for the runtime_port registers to the LPC bus. */ |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 64 | pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); |
| 65 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 66 | /* Enable COM1 */ |
| 67 | if (sio1007_enable_uart_at(SIO_PORT)) { |
| 68 | pci_write_config16(dev, LPC_EN, |
| 69 | lpc_config | COMA_LPC_EN); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 70 | } |
| 71 | } |
| 72 | |
| 73 | static void rcba_config(void) |
| 74 | { |
| 75 | u32 reg32; |
| 76 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 77 | southbridge_configure_default_intmap(); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 78 | |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 79 | /* Disable unused devices (board specific) */ |
| 80 | reg32 = RCBA32(FD); |
| 81 | reg32 |= PCH_DISABLE_ALWAYS; |
| 82 | RCBA32(FD) = reg32; |
| 83 | } |
| 84 | |
| 85 | // FIXME, this function is generic code that should go to sb/... or |
| 86 | // nb/../early_init.c |
| 87 | static void early_pch_init(void) |
| 88 | { |
| 89 | u8 reg8; |
| 90 | |
| 91 | // reset rtc power status |
| 92 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 93 | reg8 &= ~(1 << 2); |
| 94 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | static void setup_sio_gpios(void) |
| 98 | { |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 99 | const u16 port = SIO_PORT; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 100 | const u16 runtime_port = 0x180; |
| 101 | |
| 102 | /* Turn on configuration mode. */ |
| 103 | outb(0x55, port); |
| 104 | |
| 105 | /* Set the GPIO direction, polarity, and type. */ |
| 106 | sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); |
| 107 | sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); |
| 108 | sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); |
| 109 | |
| 110 | /* Set the base address for the runtime register block. */ |
| 111 | sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); |
| 112 | sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); |
| 113 | |
| 114 | /* Turn on address decoding for it. */ |
| 115 | sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); |
| 116 | |
| 117 | /* Set the value of GPIO 10 by changing GP1, bit 0. */ |
| 118 | u8 byte; |
| 119 | byte = inb(runtime_port + 0xc); |
| 120 | byte |= (1 << 0); |
| 121 | outb(byte, runtime_port + 0xc); |
| 122 | |
| 123 | /* Turn off address decoding for it. */ |
| 124 | sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); |
| 125 | |
| 126 | /* Turn off configuration mode. */ |
| 127 | outb(0xaa, port); |
| 128 | } |
| 129 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 130 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 131 | void main(unsigned long bist) |
| 132 | { |
| 133 | int boot_mode = 0; |
| 134 | int cbmem_was_initted; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 135 | |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 136 | struct pei_data pei_data = { |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 137 | .pei_version = PEI_VERSION, |
| 138 | .mchbar = DEFAULT_MCHBAR, |
| 139 | .dmibar = DEFAULT_DMIBAR, |
| 140 | .epbar = DEFAULT_EPBAR, |
| 141 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 142 | .smbusbar = SMBUS_IO_BASE, |
| 143 | .wdbbar = 0x4000000, |
| 144 | .wdbsize = 0x1000, |
| 145 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 146 | .rcba = DEFAULT_RCBABASE, |
| 147 | .pmbase = DEFAULT_PMBASE, |
| 148 | .gpiobase = DEFAULT_GPIOBASE, |
| 149 | .thermalbase = 0xfed08000, |
| 150 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 151 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 152 | .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, |
| 153 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 154 | .ec_present = 0, |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 155 | // 0 = leave channel enabled |
| 156 | // 1 = disable dimm 0 on channel |
| 157 | // 2 = disable dimm 1 on channel |
| 158 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 159 | .dimm_channel0_disabled = 2, |
| 160 | .dimm_channel1_disabled = 2, |
| 161 | .max_ddr3_freq = 1600, |
| 162 | .usb_port_config = { |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 163 | { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ |
| 164 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 165 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 166 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 167 | { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ |
| 168 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 169 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 170 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 171 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 172 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 173 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 174 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 175 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 176 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 177 | }, |
| 178 | }; |
| 179 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 180 | timestamp_init(get_initial_timestamp()); |
| 181 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 182 | |
| 183 | if (bist == 0) |
| 184 | enable_lapic(); |
| 185 | |
| 186 | pch_enable_lpc(); |
| 187 | |
| 188 | /* Enable GPIOs */ |
| 189 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 190 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
Gabe Black | 599e204 | 2012-03-30 14:33:02 -0700 | [diff] [blame] | 191 | setup_pch_gpios(&emeraldlake2_gpio_map); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 192 | setup_sio_gpios(); |
| 193 | |
| 194 | /* Early SuperIO setup */ |
| 195 | console_init(); |
| 196 | |
| 197 | /* Halt if there was a built in self test failure */ |
| 198 | report_bist_failure(bist); |
| 199 | |
| 200 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 201 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 202 | boot_mode = 1; |
| 203 | |
| 204 | /* System is not happy after keyboard reset... */ |
| 205 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 206 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 207 | halt(); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /* Perform some early chipset initialization required |
| 211 | * before RAM initialization can work |
| 212 | */ |
| 213 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 214 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 215 | |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 216 | boot_mode = southbridge_detect_s3_resume() ? 2 : 0; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 217 | |
| 218 | post_code(0x38); |
| 219 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 220 | enable_smbus(); |
| 221 | |
| 222 | /* Prepare USB controller early in S3 resume */ |
| 223 | if (boot_mode == 2) |
| 224 | enable_usb_bar(); |
| 225 | |
| 226 | post_code(0x3a); |
| 227 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 228 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 229 | sdram_initialize(&pei_data); |
| 230 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 231 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 232 | post_code(0x3b); |
| 233 | /* Perform some initialization that must run before stage2 */ |
| 234 | early_pch_init(); |
| 235 | post_code(0x3c); |
| 236 | |
| 237 | /* This should probably go away. Until now it is required |
| 238 | * and mainboard specific |
| 239 | */ |
| 240 | rcba_config(); |
| 241 | post_code(0x3d); |
| 242 | |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 243 | quick_ram_check(); |
Stefan Reinauer | afcaac2 | 2012-06-18 15:43:50 -0700 | [diff] [blame] | 244 | post_code(0x3e); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 245 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 246 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 247 | if (boot_mode!=2) |
| 248 | save_mrc_data(&pei_data); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 249 | |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 250 | if (boot_mode==2 && !cbmem_was_initted) { |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 251 | /* Failed S3 resume, reset to come up cleanly */ |
| 252 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 253 | halt(); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 254 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 255 | northbridge_romstage_finalize(boot_mode==2); |
| 256 | |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 257 | post_code(0x3f); |
| 258 | #if CONFIG_CHROMEOS |
| 259 | init_chromeos(boot_mode); |
| 260 | #endif |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 261 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 262 | } |