Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; version 2 of the License. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
| 16 | ## You should have received a copy of the GNU General Public License |
| 17 | ## along with this program; if not, write to the Free Software |
| 18 | ## Foundation, Inc. |
| 19 | ## |
| 20 | |
| 21 | config HAVE_INTEL_FIRMWARE |
| 22 | bool |
| 23 | help |
| 24 | Chipset uses the Intel Firmware Descriptor to describe the |
| 25 | layout of the SPI ROM chip. |
| 26 | |
| 27 | if HAVE_INTEL_FIRMWARE |
| 28 | |
| 29 | comment "Intel Firmware" |
| 30 | |
| 31 | config HAVE_IFD_BIN |
| 32 | bool "Add Intel descriptor.bin file" |
| 33 | help |
| 34 | The descriptor binary |
| 35 | |
| 36 | config IFD_BIN_PATH |
| 37 | string "Path and filename of the descriptor.bin file" |
Stefan Reinauer | cecabc1 | 2015-07-01 17:37:57 -0700 | [diff] [blame^] | 38 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 39 | depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD |
| 40 | |
| 41 | config HAVE_ME_BIN |
Martin Roth | c407cb9 | 2015-06-23 19:59:30 -0600 | [diff] [blame] | 42 | bool "Add Intel ME/TXE firmware" |
Martin Roth | c528c2e | 2015-06-27 08:59:10 -0600 | [diff] [blame] | 43 | depends on HAVE_IFD_BIN |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 44 | help |
| 45 | The Intel processor in the selected system requires a special firmware |
Martin Roth | c407cb9 | 2015-06-23 19:59:30 -0600 | [diff] [blame] | 46 | for an integrated controller. This might be called the Management |
| 47 | Engine (ME), the Trusted Execution Engine (TXE) or something else |
| 48 | depending on the chip. This firmware might or might not be available |
| 49 | in coreboot's 3rdparty/blobs repository. If it is not and if you don't |
| 50 | have access to the firmware from elsewhere, you can still build |
| 51 | coreboot without it. In this case however, you'll have to make sure |
| 52 | that you don't overwrite your ME/TXE firmware on your flash ROM. |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 53 | |
| 54 | config ME_BIN_PATH |
| 55 | string "Path to management engine firmware" |
Stefan Reinauer | cecabc1 | 2015-07-01 17:37:57 -0700 | [diff] [blame^] | 56 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 57 | depends on HAVE_ME_BIN |
| 58 | |
| 59 | ##### Fake IFD ##### |
| 60 | |
| 61 | config BUILD_WITH_FAKE_IFD |
| 62 | bool "Build with a fake IFD" if !HAVE_IFD_BIN |
| 63 | help |
| 64 | If you don't have an Intel Firmware Descriptor (descriptor.bin) for your |
| 65 | board, you can select this option and coreboot will build without it. |
| 66 | The resulting coreboot.rom will not contain all parts required |
| 67 | to get coreboot running on your board. You can however write only the |
| 68 | BIOS section to your board's flash ROM and keep the other sections |
| 69 | untouched. Unfortunately the current version of flashrom doesn't |
| 70 | support this yet. But there is a patch pending [1]. |
| 71 | |
| 72 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 73 | was built with a fake IFD. It just won't work. |
| 74 | |
| 75 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 76 | |
| 77 | config IFD_BIOS_SECTION |
| 78 | depends on BUILD_WITH_FAKE_IFD |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 79 | string "BIOS Region Starting:Ending addresses within the ROM" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 80 | default "" |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 81 | help |
| 82 | The BIOS region is typically the size of the CBFS area, and is located |
| 83 | at the end of the ROM space. |
| 84 | |
| 85 | For an 8MB ROM with a 3MB CBFS area, this would look like: |
| 86 | 0x00500000:0x007fffff |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 87 | |
| 88 | config IFD_ME_SECTION |
| 89 | depends on BUILD_WITH_FAKE_IFD |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 90 | string "ME/TXE Region Starting:Ending addresses within the ROM" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 91 | default "" |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 92 | help |
| 93 | The ME/TXE region typically starts at around 0x1000 and often fills the |
| 94 | ROM space not used by CBFS. |
| 95 | |
| 96 | For an 8MB ROM with a 3MB CBFS area, this might look like: |
| 97 | 0x00001000:0x004fffff |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 98 | |
| 99 | config IFD_GBE_SECTION |
| 100 | depends on BUILD_WITH_FAKE_IFD |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 101 | string "GBE Region Starting:Ending addresses within the ROM" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 102 | default "" |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 103 | help |
| 104 | The Gigabit Ethernet ROM region is used when an Intel NIC is built into |
| 105 | the Southbridge/SOC and the platform uses this device instead of an external |
| 106 | PCIe NIC. It will be located between the ME/TXE and the BIOS region. |
| 107 | |
| 108 | Leave this empty if you're unsure. |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 109 | |
| 110 | config IFD_PLATFORM_SECTION |
| 111 | depends on BUILD_WITH_FAKE_IFD |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 112 | string "Platform Region Starting:Ending addresses within the Rom" |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 113 | default "" |
Martin Roth | 57eff2a | 2015-06-23 21:49:56 -0600 | [diff] [blame] | 114 | help |
| 115 | The Platform region is used for platform specific data. |
| 116 | It will be located between the ME/TXE and the BIOS region. |
| 117 | |
| 118 | Leave this empty if you're unsure. |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 119 | |
Martin Roth | 775d508 | 2015-06-23 21:47:19 -0600 | [diff] [blame] | 120 | config LOCK_MANAGEMENT_ENGINE |
| 121 | bool "Lock ME/TXE section" |
| 122 | depends on HAVE_ME_BIN |
| 123 | default n |
| 124 | help |
| 125 | The Intel Firmware Descriptor supports preventing write accesses |
| 126 | from the host to the ME or TXE section in the firmware |
| 127 | descriptor. If the section is locked, it can only be overwritten |
| 128 | with an external SPI flash programmer. You will want this if you |
| 129 | want to increase security of your ROM image once you are sure |
| 130 | that the ME/TXE firmware is no longer going to change. |
| 131 | |
| 132 | If unsure, say N. |
| 133 | |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 134 | endif #INTEL_FIRMWARE |