Angel Pons | c74dae9 | 2020-04-02 23:48:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Kyösti Mälkki | 94ce79d | 2019-12-16 17:21:13 +0200 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 5 | #include <delay.h> |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
Nico Huber | bba9735 | 2022-08-05 13:09:25 +0200 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 10 | #include <device/pciexp.h> |
| 11 | |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 12 | static unsigned int ext_cap_id(unsigned int cap) |
| 13 | { |
| 14 | return cap & 0xffff; |
| 15 | } |
| 16 | |
| 17 | static unsigned int ext_cap_next_offset(unsigned int cap) |
| 18 | { |
Nico Huber | 5f7cfb3 | 2022-08-05 14:50:06 +0200 | [diff] [blame] | 19 | return cap >> 20 & 0xffc; |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | static unsigned int find_ext_cap_offset(const struct device *dev, unsigned int cap_id, |
| 23 | unsigned int offset) |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 24 | { |
Tim Wawrzynczak | 3d121ae1 | 2021-09-16 20:18:16 -0600 | [diff] [blame] | 25 | unsigned int this_cap_offset = offset; |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 26 | |
Nico Huber | 5f7cfb3 | 2022-08-05 14:50:06 +0200 | [diff] [blame] | 27 | while (this_cap_offset >= PCIE_EXT_CAP_OFFSET) { |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 28 | const unsigned int this_cap = pci_read_config32(dev, this_cap_offset); |
| 29 | |
Bill XIE | 385e432 | 2022-08-04 21:52:05 +0800 | [diff] [blame] | 30 | /* Bail out when this request is unsupported */ |
| 31 | if (this_cap == 0xffffffff) |
| 32 | break; |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 33 | |
| 34 | if (ext_cap_id(this_cap) == cap_id) |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 35 | return this_cap_offset; |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 36 | |
| 37 | this_cap_offset = ext_cap_next_offset(this_cap); |
Nico Huber | 4b864e5 | 2022-08-05 12:44:11 +0200 | [diff] [blame] | 38 | } |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 39 | |
| 40 | return 0; |
| 41 | } |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 42 | |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 43 | /* |
| 44 | * Search for an extended capability with the ID `cap`. |
| 45 | * |
| 46 | * Returns the offset of the first matching extended |
| 47 | * capability if found, or 0 otherwise. |
| 48 | * |
| 49 | * A new search is started with `offset == 0`. |
| 50 | * To continue a search, the prior return value |
| 51 | * should be passed as `offset`. |
| 52 | */ |
| 53 | unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap, |
| 54 | unsigned int offset) |
Tim Wawrzynczak | 3d121ae1 | 2021-09-16 20:18:16 -0600 | [diff] [blame] | 55 | { |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 56 | unsigned int next_cap_offset; |
| 57 | |
| 58 | if (offset) |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 59 | next_cap_offset = ext_cap_next_offset(pci_read_config32(dev, offset)); |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 60 | else |
| 61 | next_cap_offset = PCIE_EXT_CAP_OFFSET; |
| 62 | |
Nico Huber | 077dc2e | 2022-08-05 14:47:35 +0200 | [diff] [blame] | 63 | return find_ext_cap_offset(dev, cap, next_cap_offset); |
Tim Wawrzynczak | 3d121ae1 | 2021-09-16 20:18:16 -0600 | [diff] [blame] | 64 | } |
| 65 | |
Nico Huber | 9099fea | 2022-08-05 13:02:52 +0200 | [diff] [blame] | 66 | /* |
| 67 | * Search for a vendor-specific extended capability, |
| 68 | * with the vendor-specific ID `cap`. |
| 69 | * |
| 70 | * Returns the offset of the vendor-specific header, |
| 71 | * i.e. the offset of the extended capability + 4, |
| 72 | * or 0 if none is found. |
| 73 | * |
| 74 | * A new search is started with `offset == 0`. |
| 75 | * To continue a search, the prior return value |
| 76 | * should be passed as `offset`. |
| 77 | */ |
| 78 | unsigned int pciexp_find_ext_vendor_cap(const struct device *dev, unsigned int cap, |
| 79 | unsigned int offset) |
| 80 | { |
| 81 | /* Reconstruct capability offset from vendor-specific header offset. */ |
| 82 | if (offset >= 4) |
| 83 | offset -= 4; |
| 84 | |
| 85 | for (;;) { |
| 86 | offset = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_VNDR, offset); |
| 87 | if (!offset) |
| 88 | return 0; |
| 89 | |
| 90 | const unsigned int vndr_cap = pci_read_config32(dev, offset + 4); |
| 91 | if ((vndr_cap & 0xffff) == cap) |
| 92 | return offset + 4; |
| 93 | } |
| 94 | } |
Tim Wawrzynczak | 3d121ae1 | 2021-09-16 20:18:16 -0600 | [diff] [blame] | 95 | |
Jonathan Zhang | 1864f12 | 2022-10-10 16:27:48 -0700 | [diff] [blame] | 96 | /** |
| 97 | * Find a PCIe device with a given serial number, and a given VID if applicable |
| 98 | * |
| 99 | * @param serial The serial number of the device. |
| 100 | * @param vid Vendor ID of the device, may be 0 if not applicable. |
| 101 | * @param from Pointer to the device structure, used as a starting point in |
| 102 | * the linked list of all_devices, which can be 0 to start at the |
| 103 | * head of the list (i.e. all_devices). |
| 104 | * @return Pointer to the device struct. |
| 105 | */ |
| 106 | struct device *pcie_find_dsn(const uint64_t serial, const uint16_t vid, |
| 107 | struct device *from) |
| 108 | { |
| 109 | union dsn { |
| 110 | struct { |
| 111 | uint32_t dsn_low; |
| 112 | uint32_t dsn_high; |
| 113 | }; |
| 114 | uint64_t dsn; |
| 115 | } dsn; |
| 116 | unsigned int cap; |
| 117 | uint16_t vendor_id; |
| 118 | |
| 119 | if (!from) |
| 120 | from = all_devices; |
| 121 | else |
| 122 | from = from->next; |
| 123 | |
| 124 | while (from) { |
| 125 | if (from->path.type == DEVICE_PATH_PCI) { |
| 126 | cap = pciexp_find_extended_cap(from, PCI_EXT_CAP_ID_DSN, 0); |
| 127 | /* |
| 128 | * For PCIe device, find extended capability for serial number. |
| 129 | * The capability header is 4 bytes, followed by lower 4 bytes |
| 130 | * of serial number, then higher 4 byes of serial number. |
| 131 | */ |
| 132 | if (cap != 0) { |
| 133 | dsn.dsn_low = pci_read_config32(from, cap + 4); |
| 134 | dsn.dsn_high = pci_read_config32(from, cap + 8); |
| 135 | vendor_id = pci_read_config16(from, PCI_VENDOR_ID); |
| 136 | if ((dsn.dsn == serial) && (vid == 0 || vendor_id == vid)) |
| 137 | return from; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | from = from->next; |
| 142 | } |
| 143 | |
| 144 | return from; |
| 145 | } |
| 146 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 147 | /* |
| 148 | * Re-train a PCIe link |
| 149 | */ |
| 150 | #define PCIE_TRAIN_RETRY 10000 |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 151 | static int pciexp_retrain_link(struct device *dev, unsigned int cap) |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 152 | { |
Youness Alaoui | bb5fb64 | 2017-05-03 17:57:13 -0400 | [diff] [blame] | 153 | unsigned int try; |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 154 | u16 lnk; |
| 155 | |
Youness Alaoui | bb5fb64 | 2017-05-03 17:57:13 -0400 | [diff] [blame] | 156 | /* |
| 157 | * Implementation note (page 633) in PCIe Specification 3.0 suggests |
| 158 | * polling the Link Training bit in the Link Status register until the |
| 159 | * value returned is 0 before setting the Retrain Link bit to 1. |
| 160 | * This is meant to avoid a race condition when using the |
| 161 | * Retrain Link mechanism. |
| 162 | */ |
| 163 | for (try = PCIE_TRAIN_RETRY; try > 0; try--) { |
| 164 | lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); |
| 165 | if (!(lnk & PCI_EXP_LNKSTA_LT)) |
| 166 | break; |
| 167 | udelay(100); |
| 168 | } |
| 169 | if (try == 0) { |
| 170 | printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev)); |
| 171 | return -1; |
| 172 | } |
| 173 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 174 | /* Start link retraining */ |
| 175 | lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL); |
| 176 | lnk |= PCI_EXP_LNKCTL_RL; |
| 177 | pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk); |
| 178 | |
| 179 | /* Wait for training to complete */ |
Youness Alaoui | bb5fb64 | 2017-05-03 17:57:13 -0400 | [diff] [blame] | 180 | for (try = PCIE_TRAIN_RETRY; try > 0; try--) { |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 181 | lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); |
| 182 | if (!(lnk & PCI_EXP_LNKSTA_LT)) |
| 183 | return 0; |
| 184 | udelay(100); |
| 185 | } |
| 186 | |
| 187 | printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev)); |
| 188 | return -1; |
| 189 | } |
| 190 | |
Werner Zeh | c83c958 | 2023-02-27 07:08:59 +0100 | [diff] [blame] | 191 | static bool pciexp_is_ccc_active(struct device *root, unsigned int root_cap, |
| 192 | struct device *endp, unsigned int endp_cap) |
| 193 | { |
| 194 | u16 root_ccc, endp_ccc; |
| 195 | |
| 196 | root_ccc = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_CCC; |
| 197 | endp_ccc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_CCC; |
| 198 | if (root_ccc && endp_ccc) { |
| 199 | printk(BIOS_INFO, "PCIe: Common Clock Configuration already enabled\n"); |
| 200 | return true; |
| 201 | } |
| 202 | return false; |
| 203 | } |
| 204 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 205 | /* |
| 206 | * Check the Slot Clock Configuration for root port and endpoint |
| 207 | * and enable Common Clock Configuration if possible. If CCC is |
| 208 | * enabled the link must be retrained. |
| 209 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 210 | static void pciexp_enable_common_clock(struct device *root, unsigned int root_cap, |
| 211 | struct device *endp, unsigned int endp_cap) |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 212 | { |
| 213 | u16 root_scc, endp_scc, lnkctl; |
| 214 | |
Werner Zeh | c83c958 | 2023-02-27 07:08:59 +0100 | [diff] [blame] | 215 | /* No need to enable common clock if it is already active. */ |
| 216 | if (pciexp_is_ccc_active(root, root_cap, endp, endp_cap)) |
| 217 | return; |
| 218 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 219 | /* Get Slot Clock Configuration for root port */ |
| 220 | root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA); |
| 221 | root_scc &= PCI_EXP_LNKSTA_SLC; |
| 222 | |
| 223 | /* Get Slot Clock Configuration for endpoint */ |
| 224 | endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA); |
| 225 | endp_scc &= PCI_EXP_LNKSTA_SLC; |
| 226 | |
| 227 | /* Enable Common Clock Configuration and retrain */ |
| 228 | if (root_scc && endp_scc) { |
| 229 | printk(BIOS_INFO, "Enabling Common Clock Configuration\n"); |
| 230 | |
| 231 | /* Set in endpoint */ |
| 232 | lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); |
| 233 | lnkctl |= PCI_EXP_LNKCTL_CCC; |
| 234 | pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); |
| 235 | |
| 236 | /* Set in root port */ |
| 237 | lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); |
| 238 | lnkctl |= PCI_EXP_LNKCTL_CCC; |
| 239 | pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); |
| 240 | |
| 241 | /* Retrain link if CCC was enabled */ |
| 242 | pciexp_retrain_link(root, root_cap); |
| 243 | } |
| 244 | } |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 245 | |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 246 | static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap) |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 247 | { |
Martin Roth | 74f1877 | 2023-09-03 21:38:29 -0600 | [diff] [blame] | 248 | /* check if per port clkreq is supported in device */ |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 249 | u32 endp_ca; |
| 250 | u16 lnkctl; |
| 251 | endp_ca = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); |
| 252 | if ((endp_ca & PCI_EXP_CLK_PM) == 0) { |
Arthur Heymans | 330c46b | 2017-07-12 19:17:56 +0200 | [diff] [blame] | 253 | printk(BIOS_INFO, "PCIE CLK PM is not supported by endpoint\n"); |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 254 | return; |
| 255 | } |
| 256 | lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); |
| 257 | lnkctl = lnkctl | PCI_EXP_EN_CLK_PM; |
| 258 | pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); |
| 259 | } |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 260 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 261 | static bool _pciexp_ltr_supported(struct device *dev, unsigned int cap) |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 262 | { |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 263 | return pci_read_config16(dev, cap + PCI_EXP_DEVCAP2) & PCI_EXP_DEVCAP2_LTR; |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 264 | } |
| 265 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 266 | static bool _pciexp_ltr_enabled(struct device *dev, unsigned int cap) |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 267 | { |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 268 | return pci_read_config16(dev, cap + PCI_EXP_DEVCTL2) & PCI_EXP_DEV2_LTR; |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 269 | } |
| 270 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 271 | static bool _pciexp_enable_ltr(struct device *parent, unsigned int parent_cap, |
| 272 | struct device *dev, unsigned int cap) |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 273 | { |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 274 | if (!_pciexp_ltr_supported(dev, cap)) { |
| 275 | printk(BIOS_DEBUG, "%s: No LTR support\n", dev_path(dev)); |
| 276 | return false; |
Pratik Prajapati | 0cd0d28 | 2015-06-09 12:06:20 -0700 | [diff] [blame] | 277 | } |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 278 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 279 | if (_pciexp_ltr_enabled(dev, cap)) |
| 280 | return true; |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 281 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 282 | if (parent && |
Nico Huber | 49fc4e3 | 2022-08-17 21:57:46 +0200 | [diff] [blame] | 283 | (!_pciexp_ltr_supported(parent, parent_cap) || |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 284 | !_pciexp_ltr_enabled(parent, parent_cap))) |
| 285 | return false; |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 286 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 287 | pci_or_config16(dev, cap + PCI_EXP_DEVCTL2, PCI_EXP_DEV2_LTR); |
| 288 | printk(BIOS_INFO, "%s: Enabled LTR\n", dev_path(dev)); |
| 289 | return true; |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 290 | } |
| 291 | |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 292 | static void pciexp_enable_ltr(struct device *dev) |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 293 | { |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 294 | const unsigned int cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 295 | if (!cap) |
| 296 | return; |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 297 | |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 298 | /* |
| 299 | * If we have get_ltr_max_latencies(), treat `dev` as the root. |
| 300 | * If not, let _pciexp_enable_ltr() query the parent's state. |
| 301 | */ |
| 302 | struct device *parent = NULL; |
| 303 | unsigned int parent_cap = 0; |
| 304 | if (!dev->ops->ops_pci || !dev->ops->ops_pci->get_ltr_max_latencies) { |
| 305 | parent = dev->bus->dev; |
Nico Huber | 49fc4e3 | 2022-08-17 21:57:46 +0200 | [diff] [blame] | 306 | if (parent->path.type != DEVICE_PATH_PCI) |
| 307 | return; |
Bill XIE | a43380e | 2022-08-03 00:18:14 +0800 | [diff] [blame] | 308 | parent_cap = pci_find_capability(parent, PCI_CAP_ID_PCIE); |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 309 | if (!parent_cap) |
| 310 | return; |
Aamir Bohra | 2188f57 | 2017-09-22 19:07:21 +0530 | [diff] [blame] | 311 | } |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 312 | |
| 313 | (void)_pciexp_enable_ltr(parent, parent_cap, dev, cap); |
| 314 | } |
| 315 | |
Tim Wawrzynczak | a62cb56 | 2021-12-08 21:16:43 -0700 | [diff] [blame] | 316 | bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop) |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 317 | { |
| 318 | /* Walk the hierarchy up to find get_ltr_max_latencies(). */ |
| 319 | do { |
| 320 | if (dev->ops->ops_pci && dev->ops->ops_pci->get_ltr_max_latencies) |
| 321 | break; |
| 322 | if (dev->bus->dev == dev || dev->bus->dev->path.type != DEVICE_PATH_PCI) |
| 323 | return false; |
| 324 | dev = dev->bus->dev; |
| 325 | } while (true); |
| 326 | |
| 327 | dev->ops->ops_pci->get_ltr_max_latencies(max_snoop, max_nosnoop); |
| 328 | return true; |
| 329 | } |
| 330 | |
| 331 | static void pciexp_configure_ltr(struct device *parent, unsigned int parent_cap, |
| 332 | struct device *dev, unsigned int cap) |
| 333 | { |
| 334 | if (!_pciexp_enable_ltr(parent, parent_cap, dev, cap)) |
| 335 | return; |
| 336 | |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 337 | const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID, 0); |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 338 | if (!ltr_cap) |
| 339 | return; |
| 340 | |
| 341 | u16 max_snoop, max_nosnoop; |
| 342 | if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop)) |
| 343 | return; |
| 344 | |
| 345 | pci_write_config16(dev, ltr_cap + PCI_LTR_MAX_SNOOP, max_snoop); |
| 346 | pci_write_config16(dev, ltr_cap + PCI_LTR_MAX_NOSNOOP, max_nosnoop); |
| 347 | printk(BIOS_INFO, "%s: Programmed LTR max latencies\n", dev_path(dev)); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 348 | } |
| 349 | |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 350 | static unsigned char pciexp_L1_substate_cal(struct device *dev, unsigned int endp_cap, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 351 | unsigned int *data) |
| 352 | { |
| 353 | unsigned char mult[4] = {2, 10, 100, 0}; |
| 354 | |
| 355 | unsigned int L1SubStateSupport = *data & 0xf; |
| 356 | unsigned int comm_mode_rst_time = (*data >> 8) & 0xff; |
| 357 | unsigned int power_on_scale = (*data >> 16) & 0x3; |
| 358 | unsigned int power_on_value = (*data >> 19) & 0x1f; |
| 359 | |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 360 | unsigned int endp_data = pci_read_config32(dev, endp_cap + 4); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 361 | unsigned int endp_L1SubStateSupport = endp_data & 0xf; |
| 362 | unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff; |
| 363 | unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3; |
| 364 | unsigned int endp_power_on_value = (endp_data >> 19) & 0x1f; |
| 365 | |
| 366 | L1SubStateSupport &= endp_L1SubStateSupport; |
| 367 | |
| 368 | if (L1SubStateSupport == 0) |
| 369 | return 0; |
| 370 | |
| 371 | if (power_on_value * mult[power_on_scale] < |
| 372 | endp_power_on_value * mult[endp_power_on_scale]) { |
| 373 | power_on_value = endp_power_on_value; |
| 374 | power_on_scale = endp_power_on_scale; |
| 375 | } |
| 376 | if (comm_mode_rst_time < endp_comm_mode_restore_time) |
| 377 | comm_mode_rst_time = endp_comm_mode_restore_time; |
| 378 | |
| 379 | *data = (comm_mode_rst_time << 8) | (power_on_scale << 16) |
| 380 | | (power_on_value << 19) | L1SubStateSupport; |
| 381 | |
| 382 | return 1; |
| 383 | } |
| 384 | |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 385 | static void pciexp_L1_substate_commit(struct device *root, struct device *dev, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 386 | unsigned int root_cap, unsigned int end_cap) |
| 387 | { |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 388 | struct device *dev_t; |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 389 | unsigned char L1_ss_ok; |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 390 | unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 391 | unsigned int L1SubStateSupport; |
| 392 | unsigned int comm_mode_rst_time; |
| 393 | unsigned int power_on_scale; |
| 394 | unsigned int endp_power_on_value; |
| 395 | |
| 396 | for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { |
| 397 | /* |
| 398 | * rp_L1_support is init'd above from root port. |
| 399 | * it needs coordination with endpoints to reach in common. |
| 400 | * if certain endpoint doesn't support L1 Sub-State, abort |
| 401 | * this feature enabling. |
| 402 | */ |
| 403 | L1_ss_ok = pciexp_L1_substate_cal(dev_t, end_cap, |
| 404 | &rp_L1_support); |
| 405 | if (!L1_ss_ok) |
| 406 | return; |
| 407 | } |
| 408 | |
| 409 | L1SubStateSupport = rp_L1_support & 0xf; |
| 410 | comm_mode_rst_time = (rp_L1_support >> 8) & 0xff; |
| 411 | power_on_scale = (rp_L1_support >> 16) & 0x3; |
| 412 | endp_power_on_value = (rp_L1_support >> 19) & 0x1f; |
| 413 | |
| 414 | printk(BIOS_INFO, "L1 Sub-State supported from root port %d\n", |
| 415 | root->path.pci.devfn >> 3); |
| 416 | printk(BIOS_INFO, "L1 Sub-State Support = 0x%x\n", L1SubStateSupport); |
| 417 | printk(BIOS_INFO, "CommonModeRestoreTime = 0x%x\n", comm_mode_rst_time); |
| 418 | printk(BIOS_INFO, "Power On Value = 0x%x, Power On Scale = 0x%x\n", |
| 419 | endp_power_on_value, power_on_scale); |
| 420 | |
Kyösti Mälkki | 48c389e | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 421 | pci_update_config32(root, root_cap + 0x08, ~0xff00, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 422 | (comm_mode_rst_time << 8)); |
| 423 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 424 | pci_update_config32(root, root_cap + 0x0c, 0xffffff04, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 425 | (endp_power_on_value << 3) | (power_on_scale)); |
| 426 | |
Patrick Georgi | 9adcbfe | 2017-12-05 16:36:30 -0500 | [diff] [blame] | 427 | /* TODO: 0xa0, 2 are values that work on some chipsets but really |
| 428 | * should be determined dynamically by looking at downstream devices. |
| 429 | */ |
| 430 | pci_update_config32(root, root_cap + 0x08, |
| 431 | ~(ASPM_LTR_L12_THRESHOLD_VALUE_MASK | |
| 432 | ASPM_LTR_L12_THRESHOLD_SCALE_MASK), |
| 433 | (0xa0 << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) | |
| 434 | (2 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 435 | |
Kyösti Mälkki | 48c389e | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 436 | pci_update_config32(root, root_cap + 0x08, ~0x1f, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 437 | L1SubStateSupport); |
| 438 | |
| 439 | for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 440 | pci_update_config32(dev_t, end_cap + 0x0c, 0xffffff04, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 441 | (endp_power_on_value << 3) | (power_on_scale)); |
| 442 | |
Patrick Georgi | 9adcbfe | 2017-12-05 16:36:30 -0500 | [diff] [blame] | 443 | pci_update_config32(dev_t, end_cap + 0x08, |
| 444 | ~(ASPM_LTR_L12_THRESHOLD_VALUE_MASK | |
| 445 | ASPM_LTR_L12_THRESHOLD_SCALE_MASK), |
| 446 | (0xa0 << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) | |
| 447 | (2 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 448 | |
Kyösti Mälkki | 48c389e | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 449 | pci_update_config32(dev_t, end_cap + 0x08, ~0x1f, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 450 | L1SubStateSupport); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 451 | } |
| 452 | } |
| 453 | |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 454 | static void pciexp_config_L1_sub_state(struct device *root, struct device *dev) |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 455 | { |
| 456 | unsigned int root_cap, end_cap; |
| 457 | |
| 458 | /* Do it for function 0 only */ |
| 459 | if (dev->path.pci.devfn & 0x7) |
| 460 | return; |
| 461 | |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 462 | root_cap = pciexp_find_extended_cap(root, PCIE_EXT_CAP_L1SS_ID, 0); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 463 | if (!root_cap) |
| 464 | return; |
| 465 | |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 466 | end_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_L1SS_ID, 0); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 467 | if (!end_cap) { |
Nico Huber | bba9735 | 2022-08-05 13:09:25 +0200 | [diff] [blame] | 468 | if (dev->vendor != PCI_VID_INTEL) |
| 469 | return; |
| 470 | |
| 471 | end_cap = pciexp_find_ext_vendor_cap(dev, 0xcafe, 0); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 472 | if (!end_cap) |
| 473 | return; |
| 474 | } |
| 475 | |
| 476 | pciexp_L1_substate_commit(root, dev, root_cap, end_cap); |
| 477 | } |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 478 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 479 | /* |
| 480 | * Determine the ASPM L0s or L1 exit latency for a link |
| 481 | * by checking both root port and endpoint and returning |
| 482 | * the highest latency value. |
| 483 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 484 | static int pciexp_aspm_latency(struct device *root, unsigned int root_cap, |
| 485 | struct device *endp, unsigned int endp_cap, |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 486 | enum aspm_type type) |
| 487 | { |
| 488 | int root_lat = 0, endp_lat = 0; |
| 489 | u32 root_lnkcap, endp_lnkcap; |
| 490 | |
| 491 | root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP); |
| 492 | endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); |
| 493 | |
| 494 | /* Make sure the link supports this ASPM type by checking |
| 495 | * capability bits 11:10 with aspm_type offset by 1 */ |
| 496 | if (!(root_lnkcap & (1 << (type + 9))) || |
| 497 | !(endp_lnkcap & (1 << (type + 9)))) |
| 498 | return -1; |
| 499 | |
| 500 | /* Find the one with higher latency */ |
| 501 | switch (type) { |
| 502 | case PCIE_ASPM_L0S: |
| 503 | root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; |
| 504 | endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; |
| 505 | break; |
| 506 | case PCIE_ASPM_L1: |
| 507 | root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; |
| 508 | endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; |
| 509 | break; |
| 510 | default: |
| 511 | return -1; |
| 512 | } |
| 513 | |
| 514 | return (endp_lat > root_lat) ? endp_lat : root_lat; |
| 515 | } |
| 516 | |
| 517 | /* |
| 518 | * Enable ASPM on PCIe root port and endpoint. |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 519 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 520 | static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, |
| 521 | struct device *endp, unsigned int endp_cap) |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 522 | { |
| 523 | const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; |
| 524 | enum aspm_type apmc = PCIE_ASPM_NONE; |
| 525 | int exit_latency, ok_latency; |
| 526 | u16 lnkctl; |
| 527 | u32 devcap; |
| 528 | |
Nico Huber | 570b183 | 2017-08-30 13:38:50 +0200 | [diff] [blame] | 529 | if (endp->disable_pcie_aspm) |
| 530 | return; |
| 531 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 532 | /* Get endpoint device capabilities for acceptable limits */ |
| 533 | devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); |
| 534 | |
| 535 | /* Enable L0s if it is within endpoint acceptable limit */ |
| 536 | ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; |
| 537 | exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, |
| 538 | PCIE_ASPM_L0S); |
| 539 | if (exit_latency >= 0 && exit_latency <= ok_latency) |
| 540 | apmc |= PCIE_ASPM_L0S; |
| 541 | |
| 542 | /* Enable L1 if it is within endpoint acceptable limit */ |
| 543 | ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9; |
| 544 | exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, |
| 545 | PCIE_ASPM_L1); |
| 546 | if (exit_latency >= 0 && exit_latency <= ok_latency) |
| 547 | apmc |= PCIE_ASPM_L1; |
| 548 | |
| 549 | if (apmc != PCIE_ASPM_NONE) { |
| 550 | /* Set APMC in root port first */ |
| 551 | lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); |
| 552 | lnkctl |= apmc; |
| 553 | pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); |
| 554 | |
| 555 | /* Set APMC in endpoint device next */ |
| 556 | lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); |
| 557 | lnkctl |= apmc; |
| 558 | pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); |
| 559 | } |
| 560 | |
| 561 | printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 562 | } |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 563 | |
Kyösti Mälkki | 94ce79d | 2019-12-16 17:21:13 +0200 | [diff] [blame] | 564 | /* |
| 565 | * Set max payload size of endpoint in accordance with max payload size of root port. |
| 566 | */ |
| 567 | static void pciexp_set_max_payload_size(struct device *root, unsigned int root_cap, |
| 568 | struct device *endp, unsigned int endp_cap) |
| 569 | { |
| 570 | unsigned int endp_max_payload, root_max_payload, max_payload; |
| 571 | u16 endp_devctl, root_devctl; |
| 572 | u32 endp_devcap, root_devcap; |
| 573 | |
| 574 | /* Get max payload size supported by endpoint */ |
| 575 | endp_devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); |
| 576 | endp_max_payload = endp_devcap & PCI_EXP_DEVCAP_PAYLOAD; |
| 577 | |
| 578 | /* Get max payload size supported by root port */ |
| 579 | root_devcap = pci_read_config32(root, root_cap + PCI_EXP_DEVCAP); |
| 580 | root_max_payload = root_devcap & PCI_EXP_DEVCAP_PAYLOAD; |
| 581 | |
| 582 | /* Set max payload to smaller of the reported device capability. */ |
| 583 | max_payload = MIN(endp_max_payload, root_max_payload); |
| 584 | if (max_payload > 5) { |
| 585 | /* Values 6 and 7 are reserved in PCIe 3.0 specs. */ |
| 586 | printk(BIOS_ERR, "PCIe: Max_Payload_Size field restricted from %d to 5\n", |
| 587 | max_payload); |
| 588 | max_payload = 5; |
| 589 | } |
| 590 | |
| 591 | endp_devctl = pci_read_config16(endp, endp_cap + PCI_EXP_DEVCTL); |
| 592 | endp_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; |
| 593 | endp_devctl |= max_payload << 5; |
| 594 | pci_write_config16(endp, endp_cap + PCI_EXP_DEVCTL, endp_devctl); |
| 595 | |
| 596 | root_devctl = pci_read_config16(root, root_cap + PCI_EXP_DEVCTL); |
| 597 | root_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; |
| 598 | root_devctl |= max_payload << 5; |
| 599 | pci_write_config16(root, root_cap + PCI_EXP_DEVCTL, root_devctl); |
| 600 | |
| 601 | printk(BIOS_INFO, "PCIe: Max_Payload_Size adjusted to %d\n", (1 << (max_payload + 7))); |
| 602 | } |
| 603 | |
Wilson Chou | c8a8695 | 2022-08-29 02:08:24 +0000 | [diff] [blame] | 604 | /* |
| 605 | * Clear Lane Error State at the end of PCIe link training. |
| 606 | * Lane error status is cleared if PCIEXP_LANE_ERR_STAT_CLEAR is set. |
| 607 | * Lane error is normal during link training, so we need to clear it. |
| 608 | * At this moment, link has been used, but for a very short duration. |
| 609 | */ |
| 610 | static void clear_lane_error_status(struct device *dev) |
| 611 | { |
| 612 | u32 reg32; |
| 613 | u16 pos; |
| 614 | |
| 615 | pos = pciexp_find_extended_cap(dev, PCI_EXP_SEC_CAP_ID, 0); |
| 616 | if (pos == 0) |
| 617 | return; |
| 618 | |
| 619 | reg32 = pci_read_config32(dev, pos + PCI_EXP_SEC_LANE_ERR_STATUS); |
| 620 | if (reg32 == 0) |
| 621 | return; |
| 622 | |
| 623 | printk(BIOS_DEBUG, "%s: Clear Lane Error Status.\n", dev_path(dev)); |
| 624 | printk(BIOS_DEBUG, "LaneErrStat:0x%x\n", reg32); |
| 625 | pci_write_config32(dev, pos + PCI_EXP_SEC_LANE_ERR_STATUS, reg32); |
| 626 | } |
| 627 | |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 628 | static void pciexp_tune_dev(struct device *dev) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 629 | { |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 630 | struct device *root = dev->bus->dev; |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 631 | unsigned int root_cap, cap; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 632 | |
| 633 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 634 | if (!cap) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 635 | return; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 636 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 637 | root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE); |
| 638 | if (!root_cap) |
| 639 | return; |
Stefan Reinauer | f6eb88a | 2010-01-17 13:54:08 +0000 | [diff] [blame] | 640 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 641 | /* Check for and enable Common Clock */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 642 | if (CONFIG(PCIEXP_COMMON_CLOCK)) |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 643 | pciexp_enable_common_clock(root, root_cap, dev, cap); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 644 | |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 645 | /* Check if per port CLK req is supported by endpoint*/ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 646 | if (CONFIG(PCIEXP_CLK_PM)) |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 647 | pciexp_enable_clock_power_pm(dev, cap); |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 648 | |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 649 | /* Enable L1 Sub-State when both root port and endpoint support */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 650 | if (CONFIG(PCIEXP_L1_SUB_STATE)) |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 651 | pciexp_config_L1_sub_state(root, dev); |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 652 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 653 | /* Check for and enable ASPM */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 654 | if (CONFIG(PCIEXP_ASPM)) |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 655 | pciexp_enable_aspm(root, root_cap, dev, cap); |
Kyösti Mälkki | 94ce79d | 2019-12-16 17:21:13 +0200 | [diff] [blame] | 656 | |
Wilson Chou | c8a8695 | 2022-08-29 02:08:24 +0000 | [diff] [blame] | 657 | /* Clear PCIe Lane Error Status */ |
| 658 | if (CONFIG(PCIEXP_LANE_ERR_STAT_CLEAR)) |
| 659 | clear_lane_error_status(root); |
| 660 | |
Kyösti Mälkki | 94ce79d | 2019-12-16 17:21:13 +0200 | [diff] [blame] | 661 | /* Adjust Max_Payload_Size of link ends. */ |
| 662 | pciexp_set_max_payload_size(root, root_cap, dev, cap); |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 663 | |
| 664 | pciexp_configure_ltr(root, root_cap, dev, cap); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 665 | } |
| 666 | |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 667 | void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, |
| 668 | unsigned int max_devfn) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 669 | { |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 670 | struct device *child; |
Nico Huber | 968ef75 | 2021-03-07 01:39:18 +0100 | [diff] [blame] | 671 | |
| 672 | pciexp_enable_ltr(bus->dev); |
| 673 | |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 674 | pci_scan_bus(bus, min_devfn, max_devfn); |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 675 | |
| 676 | for (child = bus->children; child; child = child->sibling) { |
Duncan Laurie | bf69622 | 2020-10-18 15:10:00 -0700 | [diff] [blame] | 677 | if (child->path.type != DEVICE_PATH_PCI) |
| 678 | continue; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 679 | if ((child->path.pci.devfn < min_devfn) || |
| 680 | (child->path.pci.devfn > max_devfn)) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 681 | continue; |
| 682 | } |
| 683 | pciexp_tune_dev(child); |
| 684 | } |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 685 | } |
| 686 | |
Elyes HAOUAS | b1fa287 | 2018-05-02 21:11:38 +0200 | [diff] [blame] | 687 | void pciexp_scan_bridge(struct device *dev) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 688 | { |
Kyösti Mälkki | 580e722 | 2015-03-19 21:04:23 +0200 | [diff] [blame] | 689 | do_pci_scan_bridge(dev, pciexp_scan_bus); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 690 | } |
| 691 | |
| 692 | /** Default device operations for PCI Express bridges */ |
| 693 | static struct pci_operations pciexp_bus_ops_pci = { |
| 694 | .set_subsystem = 0, |
| 695 | }; |
| 696 | |
| 697 | struct device_operations default_pciexp_ops_bus = { |
| 698 | .read_resources = pci_bus_read_resources, |
| 699 | .set_resources = pci_dev_set_resources, |
| 700 | .enable_resources = pci_bus_enable_resources, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 701 | .scan_bus = pciexp_scan_bridge, |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 702 | .reset_bus = pci_bus_reset, |
| 703 | .ops_pci = &pciexp_bus_ops_pci, |
| 704 | }; |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 705 | |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 706 | static void pciexp_hotplug_dummy_read_resources(struct device *dev) |
| 707 | { |
| 708 | struct resource *resource; |
| 709 | |
Furquan Shaikh | 32f385e | 2020-05-15 23:35:00 -0700 | [diff] [blame] | 710 | /* Add extra memory space */ |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 711 | resource = new_resource(dev, 0x10); |
| 712 | resource->size = CONFIG_PCIEXP_HOTPLUG_MEM; |
| 713 | resource->align = 12; |
| 714 | resource->gran = 12; |
| 715 | resource->limit = 0xffffffff; |
| 716 | resource->flags |= IORESOURCE_MEM; |
| 717 | |
Furquan Shaikh | 32f385e | 2020-05-15 23:35:00 -0700 | [diff] [blame] | 718 | /* Add extra prefetchable memory space */ |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 719 | resource = new_resource(dev, 0x14); |
| 720 | resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM; |
| 721 | resource->align = 12; |
| 722 | resource->gran = 12; |
| 723 | resource->limit = 0xffffffffffffffff; |
| 724 | resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 725 | |
Furquan Shaikh | 32f385e | 2020-05-15 23:35:00 -0700 | [diff] [blame] | 726 | /* Set resource flag requesting allocation above 4G boundary. */ |
| 727 | if (CONFIG(PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G)) |
| 728 | resource->flags |= IORESOURCE_ABOVE_4G; |
| 729 | |
| 730 | /* Add extra I/O space */ |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 731 | resource = new_resource(dev, 0x18); |
| 732 | resource->size = CONFIG_PCIEXP_HOTPLUG_IO; |
| 733 | resource->align = 12; |
| 734 | resource->gran = 12; |
| 735 | resource->limit = 0xffff; |
| 736 | resource->flags |= IORESOURCE_IO; |
| 737 | } |
| 738 | |
| 739 | static struct device_operations pciexp_hotplug_dummy_ops = { |
| 740 | .read_resources = pciexp_hotplug_dummy_read_resources, |
John Su | 3ecc777 | 2022-03-25 10:37:52 +0800 | [diff] [blame] | 741 | .set_resources = noop_set_resources, |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 742 | }; |
| 743 | |
| 744 | void pciexp_hotplug_scan_bridge(struct device *dev) |
| 745 | { |
Nico Huber | 577c6b9 | 2022-08-15 00:08:58 +0200 | [diff] [blame] | 746 | dev->hotplug_port = 1; |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 747 | dev->hotplug_buses = CONFIG_PCIEXP_HOTPLUG_BUSES; |
| 748 | |
| 749 | /* Normal PCIe Scan */ |
| 750 | pciexp_scan_bridge(dev); |
| 751 | |
| 752 | /* Add dummy slot to preserve resources, must happen after bus scan */ |
| 753 | struct device *dummy; |
| 754 | struct device_path dummy_path = { .type = DEVICE_PATH_NONE }; |
| 755 | dummy = alloc_dev(dev->link_list, &dummy_path); |
| 756 | dummy->ops = &pciexp_hotplug_dummy_ops; |
| 757 | } |
| 758 | |
| 759 | struct device_operations default_pciexp_hotplug_ops_bus = { |
| 760 | .read_resources = pci_bus_read_resources, |
| 761 | .set_resources = pci_dev_set_resources, |
| 762 | .enable_resources = pci_bus_enable_resources, |
| 763 | .scan_bus = pciexp_hotplug_scan_bridge, |
| 764 | .reset_bus = pci_bus_reset, |
| 765 | .ops_pci = &pciexp_bus_ops_pci, |
| 766 | }; |