Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #define ASSEMBLY 1 |
| 22 | #define __PRE_RAM__ |
| 23 | |
| 24 | //#define SYSTEM_TYPE 0 /* SERVER */ |
| 25 | #define SYSTEM_TYPE 1 /* DESKTOP */ |
| 26 | //#define SYSTEM_TYPE 2 /* MOBILE */ |
| 27 | |
| 28 | |
| 29 | #define RAMINIT_SYSINFO 1 |
| 30 | #define CACHE_AS_RAM_ADDRESS_DEBUG 1 |
| 31 | |
| 32 | #define SET_NB_CFG_54 1 |
| 33 | |
| 34 | //used by raminit |
| 35 | #define QRANK_DIMM_SUPPORT 1 |
| 36 | |
| 37 | //used by incoherent_ht |
| 38 | #define FAM10_SCAN_PCI_BUS 0 |
| 39 | #define FAM10_ALLOCATE_IO_RANGE 0 |
| 40 | |
| 41 | //used by init_cpus and fidvid |
| 42 | #define FAM10_SET_FIDVID 1 |
| 43 | #define FAM10_SET_FIDVID_CORE_RANGE 0 |
| 44 | |
| 45 | #include <stdint.h> |
| 46 | #include <string.h> |
| 47 | #include <device/pci_def.h> |
| 48 | #include <device/pci_ids.h> |
| 49 | #include <arch/io.h> |
| 50 | #include <device/pnp_def.h> |
| 51 | #include <arch/romcc_io.h> |
| 52 | #include <cpu/x86/lapic.h> |
| 53 | #include "option_table.h" |
| 54 | #include "pc80/mc146818rtc_early.c" |
| 55 | |
| 56 | /* FIXME: Use console.c post_code function */ |
| 57 | static void post_code(u8 value) { |
| 58 | outb(value, 0x80); |
| 59 | } |
| 60 | |
| 61 | #if (CONFIG_USE_FAILOVER_IMAGE == 0) |
| 62 | #include "arch/i386/lib/console.c" |
| 63 | #include "pc80/serial.c" |
| 64 | #include "lib/ramtest.c" |
| 65 | #include <cpu/amd/model_10xxx_rev.h> |
| 66 | #include "northbridge/amd/amdfam10/raminit.h" |
| 67 | #include "northbridge/amd/amdfam10/amdfam10.h" |
| 68 | #endif |
| 69 | |
| 70 | #include "cpu/x86/lapic/boot_cpu.c" |
| 71 | #include "northbridge/amd/amdfam10/reset_test.c" |
| 72 | |
| 73 | #include <console/loglevel.h> |
| 74 | #if 0 |
| 75 | void die(const char *msg); |
| 76 | int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); |
| 77 | #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) |
| 78 | #endif |
| 79 | #define printk_info(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) |
| 80 | #include "cpu/x86/bist.h" |
| 81 | |
| 82 | |
| 83 | #if (CONFIG_USE_FAILOVER_IMAGE == 0) |
| 84 | |
| 85 | static int smbus_read_byte(u32 device, u32 address); |
| 86 | |
| 87 | #include "superio/ite/it8718f/it8718f_early_serial.c" |
| 88 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 89 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
| 90 | |
| 91 | #include "southbridge/amd/rs780/rs780_early_setup.c" |
| 92 | #include "southbridge/amd/sb700/sb700_early_setup.c" |
| 93 | #include "northbridge/amd/amdfam10/debug.c" |
| 94 | |
| 95 | static void memreset_setup(void) |
| 96 | { |
| 97 | } |
| 98 | |
| 99 | |
| 100 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 101 | { |
| 102 | } |
| 103 | |
| 104 | |
| 105 | static void activate_spd_rom(const struct mem_controller *ctrl) |
| 106 | { |
| 107 | } |
| 108 | |
| 109 | |
| 110 | static int spd_read_byte(u32 device, u32 address) |
| 111 | { |
| 112 | int result; |
| 113 | result = smbus_read_byte(device, address); |
| 114 | return result; |
| 115 | } |
| 116 | |
| 117 | #include "northbridge/amd/amdfam10/amdfam10.h" |
| 118 | #include "northbridge/amd/amdht/ht_wrapper.c" |
| 119 | |
| 120 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
| 121 | #include "northbridge/amd/amdfam10/raminit_amdmct.c" |
| 122 | #include "northbridge/amd/amdfam10/amdfam10_pci.c" |
| 123 | |
| 124 | #include "resourcemap.c" |
| 125 | #include "cpu/amd/quadcore/quadcore.c" |
| 126 | #include "cpu/amd/car/copy_and_run.c" |
| 127 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 128 | #include "cpu/amd/model_10xxx/init_cpus.c" |
| 129 | #include "cpu/amd/model_10xxx/fidvid.c" |
| 130 | |
| 131 | #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ |
| 132 | |
| 133 | |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 134 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 135 | #include "southbridge/amd/sb700/sb700_early_setup.c" |
| 136 | |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 137 | #if (CONFIG_USE_FAILOVER_IMAGE==0) |
| 138 | //#include "spd_addr.h" |
| 139 | #include "cpu/amd/microcode/microcode.c" |
| 140 | #include "cpu/amd/model_10xxx/update_microcode.c" |
| 141 | |
| 142 | #define RC00 0 |
| 143 | #define RC01 1 |
| 144 | |
| 145 | #define DIMM0 0x50 |
| 146 | #define DIMM1 0x51 |
| 147 | #define DIMM2 0x52 |
| 148 | #define DIMM3 0x53 |
| 149 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame^] | 150 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 151 | { |
| 152 | |
| 153 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 154 | static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; |
| 155 | u32 bsp_apicid = 0; |
| 156 | u32 val; |
| 157 | msr_t msr; |
| 158 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame^] | 159 | if (!((cpu_init_detectedx) || (!boot_cpu()))) { |
| 160 | /* Nothing special needs to be done to find bus 0 */ |
| 161 | /* Allow the HT devices to be found */ |
| 162 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 163 | set_bsp_node_CHtExtNodeCfgEn(); |
| 164 | enumerate_ht_chain(); |
| 165 | |
| 166 | sb700_pci_port80(); |
| 167 | } |
| 168 | |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 169 | post_code(0x30); |
| 170 | |
| 171 | if (bist == 0) { |
| 172 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ |
| 173 | /* All cores run this but the BSP(node0,core0) is the only core that returns. */ |
| 174 | } |
| 175 | |
| 176 | post_code(0x32); |
| 177 | |
| 178 | enable_rs780_dev8(); |
| 179 | sb700_lpc_init(); |
| 180 | |
| 181 | it8718f_enable_serial(0, CONFIG_TTYS0_BASE); |
| 182 | uart_init(); |
| 183 | console_init(); |
| 184 | printk_debug("\n"); |
| 185 | |
| 186 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
| 187 | |
| 188 | /* Halt if there was a built in self test failure */ |
| 189 | report_bist_failure(bist); |
| 190 | |
| 191 | // Load MPB |
| 192 | val = cpuid_eax(1); |
| 193 | printk_debug("BSP Family_Model: %08x \n", val); |
| 194 | printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); |
| 195 | printk_debug("bsp_apicid = %02x \n", bsp_apicid); |
| 196 | printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); |
| 197 | |
| 198 | /* Setup sysinfo defaults */ |
| 199 | set_sysinfo_in_ram(0); |
| 200 | |
| 201 | update_microcode(val); |
| 202 | post_code(0x33); |
| 203 | |
| 204 | cpuSetAMDMSR(); |
| 205 | post_code(0x34); |
| 206 | |
| 207 | amd_ht_init(sysinfo); |
| 208 | post_code(0x35); |
| 209 | |
| 210 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 211 | finalize_node_setup(sysinfo); |
| 212 | |
| 213 | /* Setup any mainboard PCI settings etc. */ |
| 214 | setup_mb_resource_map(); |
| 215 | post_code(0x36); |
| 216 | |
| 217 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 218 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 219 | It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 220 | I think it could be done by putting the spinlock flag in the cache |
| 221 | of the BSP located right after sysinfo. |
| 222 | */ |
| 223 | wait_all_core0_started(); |
| 224 | |
| 225 | #if CONFIG_LOGICAL_CPUS==1 |
| 226 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 227 | printk_debug("start_other_cores()\n"); |
| 228 | start_other_cores(); |
| 229 | post_code(0x37); |
| 230 | wait_all_other_cores_started(bsp_apicid); |
| 231 | #endif |
| 232 | |
| 233 | post_code(0x38); |
| 234 | |
| 235 | /* run _early_setup before soft-reset. */ |
| 236 | rs780_early_setup(); |
| 237 | sb700_early_setup(); |
| 238 | |
| 239 | #if FAM10_SET_FIDVID == 1 |
| 240 | msr = rdmsr(0xc0010071); |
| 241 | printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
| 242 | |
| 243 | /* FIXME: The sb fid change may survive the warm reset and only |
| 244 | need to be done once.*/ |
| 245 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 246 | |
| 247 | post_code(0x39); |
| 248 | |
| 249 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 250 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 251 | } else { |
| 252 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 253 | } |
| 254 | |
| 255 | post_code(0x3A); |
| 256 | |
| 257 | /* show final fid and vid */ |
| 258 | msr=rdmsr(0xc0010071); |
| 259 | printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
| 260 | #endif |
| 261 | |
| 262 | rs780_htinit(); |
| 263 | |
| 264 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 265 | if (!warm_reset_detect(0)) { |
| 266 | print_info("...WARM RESET...\n\n\n"); |
| 267 | soft_reset(); |
| 268 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 269 | } |
| 270 | |
| 271 | post_code(0x3B); |
| 272 | |
| 273 | /* It's the time to set ctrl in sysinfo now; */ |
| 274 | printk_debug("fill_mem_ctrl()\n"); |
| 275 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 276 | post_code(0x3D); |
| 277 | |
| 278 | memreset_setup(); |
| 279 | post_code(0x40); |
| 280 | |
| 281 | // die("Die Before MCT init."); |
| 282 | |
| 283 | printk_debug("raminit_amdmct()\n"); |
| 284 | raminit_amdmct(sysinfo); |
| 285 | post_code(0x41); |
| 286 | |
| 287 | /* |
| 288 | dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); |
| 289 | dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); |
| 290 | dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); |
| 291 | dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); |
| 292 | */ |
| 293 | |
| 294 | // ram_check(0x00200000, 0x00200000 + (640 * 1024)); |
| 295 | // ram_check(0x40200000, 0x40200000 + (640 * 1024)); |
| 296 | |
| 297 | |
| 298 | // die("After MCT init before CAR disabled."); |
| 299 | |
| 300 | rs780_before_pci_init(); |
| 301 | sb700_before_pci_init(); |
| 302 | |
| 303 | post_code(0x42); |
| 304 | printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); |
| 305 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 306 | post_code(0x43); // Should never see this post code. |
| 307 | } |
| 308 | |
| 309 | |
| 310 | #endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ |